| 1 | /** @file
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| 2 | * MM - The Memory Manager.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2007 innotek GmbH
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_mm_h
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| 27 | #define ___VBox_mm_h
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| 28 |
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| 29 | #include <VBox/cdefs.h>
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| 30 | #include <VBox/types.h>
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| 31 | #include <VBox/x86.h>
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| 32 | #include <VBox/sup.h>
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| 33 |
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| 34 |
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| 35 | __BEGIN_DECLS
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| 36 |
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| 37 | /** @defgroup grp_mm The Memory Manager API
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| 38 | * @{
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| 39 | */
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| 40 |
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| 41 | /** @name RAM Page Flags
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| 42 | * Since internal ranges have a byte granularity it's possible for a
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| 43 | * page be flagged for several uses. The access virtualization in PGM
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| 44 | * will choose the most restricted one and use EM to emulate access to
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| 45 | * the less restricted areas of the page.
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| 46 | *
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| 47 | * Bits 0-11 only since they are fitted into the offset part of a physical memory address.
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| 48 | * @{
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| 49 | */
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| 50 | /** Reserved - Not RAM, ROM nor MMIO2.
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| 51 | * If this bit is cleared the memory is assumed to be some kind of RAM.
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| 52 | * Normal MMIO may set it but that depends on whether the RAM range was
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| 53 | * created specially for the MMIO or not.
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| 54 | *
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| 55 | * @remarks The current implementation will always reserve backing
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| 56 | * memory for reserved ranges to simplify things.
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| 57 | */
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| 58 | #define MM_RAM_FLAGS_RESERVED RT_BIT(0)
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| 59 | /** ROM - Read Only Memory.
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| 60 | * The page have a HC physical address which contains the BIOS code. All write
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| 61 | * access is trapped and ignored.
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| 62 | *
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| 63 | * HACK: Writable shadow ROM is indicated by both ROM and MMIO2 being
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| 64 | * set. (We're out of bits.)
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| 65 | */
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| 66 | #define MM_RAM_FLAGS_ROM RT_BIT(1)
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| 67 | /** MMIO - Memory Mapped I/O.
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| 68 | * All access is trapped and emulated. No physical backing is required, but
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| 69 | * might for various reasons be present.
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| 70 | */
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| 71 | #define MM_RAM_FLAGS_MMIO RT_BIT(2)
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| 72 | /** MMIO2 - Memory Mapped I/O, variation 2.
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| 73 | * The virtualization is performed using real memory and only catching
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| 74 | * a few accesses for like keeping track for dirty pages.
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| 75 | * @remark Involved in the shadow ROM hack.
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| 76 | */
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| 77 | #define MM_RAM_FLAGS_MMIO2 RT_BIT(3)
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| 78 |
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| 79 | /** PGM has virtual page access handler(s) defined for pages with this flag. */
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| 80 | #define MM_RAM_FLAGS_VIRTUAL_HANDLER RT_BIT(4)
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| 81 | /** PGM has virtual page access handler(s) for write access. */
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| 82 | #define MM_RAM_FLAGS_VIRTUAL_WRITE RT_BIT(5)
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| 83 | /** PGM has virtual page access handler(s) for all access. */
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| 84 | #define MM_RAM_FLAGS_VIRTUAL_ALL RT_BIT(6)
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| 85 | /** PGM has physical page access handler(s) defined for pages with this flag. */
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| 86 | #define MM_RAM_FLAGS_PHYSICAL_HANDLER RT_BIT(7)
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| 87 | /** PGM has physical page access handler(s) for write access. */
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| 88 | #define MM_RAM_FLAGS_PHYSICAL_WRITE RT_BIT(8)
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| 89 | /** PGM has physical page access handler(s) for all access. */
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| 90 | #define MM_RAM_FLAGS_PHYSICAL_ALL RT_BIT(9)
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| 91 | /** PGM has physical page access handler(s) for this page and has temporarily disabled it. */
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| 92 | #define MM_RAM_FLAGS_PHYSICAL_TEMP_OFF RT_BIT(10)
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| 93 | #ifndef VBOX_WITH_NEW_PHYS_CODE
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| 94 | /** Physical backing memory is allocated dynamically. Not set implies a one time static allocation. */
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| 95 | #define MM_RAM_FLAGS_DYNAMIC_ALLOC RT_BIT(11)
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| 96 | #endif /* !VBOX_WITH_NEW_PHYS_CODE */
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| 97 |
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| 98 | /** The shift used to get the reference count. */
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| 99 | #define MM_RAM_FLAGS_CREFS_SHIFT 62
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| 100 | /** The mask applied to the the page pool idx after using MM_RAM_FLAGS_CREFS_SHIFT to shift it down. */
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| 101 | #define MM_RAM_FLAGS_CREFS_MASK 0x3
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| 102 | /** The (shifted) cRef value used to indiciate that the idx is the head of a
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| 103 | * physical cross reference extent list. */
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| 104 | #define MM_RAM_FLAGS_CREFS_PHYSEXT MM_RAM_FLAGS_CREFS_MASK
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| 105 | /** The shift used to get the page pool idx. (Apply MM_RAM_FLAGS_IDX_MASK to the result when shifting down). */
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| 106 | #define MM_RAM_FLAGS_IDX_SHIFT 48
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| 107 | /** The mask applied to the the page pool idx after using MM_RAM_FLAGS_IDX_SHIFT to shift it down. */
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| 108 | #define MM_RAM_FLAGS_IDX_MASK 0x3fff
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| 109 | /** The idx value when we're out of of extents or there are simply too many mappings of this page. */
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| 110 | #define MM_RAM_FLAGS_IDX_OVERFLOWED MM_RAM_FLAGS_IDX_MASK
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| 111 |
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| 112 | /** Mask for masking off any references to the page. */
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| 113 | #define MM_RAM_FLAGS_NO_REFS_MASK UINT64_C(0x0000ffffffffffff)
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| 114 | /** @} */
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| 115 |
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| 116 | #ifndef VBOX_WITH_NEW_PHYS_CODE
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| 117 | /** @name MMR3PhysRegisterEx registration type
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| 118 | * @{
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| 119 | */
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| 120 | typedef enum
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| 121 | {
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| 122 | /** Normal physical region (flags specify exact page type) */
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| 123 | MM_PHYS_TYPE_NORMAL = 0,
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| 124 | /** Allocate part of a dynamically allocated physical region */
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| 125 | MM_PHYS_TYPE_DYNALLOC_CHUNK,
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| 126 |
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| 127 | MM_PHYS_TYPE_32BIT_HACK = 0x7fffffff
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| 128 | } MMPHYSREG;
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| 129 | /** @} */
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| 130 | #endif
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| 131 |
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| 132 | /**
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| 133 | * Memory Allocation Tags.
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| 134 | * For use with MMHyperAlloc(), MMR3HeapAlloc(), MMR3HeapAllocEx(),
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| 135 | * MMR3HeapAllocZ() and MMR3HeapAllocZEx().
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| 136 | *
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| 137 | * @remark Don't forget to update the dump command in MMHeap.cpp!
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| 138 | */
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| 139 | typedef enum MMTAG
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| 140 | {
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| 141 | MM_TAG_INVALID = 0,
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| 142 |
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| 143 | MM_TAG_CFGM,
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| 144 | MM_TAG_CFGM_BYTES,
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| 145 | MM_TAG_CFGM_STRING,
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| 146 | MM_TAG_CFGM_USER,
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| 147 |
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| 148 | MM_TAG_CSAM,
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| 149 | MM_TAG_CSAM_PATCH,
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| 150 |
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| 151 | MM_TAG_DBGF,
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| 152 | MM_TAG_DBGF_INFO,
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| 153 | MM_TAG_DBGF_LINE,
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| 154 | MM_TAG_DBGF_LINE_DUP,
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| 155 | MM_TAG_DBGF_STACK,
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| 156 | MM_TAG_DBGF_SYMBOL,
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| 157 | MM_TAG_DBGF_SYMBOL_DUP,
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| 158 | MM_TAG_DBGF_MODULE,
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| 159 |
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| 160 | MM_TAG_EM,
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| 161 |
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| 162 | MM_TAG_IOM,
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| 163 | MM_TAG_IOM_STATS,
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| 164 |
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| 165 | MM_TAG_MM,
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| 166 | MM_TAG_MM_LOOKUP_GUEST,
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| 167 | MM_TAG_MM_LOOKUP_PHYS,
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| 168 | MM_TAG_MM_LOOKUP_VIRT,
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| 169 | MM_TAG_MM_PAGE,
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| 170 |
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| 171 | MM_TAG_PATM,
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| 172 | MM_TAG_PATM_PATCH,
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| 173 |
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| 174 | MM_TAG_PDM,
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| 175 | MM_TAG_PDM_ASYNC_COMPLETION,
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| 176 | MM_TAG_PDM_DEVICE,
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| 177 | MM_TAG_PDM_DEVICE_USER,
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| 178 | MM_TAG_PDM_DRIVER,
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| 179 | MM_TAG_PDM_DRIVER_USER,
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| 180 | MM_TAG_PDM_USB,
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| 181 | MM_TAG_PDM_USB_USER,
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| 182 | MM_TAG_PDM_LUN,
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| 183 | MM_TAG_PDM_QUEUE,
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| 184 | MM_TAG_PDM_THREAD,
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| 185 |
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| 186 | MM_TAG_PGM,
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| 187 | MM_TAG_PGM_CHUNK_MAPPING,
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| 188 | MM_TAG_PGM_HANDLERS,
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| 189 | MM_TAG_PGM_PHYS,
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| 190 | MM_TAG_PGM_POOL,
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| 191 |
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| 192 | MM_TAG_REM,
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| 193 |
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| 194 | MM_TAG_SELM,
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| 195 |
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| 196 | MM_TAG_SSM,
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| 197 |
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| 198 | MM_TAG_STAM,
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| 199 |
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| 200 | MM_TAG_TM,
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| 201 |
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| 202 | MM_TAG_TRPM,
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| 203 |
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| 204 | MM_TAG_VM,
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| 205 | MM_TAG_VM_REQ,
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| 206 |
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| 207 | MM_TAG_VMM,
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| 208 |
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| 209 | MM_TAG_HWACCM,
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| 210 |
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| 211 | MM_TAG_32BIT_HACK = 0x7fffffff
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| 212 | } MMTAG;
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| 213 |
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| 214 |
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| 215 |
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| 216 |
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| 217 | /** @defgroup grp_mm_hyper Hypervisor Memory Management
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| 218 | * @ingroup grp_mm
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| 219 | * @{ */
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| 220 |
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| 221 | MMDECL(RTR3PTR) MMHyperR0ToR3(PVM pVM, RTR0PTR R0Ptr);
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| 222 | MMDECL(RTGCPTR) MMHyperR0ToGC(PVM pVM, RTR0PTR R0Ptr);
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| 223 | #ifndef IN_RING0
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| 224 | MMDECL(void *) MMHyperR0ToCC(PVM pVM, RTR0PTR R0Ptr);
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| 225 | #endif
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| 226 | MMDECL(RTR0PTR) MMHyperR3ToR0(PVM pVM, RTR3PTR R3Ptr);
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| 227 | MMDECL(RTGCPTR) MMHyperR3ToGC(PVM pVM, RTR3PTR R3Ptr);
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| 228 | MMDECL(RTR3PTR) MMHyperGCToR3(PVM pVM, RTGCPTR GCPtr);
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| 229 | MMDECL(RTR0PTR) MMHyperGCToR0(PVM pVM, RTGCPTR GCPtr);
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| 230 |
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| 231 | #ifndef IN_RING3
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| 232 | MMDECL(void *) MMHyperR3ToCC(PVM pVM, RTR3PTR R3Ptr);
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| 233 | #else
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| 234 | DECLINLINE(void *) MMHyperR3ToCC(PVM pVM, RTR3PTR R3Ptr)
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| 235 | {
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| 236 | NOREF(pVM);
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| 237 | return R3Ptr;
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| 238 | }
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| 239 | #endif
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| 240 |
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| 241 |
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| 242 | #ifndef IN_GC
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| 243 | MMDECL(void *) MMHyperGCToCC(PVM pVM, RTGCPTR GCPtr);
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| 244 | #else
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| 245 | DECLINLINE(void *) MMHyperGCToCC(PVM pVM, RTGCPTR GCPtr)
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| 246 | {
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| 247 | NOREF(pVM);
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| 248 | return GCPtr;
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| 249 | }
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| 250 | #endif
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| 251 |
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| 252 | #ifndef IN_RING3
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| 253 | MMDECL(RTR3PTR) MMHyperCCToR3(PVM pVM, void *pv);
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| 254 | #else
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| 255 | DECLINLINE(RTR3PTR) MMHyperCCToR3(PVM pVM, void *pv)
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| 256 | {
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| 257 | NOREF(pVM);
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| 258 | return pv;
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| 259 | }
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| 260 | #endif
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| 261 |
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| 262 | #ifndef IN_RING0
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| 263 | MMDECL(RTR0PTR) MMHyperCCToR0(PVM pVM, void *pv);
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| 264 | #else
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| 265 | DECLINLINE(RTR0PTR) MMHyperCCToR0(PVM pVM, void *pv)
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| 266 | {
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| 267 | NOREF(pVM);
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| 268 | return pv;
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| 269 | }
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| 270 | #endif
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| 271 |
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| 272 | #ifndef IN_GC
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| 273 | MMDECL(RTGCPTR) MMHyperCCToGC(PVM pVM, void *pv);
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| 274 | #else
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| 275 | DECLINLINE(RTGCPTR) MMHyperCCToGC(PVM pVM, void *pv)
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| 276 | {
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| 277 | NOREF(pVM);
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| 278 | return pv;
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| 279 | }
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| 280 | #endif
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| 281 |
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| 282 |
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| 283 | #ifdef IN_GC
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| 284 | MMDECL(RTHCPTR) MMHyper2HC(PVM pVM, uintptr_t Ptr);
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| 285 | #else
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| 286 | DECLINLINE(RTHCPTR) MMHyper2HC(PVM pVM, uintptr_t Ptr)
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| 287 | {
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| 288 | NOREF(pVM);
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| 289 | return (RTHCPTR)Ptr;
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| 290 | }
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| 291 | #endif
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| 292 |
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| 293 | #ifndef IN_GC
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| 294 | MMDECL(RTGCPTR) MMHyper2GC(PVM pVM, uintptr_t Ptr);
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| 295 | #else
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| 296 | DECLINLINE(RTGCPTR) MMHyper2GC(PVM pVM, uintptr_t Ptr)
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| 297 | {
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| 298 | NOREF(pVM);
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| 299 | return (RTGCPTR)Ptr;
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| 300 | }
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| 301 | #endif
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| 302 |
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| 303 | MMDECL(RTGCPTR) MMHyperHC2GC(PVM pVM, RTHCPTR HCPtr);
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| 304 | MMDECL(RTHCPTR) MMHyperGC2HC(PVM pVM, RTGCPTR GCPtr);
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| 305 | MMDECL(int) MMHyperAlloc(PVM pVM, size_t cb, uint32_t uAlignment, MMTAG enmTag, void **ppv);
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| 306 | MMDECL(int) MMHyperFree(PVM pVM, void *pv);
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| 307 | #ifdef DEBUG
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| 308 | MMDECL(void) MMHyperHeapDump(PVM pVM);
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| 309 | #endif
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| 310 | MMDECL(size_t) MMHyperHeapGetFreeSize(PVM pVM);
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| 311 | MMDECL(size_t) MMHyperHeapGetSize(PVM pVM);
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| 312 | MMDECL(RTGCPTR) MMHyperGetArea(PVM pVM, size_t *pcb);
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| 313 | MMDECL(bool) MMHyperIsInsideArea(PVM pVM, RTGCPTR GCPtr);
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| 314 |
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| 315 |
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| 316 | MMDECL(RTHCPHYS) MMPage2Phys(PVM pVM, void *pvPage);
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| 317 | MMDECL(void *) MMPagePhys2Page(PVM pVM, RTHCPHYS HCPhysPage);
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| 318 | MMDECL(int) MMPagePhys2PageEx(PVM pVM, RTHCPHYS HCPhysPage, void **ppvPage);
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| 319 | MMDECL(int) MMPagePhys2PageTry(PVM pVM, RTHCPHYS HCPhysPage, void **ppvPage);
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| 320 | MMDECL(void *) MMPhysGCPhys2HCVirt(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
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| 321 |
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| 322 |
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| 323 | /** @def MMHYPER_GC_ASSERT_GCPTR
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| 324 | * Asserts that an address is either NULL or inside the hypervisor memory area.
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| 325 | * This assertion only works while IN_GC, it's a NOP everywhere else.
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| 326 | * @thread The Emulation Thread.
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| 327 | */
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| 328 | #ifdef IN_GC
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| 329 | # define MMHYPER_GC_ASSERT_GCPTR(pVM, GCPtr) Assert(MMHyperIsInsideArea((pVM), (GCPtr)) || !(GCPtr))
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| 330 | #else
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| 331 | # define MMHYPER_GC_ASSERT_GCPTR(pVM, GCPtr) do { } while (0)
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| 332 | #endif
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| 333 |
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| 334 | /** @} */
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| 335 |
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| 336 |
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| 337 | #ifdef IN_RING3
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| 338 | /** @defgroup grp_mm_r3 The MM Host Context Ring-3 API
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| 339 | * @ingroup grp_mm
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| 340 | * @{
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| 341 | */
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| 342 |
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| 343 | MMR3DECL(int) MMR3InitUVM(PUVM pUVM);
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| 344 | MMR3DECL(int) MMR3Init(PVM pVM);
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| 345 | MMR3DECL(int) MMR3InitPaging(PVM pVM);
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| 346 | MMR3DECL(int) MMR3HyperInitFinalize(PVM pVM);
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| 347 | MMR3DECL(int) MMR3Term(PVM pVM);
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| 348 | MMR3DECL(void) MMR3TermUVM(PUVM pUVM);
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| 349 | MMR3DECL(void) MMR3Reset(PVM pVM);
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| 350 | MMR3DECL(int) MMR3IncreaseBaseReservation(PVM pVM, uint64_t cAddBasePages);
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| 351 | MMR3DECL(int) MMR3IncreaseFixedReservation(PVM pVM, uint32_t cAddFixedPages);
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| 352 | MMR3DECL(int) MMR3UpdateShadowReservation(PVM pVM, uint32_t cShadowPages);
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| 353 |
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| 354 | MMR3DECL(int) MMR3HCPhys2HCVirt(PVM pVM, RTHCPHYS HCPhys, void **ppv);
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| 355 | MMR3DECL(int) MMR3ReadGCVirt(PVM pVM, void *pvDst, RTGCPTR GCPtr, size_t cb);
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| 356 | MMR3DECL(int) MMR3WriteGCVirt(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
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| 357 |
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| 358 |
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| 359 | /** @defgroup grp_mm_r3_hyper Hypervisor Memory Manager (HC R3 Portion)
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| 360 | * @ingroup grp_mm_r3
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| 361 | * @{ */
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| 362 | MMDECL(int) MMR3HyperAllocOnceNoRel(PVM pVM, size_t cb, uint32_t uAlignment, MMTAG enmTag, void **ppv);
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| 363 | MMR3DECL(int) MMR3HyperMapHCPhys(PVM pVM, void *pvHC, RTHCPHYS HCPhys, size_t cb, const char *pszDesc, PRTGCPTR pGCPtr);
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| 364 | MMR3DECL(int) MMR3HyperMapGCPhys(PVM pVM, RTGCPHYS GCPhys, size_t cb, const char *pszDesc, PRTGCPTR pGCPtr);
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| 365 | MMR3DECL(int) MMR3HyperMapHCRam(PVM pVM, void *pvHC, size_t cb, bool fFree, const char *pszDesc, PRTGCPTR pGCPtr);
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| 366 | MMR3DECL(int) MMR3HyperMapPages(PVM pVM, void *pvR3, RTR0PTR pvR0, size_t cPages, PCSUPPAGE paPages, const char *pszDesc, PRTGCPTR pGCPtr);
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| 367 | MMR3DECL(int) MMR3HyperReserve(PVM pVM, unsigned cb, const char *pszDesc, PRTGCPTR pGCPtr);
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| 368 | MMR3DECL(RTHCPHYS) MMR3HyperHCVirt2HCPhys(PVM pVM, void *pvHC);
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| 369 | MMR3DECL(int) MMR3HyperHCVirt2HCPhysEx(PVM pVM, void *pvHC, PRTHCPHYS pHCPhys);
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| 370 | MMR3DECL(void *) MMR3HyperHCPhys2HCVirt(PVM pVM, RTHCPHYS HCPhys);
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| 371 | MMR3DECL(int) MMR3HyperHCPhys2HCVirtEx(PVM pVM, RTHCPHYS HCPhys, void **ppv);
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| 372 | MMR3DECL(int) MMR3HyperReadGCVirt(PVM pVM, void *pvDst, RTGCPTR GCPtr, size_t cb);
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| 373 | /** @} */
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| 374 |
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| 375 |
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| 376 | /** @defgroup grp_mm_phys Guest Physical Memory Manager
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| 377 | * @ingroup grp_mm_r3
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| 378 | * @{ */
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| 379 | MMR3DECL(int) MMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, unsigned cb, unsigned fFlags, const char *pszDesc);
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| 380 | #ifndef VBOX_WITH_NEW_PHYS_CODE
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| 381 | MMR3DECL(int) MMR3PhysRegisterEx(PVM pVM, void *pvRam, RTGCPHYS GCPhys, unsigned cb, unsigned fFlags, MMPHYSREG enmType, const char *pszDesc);
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| 382 | #endif
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| 383 | MMR3DECL(int) MMR3PhysRelocate(PVM pVM, RTGCPHYS GCPhysOld, RTGCPHYS GCPhysNew, unsigned cb);
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| 384 | MMR3DECL(int) MMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTUINT cbRange, const void *pvBinary, bool fShadow, const char *pszDesc);
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| 385 | MMR3DECL(int) MMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
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| 386 | MMR3DECL(int) MMR3PhysReserve(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, const char *pszDesc);
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| 387 | MMR3DECL(uint64_t) MMR3PhysGetRamSize(PVM pVM);
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| 388 | /** @} */
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| 389 |
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| 390 |
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| 391 | /** @defgroup grp_mm_page Physical Page Pool
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| 392 | * @ingroup grp_mm_r3
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| 393 | * @{ */
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| 394 | MMR3DECL(void *) MMR3PageAlloc(PVM pVM);
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| 395 | MMR3DECL(RTHCPHYS) MMR3PageAllocPhys(PVM pVM);
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| 396 | MMR3DECL(void) MMR3PageFree(PVM pVM, void *pvPage);
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| 397 | MMR3DECL(void *) MMR3PageAllocLow(PVM pVM);
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| 398 | MMR3DECL(void) MMR3PageFreeLow(PVM pVM, void *pvPage);
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| 399 | MMR3DECL(void) MMR3PageFreeByPhys(PVM pVM, RTHCPHYS HCPhysPage);
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| 400 | MMR3DECL(void *) MMR3PageDummyHCPtr(PVM pVM);
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| 401 | MMR3DECL(RTHCPHYS) MMR3PageDummyHCPhys(PVM pVM);
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| 402 | /** @} */
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| 403 |
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| 404 |
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| 405 | /** @defgroup grp_mm_heap Heap Manager
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| 406 | * @ingroup grp_mm_r3
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| 407 | * @{ */
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| 408 | MMR3DECL(void *) MMR3HeapAlloc(PVM pVM, MMTAG enmTag, size_t cbSize);
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| 409 | MMR3DECL(void *) MMR3HeapAllocU(PUVM pUVM, MMTAG enmTag, size_t cbSize);
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| 410 | MMR3DECL(int) MMR3HeapAllocEx(PVM pVM, MMTAG enmTag, size_t cbSize, void **ppv);
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| 411 | MMR3DECL(int) MMR3HeapAllocExU(PUVM pUVM, MMTAG enmTag, size_t cbSize, void **ppv);
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| 412 | MMR3DECL(void *) MMR3HeapAllocZ(PVM pVM, MMTAG enmTag, size_t cbSize);
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| 413 | MMR3DECL(void *) MMR3HeapAllocZU(PUVM pUVM, MMTAG enmTag, size_t cbSize);
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| 414 | MMR3DECL(int) MMR3HeapAllocZEx(PVM pVM, MMTAG enmTag, size_t cbSize, void **ppv);
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| 415 | MMR3DECL(int) MMR3HeapAllocZExU(PUVM pUVM, MMTAG enmTag, size_t cbSize, void **ppv);
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| 416 | MMR3DECL(void *) MMR3HeapRealloc(void *pv, size_t cbNewSize);
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| 417 | MMR3DECL(char *) MMR3HeapStrDup(PVM pVM, MMTAG enmTag, const char *psz);
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| 418 | MMR3DECL(char *) MMR3HeapStrDupU(PUVM pUVM, MMTAG enmTag, const char *psz);
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| 419 | MMR3DECL(void) MMR3HeapFree(void *pv);
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| 420 | /** @} */
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| 421 |
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| 422 | /** @} */
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| 423 | #endif /* IN_RING3 */
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| 424 |
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| 425 |
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| 426 |
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| 427 | #ifdef IN_GC
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| 428 | /** @defgroup grp_mm_gc The MM Guest Context API
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| 429 | * @ingroup grp_mm
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| 430 | * @{
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| 431 | */
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| 432 |
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| 433 | MMGCDECL(void) MMGCRamRegisterTrapHandler(PVM pVM);
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| 434 | MMGCDECL(void) MMGCRamDeregisterTrapHandler(PVM pVM);
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| 435 | MMGCDECL(int) MMGCRamReadNoTrapHandler(void *pDst, void *pSrc, size_t cb);
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| 436 | MMGCDECL(int) MMGCRamWriteNoTrapHandler(void *pDst, void *pSrc, size_t cb);
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| 437 | MMGCDECL(int) MMGCRamRead(PVM pVM, void *pDst, void *pSrc, size_t cb);
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| 438 | MMGCDECL(int) MMGCRamWrite(PVM pVM, void *pDst, void *pSrc, size_t cb);
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| 439 |
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| 440 | /** @} */
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| 441 | #endif /* IN_GC */
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| 442 |
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| 443 | /** @} */
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| 444 | __END_DECLS
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| 445 |
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| 446 |
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| 447 | #endif
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| 448 |
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