| 1 | /** @file
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| 2 | * MSI - Message signalled interrupts support.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2010 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_msi_h
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| 27 | #define ___VBox_msi_h
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| 28 |
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| 29 | #include <VBox/cdefs.h>
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| 30 | #include <VBox/types.h>
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| 31 | #include <iprt/assert.h>
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| 32 |
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| 33 | #include <VBox/pci.h>
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| 34 |
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| 35 | /* Constants for Intel APIC MSI messages */
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| 36 | #define VBOX_MSI_DATA_VECTOR_SHIFT 0
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| 37 | #define VBOX_MSI_DATA_VECTOR_MASK 0x000000ff
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| 38 | #define VBOX_MSI_DATA_VECTOR(v) (((v) << VBOX_MSI_DATA_VECTOR_SHIFT) & \
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| 39 | VBOX_MSI_DATA_VECTOR_MASK)
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| 40 | #define VBOX_MSI_DATA_DELIVERY_MODE_SHIFT 8
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| 41 | #define VBOX_MSI_DATA_DELIVERY_FIXED (0 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
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| 42 | #define VBOX_MSI_DATA_DELIVERY_LOWPRI (1 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
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| 43 |
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| 44 | #define VBOX_MSI_DATA_LEVEL_SHIFT 14
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| 45 | #define VBOX_MSI_DATA_LEVEL_DEASSERT (0 << VBOX_MSI_DATA_LEVEL_SHIFT)
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| 46 | #define VBOX_MSI_DATA_LEVEL_ASSERT (1 << VBOX_MSI_DATA_LEVEL_SHIFT)
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| 47 |
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| 48 | #define VBOX_MSI_DATA_TRIGGER_SHIFT 15
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| 49 | #define VBOX_MSI_DATA_TRIGGER_EDGE (0 << VBOX_MSI_DATA_TRIGGER_SHIFT)
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| 50 | #define VBOX_MSI_DATA_TRIGGER_LEVEL (1 << VBOX_MSI_DATA_TRIGGER_SHIFT)
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| 51 |
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| 52 | /**
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| 53 | * MSI region, actually same as LAPIC MMIO region, but listens on bus,
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| 54 | * not CPU, accesses.
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| 55 | */
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| 56 | #define VBOX_MSI_ADDR_BASE 0xfee00000
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| 57 | #define VBOX_MSI_ADDR_SIZE 0x100000
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| 58 |
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| 59 | #define VBOX_MSI_ADDR_DEST_MODE_SHIFT 2
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| 60 | #define VBOX_MSI_ADDR_DEST_MODE_PHYSICAL (0 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
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| 61 | #define VBOX_MSI_ADDR_DEST_MODE_LOGICAL (1 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
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| 62 |
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| 63 | #define VBOX_MSI_ADDR_REDIRECTION_SHIFT 3
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| 64 | #define VBOX_MSI_ADDR_REDIRECTION_CPU (0 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
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| 65 | /* dedicated cpu */
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| 66 | #define VBOX_MSI_ADDR_REDIRECTION_LOWPRI (1 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
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| 67 | /* lowest priority */
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| 68 |
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| 69 | #define VBOX_MSI_ADDR_DEST_ID_SHIFT 12
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| 70 | #define VBOX_MSI_ADDR_DEST_ID_MASK 0x00ffff0
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| 71 | #define VBOX_MSI_ADDR_DEST_ID(dest) (((dest) << VBOX_MSI_ADDR_DEST_ID_SHIFT) & \
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| 72 | VBOX_MSI_ADDR_DEST_ID_MASK)
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| 73 | #define VBOX_MSI_ADDR_EXT_DEST_ID(dest) ((dest) & 0xffffff00)
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| 74 |
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| 75 | #define VBOX_MSI_ADDR_IR_EXT_INT (1 << 4)
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| 76 | #define VBOX_MSI_ADDR_IR_SHV (1 << 3)
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| 77 | #define VBOX_MSI_ADDR_IR_INDEX1(index) ((index & 0x8000) >> 13)
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| 78 | #define VBOX_MSI_ADDR_IR_INDEX2(index) ((index & 0x7fff) << 5)
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| 79 |
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| 80 | /* Maximum number of vectors, per device/function */
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| 81 | #define VBOX_MSI_MAX_ENTRIES 32
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| 82 |
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| 83 | /* Offsets in MSI PCI capability structure (VBOX_PCI_CAP_ID_MSI) */
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| 84 | #define VBOX_MSI_CAP_MESSAGE_CONTROL 0x02
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| 85 | #define VBOX_MSI_CAP_MESSAGE_ADDRESS_32 0x04
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| 86 | #define VBOX_MSI_CAP_MESSAGE_ADDRESS_LO 0x04
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| 87 | #define VBOX_MSI_CAP_MESSAGE_ADDRESS_HI 0x08
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| 88 | #define VBOX_MSI_CAP_MESSAGE_DATA_32 0x08
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| 89 | #define VBOX_MSI_CAP_MESSAGE_DATA_64 0x0c
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| 90 | #define VBOX_MSI_CAP_MASK_BITS_32 0x0c
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| 91 | #define VBOX_MSI_CAP_PENDING_BITS_32 0x10
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| 92 | #define VBOX_MSI_CAP_MASK_BITS_64 0x10
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| 93 | #define VBOX_MSI_CAP_PENDING_BITS_64 0x14
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| 94 |
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| 95 | /* We implement MSI with per-vector masking */
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| 96 | #define VBOX_MSI_CAP_SIZE_32 0x14
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| 97 | #define VBOX_MSI_CAP_SIZE_64 0x18
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| 98 |
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| 99 | /**
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| 100 | * MSI-X different from MSI by the fact that dedicated physical page
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| 101 | * (in device memory) is assigned for MSI-X table, and Pending Bit Array (PBA),
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| 102 | * which is recommended to be separated from the main table by at least 2K.
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| 103 | */
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| 104 | /* Size of a MSI-X page */
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| 105 | #define VBOX_MSIX_PAGE_SIZE 0x1000
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| 106 | /* Pending interrupts (PBA) */
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| 107 | #define VBOX_MSIX_PAGE_PENDING (VBOX_MSIX_PAGE_SIZE / 2)
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| 108 | /* Maximum number of vectors, per device/function */
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| 109 | #define VBOX_MSIX_MAX_ENTRIES 32
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| 110 | #define VBOX_MSIX_ENTRY_SIZE 16
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| 111 | /* Size of MSI-X PCI capability */
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| 112 | #define VBOX_MSIX_CAP_SIZE 12
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| 113 | /* Offsets in MSI-X PCI capability structure (VBOX_PCI_CAP_ID_MSIX) */
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| 114 | #define VBOX_MSIX_CAP_MESSAGE_CONTROL 0x02
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| 115 | #define VBOX_MSIX_TABLE_BIROFFSET 0x04
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| 116 | #define VBOX_MSIX_PBA_BIROFFSET 0x08
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| 117 | /* Size of single MSI-X table entry */
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| 118 | #define VBOX_MSIX_ENTRY_SIZE 16
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| 119 |
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| 120 |
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| 121 | #endif
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