msi.h@ 89002

Last change on this file since 89002 was 89002, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 VBox/msi.h: Add unions for IOMMU DMAR remappable format and x2APIC format.
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1	/** @file
2	* MSI - Message signalled interrupts support.
3	*/
4
5	/*
6	* Copyright (C) 2010-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_msi_h
27	#define VBOX_INCLUDED_msi_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/cdefs.h>
33	#include <VBox/types.h>
34	#include <iprt/assert.h>
35
36	#include <VBox/pci.h>
37
38	/* Constants for Intel APIC MSI messages */
39	#define VBOX_MSI_DATA_VECTOR_SHIFT 0
40	#define VBOX_MSI_DATA_VECTOR_MASK 0x000000ff
41	#define VBOX_MSI_DATA_VECTOR(v) (((v) << VBOX_MSI_DATA_VECTOR_SHIFT) & \
42	VBOX_MSI_DATA_VECTOR_MASK)
43	#define VBOX_MSI_DATA_DELIVERY_MODE_SHIFT 8
44	#define VBOX_MSI_DATA_DELIVERY_FIXED (0 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
45	#define VBOX_MSI_DATA_DELIVERY_LOWPRI (1 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
46
47	#define VBOX_MSI_DATA_LEVEL_SHIFT 14
48	#define VBOX_MSI_DATA_LEVEL_DEASSERT (0 << VBOX_MSI_DATA_LEVEL_SHIFT)
49	#define VBOX_MSI_DATA_LEVEL_ASSERT (1 << VBOX_MSI_DATA_LEVEL_SHIFT)
50
51	#define VBOX_MSI_DATA_TRIGGER_SHIFT 15
52	#define VBOX_MSI_DATA_TRIGGER_EDGE (0 << VBOX_MSI_DATA_TRIGGER_SHIFT)
53	#define VBOX_MSI_DATA_TRIGGER_LEVEL (1 << VBOX_MSI_DATA_TRIGGER_SHIFT)
54
55	/**
56	* MSI Interrupt Delivery modes.
57	* In accordance with the Intel spec.
58	* See Intel spec. "10.11.2 Message Data Register Format".
59	*/
60	#define VBOX_MSI_DELIVERY_MODE_FIXED (0)
61	#define VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO (1)
62	#define VBOX_MSI_DELIVERY_MODE_SMI (2)
63	#define VBOX_MSI_DELIVERY_MODE_NMI (4)
64	#define VBOX_MSI_DELIVERY_MODE_INIT (5)
65	#define VBOX_MSI_DELIVERY_MODE_EXT_INT (7)
66
67	/**
68	* MSI region, actually same as LAPIC MMIO region, but listens on bus,
69	* not CPU, accesses.
70	*/
71	#define VBOX_MSI_ADDR_BASE 0xfee00000
72	#define VBOX_MSI_ADDR_SIZE 0x100000
73
74	#define VBOX_MSI_ADDR_SHIFT 20
75
76	#define VBOX_MSI_ADDR_DEST_MODE_SHIFT 2
77	#define VBOX_MSI_ADDR_DEST_MODE_PHYSICAL (0 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
78	#define VBOX_MSI_ADDR_DEST_MODE_LOGICAL (1 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
79
80	#define VBOX_MSI_ADDR_REDIRECTION_SHIFT 3
81	#define VBOX_MSI_ADDR_REDIRECTION_CPU (0 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
82	/* dedicated cpu */
83	#define VBOX_MSI_ADDR_REDIRECTION_LOWPRI (1 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
84	/* lowest priority */
85
86	#define VBOX_MSI_ADDR_DEST_ID_SHIFT 12
87	#define VBOX_MSI_ADDR_DEST_ID_MASK 0x00ffff0
88	#define VBOX_MSI_ADDR_DEST_ID(dest) (((dest) << VBOX_MSI_ADDR_DEST_ID_SHIFT) & \
89	VBOX_MSI_ADDR_DEST_ID_MASK)
90	#define VBOX_MSI_ADDR_EXT_DEST_ID(dest) ((dest) & 0xffffff00)
91
92	#define VBOX_MSI_ADDR_IR_EXT_INT (1 << 4)
93	#define VBOX_MSI_ADDR_IR_SHV (1 << 3)
94	#define VBOX_MSI_ADDR_IR_INDEX1(index) ((index & 0x8000) >> 13)
95	#define VBOX_MSI_ADDR_IR_INDEX2(index) ((index & 0x7fff) << 5)
96
97	/* Maximum number of vectors, per device/function */
98	#define VBOX_MSI_MAX_ENTRIES 32
99
100	/* Offsets in MSI PCI capability structure (VBOX_PCI_CAP_ID_MSI) */
101	#define VBOX_MSI_CAP_MESSAGE_CONTROL 0x02
102	#define VBOX_MSI_CAP_MESSAGE_ADDRESS_32 0x04
103	#define VBOX_MSI_CAP_MESSAGE_ADDRESS_LO 0x04
104	#define VBOX_MSI_CAP_MESSAGE_ADDRESS_HI 0x08
105	#define VBOX_MSI_CAP_MESSAGE_DATA_32 0x08
106	#define VBOX_MSI_CAP_MESSAGE_DATA_64 0x0c
107	#define VBOX_MSI_CAP_MASK_BITS_32 0x0c
108	#define VBOX_MSI_CAP_PENDING_BITS_32 0x10
109	#define VBOX_MSI_CAP_MASK_BITS_64 0x10
110	#define VBOX_MSI_CAP_PENDING_BITS_64 0x14
111
112	/* We implement MSI with per-vector masking */
113	#define VBOX_MSI_CAP_SIZE_32 0x14
114	#define VBOX_MSI_CAP_SIZE_64 0x18
115
116	/**
117	* MSI-X differs from MSI by the fact that a dedicated physical page (in device
118	* memory) is assigned for MSI-X table, and Pending Bit Array (PBA), which is
119	* recommended to be separated from the main table by at least 2K.
120	*
121	* @{
122	*/
123	/** Size of a MSI-X page */
124	#define VBOX_MSIX_PAGE_SIZE 0x1000
125	/** Pending interrupts (PBA) */
126	#define VBOX_MSIX_PAGE_PENDING (VBOX_MSIX_PAGE_SIZE / 2)
127	/** Maximum number of vectors, per device/function */
128	#define VBOX_MSIX_MAX_ENTRIES 2048
129	/** Size of MSI-X PCI capability */
130	#define VBOX_MSIX_CAP_SIZE 12
131	/** Offsets in MSI-X PCI capability structure (VBOX_PCI_CAP_ID_MSIX) */
132	#define VBOX_MSIX_CAP_MESSAGE_CONTROL 0x02
133	#define VBOX_MSIX_TABLE_BIROFFSET 0x04
134	#define VBOX_MSIX_PBA_BIROFFSET 0x08
135	/** Size of single MSI-X table entry */
136	#define VBOX_MSIX_ENTRY_SIZE 16
137	/** @} */
138
139	/**
140	* MSI Address Register.
141	*/
142	typedef union MSIADDR
143	{
144	/*
145	* Intel and AMD xAPIC format.
146	* See Intel spec. 10.11.1 "Message Address Register Format".
147	* This also conforms to the AMD IOMMU spec. which omits specifying
148	* individual fields but specifies reserved bits.
149	*/
150	struct
151	{
152	uint32_t u2Ign0 : 2; /*< Bits 1:0 - Ignored (read as 0, writes ignored). /
153	uint32_t u1DestMode : 1; /*< Bit 2 - DM: Destination Mode. /
154	uint32_t u1RedirHint : 1; /*< Bit 3 - RH: Redirection Hint. /
155	uint32_t u8Rsvd0 : 8; /*< Bits 11:4 - Reserved. /
156	uint32_t u8DestId : 8; /*< Bits 19:12 - Destination Id. /
157	uint32_t u12Addr : 12; /*< Bits 31:20 - Address. /
158	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
159	} n;
160
161	/*
162	* Intel x2APIC Format.
163	* See Intel VT-d spec. 5.1.6.2 "Programming in Intel 64 x2APIC Mode".
164	*/
165	struct
166	{
167	uint32_t u2Ign0 : 2; /*< Bits 1:0 - Ignored (read as 0, writes ignored). /
168	uint32_t u1DestMode : 1; /*< Bit 2 - DM: Destination Mode. /
169	uint32_t u1RedirHint : 1; /*< Bit 3 - RH: Redirection Hint. /
170	uint32_t u8Rsvd0 : 8; /*< Bits 11:4 - Reserved. /
171	uint32_t u8DestIdLo : 8; /*< Bits 19:12 - Destination Id (bits 7:0). /
172	uint32_t u12Addr : 12; /*< Bits 31:20 - Address. /
173	uint32_t u8Rsvd : 8; /*< Bits 39:32 - Reserved. /
174	uint32_t u24DestIdHi : 24; /*< Bits 63:40 - Destination Id (bits 31:8). /
175	} x2apic;
176
177	/*
178	* Intel IOMMU Remappable Interrupt Format.
179	* See Intel VT-d spec. 5.1.2.2 "Interrupt Requests in Remappable Format".
180	*/
181	struct
182	{
183	uint32_t u2Ign0 : 2; /*< Bits 1:0 - Ignored (read as 0, writes ignored). /
184	uint32_t u1IntrIndexHi : 1; /*< Bit 2 - Interrupt Index[15]. /
185	uint32_t fShv : 1; /*< Bit 3 - Sub-Handle Valid. /
186	uint32_t fIntrFormat : 1; /*< Bit 4 - Interrupt Format (1=remappable, 0=compatibility). /
187	uint32_t u14IntrIndexLo : 15; /*< Bits 19:5 - Interrupt Index[14:0]. /
188	uint32_t u12Addr : 12; /*< Bits 31:20 - Address. /
189	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
190	} dmar_remap;
191
192	/** The 32-bit unsigned integer view. */
193	uint32_t au32[2];
194
195	/** The 64-bit unsigned integer view. */
196	uint64_t u64;
197	} MSIADDR;
198	AssertCompileSize(MSIADDR, 8);
199	/** Pointer to an MSI address register. */
200	typedef MSIADDR *PMSIADDR;
201	/** Pointer to a const MSI address register. */
202	typedef MSIADDR const *PCMSIADDR;
203
204	/** Mask of valid bits in the MSI address register. According to the AMD IOMMU spec.
205	* and presumably the PCI spec., the top 32-bits are not reserved. From a PCI/IOMMU
206	* standpoint this makes sense. However, when dealing with the CPU side of things
207	* we might want to ensure the upper bits are reserved. Does x86/x64 really
208	* support a 64-bit MSI address? */
209	#define VBOX_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
210	#define VBOX_MSI_ADDR_ADDR_MASK UINT64_C(0x00000000fff00000)
211
212	/**
213	* MSI Data Register.
214	*/
215	typedef union MSIDATA
216	{
217	/*
218	* Intel and AMD xAPIC format.
219	* See Intel spec. 10.11.2 "Message Data Register Format".
220	* This also conforms to the AMD IOMMU spec. which omits specifying
221	* individual fields but specifies reserved bits.
222	*/
223	struct
224	{
225	uint32_t u8Vector : 8; /*< Bits 7:0 - Vector. /
226	uint32_t u3DeliveryMode : 3; /*< Bits 10:8 - Delivery Mode. /
227	uint32_t u3Rsvd0 : 3; /*< Bits 13:11 - Reserved. /
228	uint32_t u1Level : 1; /*< Bit 14 - Level. /
229	uint32_t u1TriggerMode : 1; /*< Bit 15 - Trigger Mode (0=edge, 1=level). /
230	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
231	} n;
232
233	/*
234	* Intel x2APIC Format.
235	* See Intel VT-d spec. 5.1.6.2 "Programming in Intel 64 x2APIC Mode".
236	*/
237	struct
238	{
239	uint32_t u8Vector : 8; /*< Bits 7:0 - Vector. /
240	uint32_t u1DeliveryMode : 1; /*< Bit 8 - Delivery Mode (0=fixed, 1=lowest priority). /
241	uint32_t u23Rsvd0 : 23; /*< Bits 31:9 - Reserved. /
242	} x2apic;
243
244	/*
245	* Intel IOMMU Remappable Interrupt Format.
246	* See Intel VT-d spec. 5.1.2.2 "Interrupt Requests in Remappable Format".
247	*/
248	struct
249	{
250	uint16_t u16SubHandle;
251	uint16_t u16Rsvd0;
252	} dmar_remap;
253
254	/** The 32-bit unsigned integer view. */
255	uint32_t u32;
256	} MSIDATA;
257	AssertCompileSize(MSIDATA, 4);
258	/** Pointer to an MSI data register. */
259	typedef MSIDATA *PMSIDATA;
260	/** Pointer to a const MSI data register. */
261	typedef MSIDATA const *PCMSIDATA;
262
263	/** Mask of valid bits in the MSI data register. */
264	#define VBOX_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
265
266	/**
267	* MSI Message (Address and Data Register Pair).
268	*/
269	typedef struct MSIMSG
270	{
271	/** The MSI Address Register. */
272	MSIADDR Addr;
273	/** The MSI Data Register. */
274	MSIDATA Data;
275	} MSIMSG;
276
277	#endif /* !VBOX_INCLUDED_msi_h */

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source: vbox/trunk/include/VBox/msi.h@ 89002

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