VirtualBox

source: vbox/trunk/include/VBox/msi.h@ 99547

Last change on this file since 99547 was 98103, checked in by vboxsync, 2 years ago

Copyright year updates by scm.

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1/** @file
2 * MSI - Message signalled interrupts support.
3 */
4
5/*
6 * Copyright (C) 2010-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_msi_h
37#define VBOX_INCLUDED_msi_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/cdefs.h>
43#include <VBox/types.h>
44#include <iprt/assert.h>
45
46#include <VBox/pci.h>
47
48/* Constants for Intel APIC MSI messages */
49#define VBOX_MSI_DATA_VECTOR_SHIFT 0
50#define VBOX_MSI_DATA_VECTOR_MASK 0x000000ff
51#define VBOX_MSI_DATA_VECTOR(v) (((v) << VBOX_MSI_DATA_VECTOR_SHIFT) & \
52 VBOX_MSI_DATA_VECTOR_MASK)
53#define VBOX_MSI_DATA_DELIVERY_MODE_SHIFT 8
54#define VBOX_MSI_DATA_DELIVERY_FIXED (0 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
55#define VBOX_MSI_DATA_DELIVERY_LOWPRI (1 << VBOX_MSI_DATA_DELIVERY_MODE_SHIFT)
56
57#define VBOX_MSI_DATA_LEVEL_SHIFT 14
58#define VBOX_MSI_DATA_LEVEL_DEASSERT (0 << VBOX_MSI_DATA_LEVEL_SHIFT)
59#define VBOX_MSI_DATA_LEVEL_ASSERT (1 << VBOX_MSI_DATA_LEVEL_SHIFT)
60
61#define VBOX_MSI_DATA_TRIGGER_SHIFT 15
62#define VBOX_MSI_DATA_TRIGGER_EDGE (0 << VBOX_MSI_DATA_TRIGGER_SHIFT)
63#define VBOX_MSI_DATA_TRIGGER_LEVEL (1 << VBOX_MSI_DATA_TRIGGER_SHIFT)
64
65/**
66 * MSI Interrupt Delivery modes.
67 * In accordance with the Intel spec.
68 * See Intel spec. "10.11.2 Message Data Register Format".
69 */
70#define VBOX_MSI_DELIVERY_MODE_FIXED (0)
71#define VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO (1)
72#define VBOX_MSI_DELIVERY_MODE_SMI (2)
73#define VBOX_MSI_DELIVERY_MODE_NMI (4)
74#define VBOX_MSI_DELIVERY_MODE_INIT (5)
75#define VBOX_MSI_DELIVERY_MODE_EXT_INT (7)
76
77/**
78 * MSI region, actually same as LAPIC MMIO region, but listens on bus,
79 * not CPU, accesses.
80 */
81#define VBOX_MSI_ADDR_BASE 0xfee00000
82#define VBOX_MSI_ADDR_SIZE 0x100000
83
84#define VBOX_MSI_ADDR_SHIFT 20
85
86#define VBOX_MSI_ADDR_DEST_MODE_SHIFT 2
87#define VBOX_MSI_ADDR_DEST_MODE_PHYSICAL (0 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
88#define VBOX_MSI_ADDR_DEST_MODE_LOGICAL (1 << VBOX_MSI_ADDR_DEST_MODE_SHIFT)
89
90#define VBOX_MSI_ADDR_REDIRECTION_SHIFT 3
91#define VBOX_MSI_ADDR_REDIRECTION_CPU (0 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
92 /* dedicated cpu */
93#define VBOX_MSI_ADDR_REDIRECTION_LOWPRI (1 << VBOX_MSI_ADDR_REDIRECTION_SHIFT)
94 /* lowest priority */
95
96#define VBOX_MSI_ADDR_DEST_ID_SHIFT 12
97#define VBOX_MSI_ADDR_DEST_ID_MASK 0x00ffff0
98#define VBOX_MSI_ADDR_DEST_ID(dest) (((dest) << VBOX_MSI_ADDR_DEST_ID_SHIFT) & \
99 VBOX_MSI_ADDR_DEST_ID_MASK)
100#define VBOX_MSI_ADDR_EXT_DEST_ID(dest) ((dest) & 0xffffff00)
101
102#define VBOX_MSI_ADDR_IR_EXT_INT (1 << 4)
103#define VBOX_MSI_ADDR_IR_SHV (1 << 3)
104#define VBOX_MSI_ADDR_IR_INDEX1(index) ((index & 0x8000) >> 13)
105#define VBOX_MSI_ADDR_IR_INDEX2(index) ((index & 0x7fff) << 5)
106
107/* Maximum number of vectors, per device/function */
108#define VBOX_MSI_MAX_ENTRIES 32
109
110/* Offsets in MSI PCI capability structure (VBOX_PCI_CAP_ID_MSI) */
111#define VBOX_MSI_CAP_MESSAGE_CONTROL 0x02
112#define VBOX_MSI_CAP_MESSAGE_ADDRESS_32 0x04
113#define VBOX_MSI_CAP_MESSAGE_ADDRESS_LO 0x04
114#define VBOX_MSI_CAP_MESSAGE_ADDRESS_HI 0x08
115#define VBOX_MSI_CAP_MESSAGE_DATA_32 0x08
116#define VBOX_MSI_CAP_MESSAGE_DATA_64 0x0c
117#define VBOX_MSI_CAP_MASK_BITS_32 0x0c
118#define VBOX_MSI_CAP_PENDING_BITS_32 0x10
119#define VBOX_MSI_CAP_MASK_BITS_64 0x10
120#define VBOX_MSI_CAP_PENDING_BITS_64 0x14
121
122/* We implement MSI with per-vector masking */
123#define VBOX_MSI_CAP_SIZE_32 0x14
124#define VBOX_MSI_CAP_SIZE_64 0x18
125
126/**
127 * MSI-X differs from MSI by the fact that a dedicated physical page (in device
128 * memory) is assigned for MSI-X table, and Pending Bit Array (PBA), which is
129 * recommended to be separated from the main table by at least 2K.
130 *
131 * @{
132 */
133/** Size of a MSI-X page */
134#define VBOX_MSIX_PAGE_SIZE 0x1000
135/** Pending interrupts (PBA) */
136#define VBOX_MSIX_PAGE_PENDING (VBOX_MSIX_PAGE_SIZE / 2)
137/** Maximum number of vectors, per device/function */
138#define VBOX_MSIX_MAX_ENTRIES 2048
139/** Size of MSI-X PCI capability */
140#define VBOX_MSIX_CAP_SIZE 12
141/** Offsets in MSI-X PCI capability structure (VBOX_PCI_CAP_ID_MSIX) */
142#define VBOX_MSIX_CAP_MESSAGE_CONTROL 0x02
143#define VBOX_MSIX_TABLE_BIROFFSET 0x04
144#define VBOX_MSIX_PBA_BIROFFSET 0x08
145/** Size of single MSI-X table entry */
146#define VBOX_MSIX_ENTRY_SIZE 16
147/** @} */
148
149/**
150 * MSI Address Register.
151 */
152typedef union MSIADDR
153{
154 /*
155 * Intel and AMD xAPIC format.
156 * See Intel spec. 10.11.1 "Message Address Register Format".
157 * This also conforms to the AMD IOMMU spec. which omits specifying
158 * individual fields but specifies reserved bits.
159 */
160 struct
161 {
162 uint32_t u2Ign0 : 2; /**< Bits 1:0 - Ignored (read as 0, writes ignored). */
163 uint32_t u1DestMode : 1; /**< Bit 2 - DM: Destination Mode. */
164 uint32_t u1RedirHint : 1; /**< Bit 3 - RH: Redirection Hint. */
165 uint32_t u8Rsvd0 : 8; /**< Bits 11:4 - Reserved. */
166 uint32_t u8DestId : 8; /**< Bits 19:12 - Destination Id. */
167 uint32_t u12Addr : 12; /**< Bits 31:20 - Address. */
168 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
169 } n;
170
171 /*
172 * Intel x2APIC Format.
173 * See Intel VT-d spec. 5.1.6.2 "Programming in Intel 64 x2APIC Mode".
174 */
175 struct
176 {
177 uint32_t u2Ign0 : 2; /**< Bits 1:0 - Ignored (read as 0, writes ignored). */
178 uint32_t u1DestMode : 1; /**< Bit 2 - DM: Destination Mode. */
179 uint32_t u1RedirHint : 1; /**< Bit 3 - RH: Redirection Hint. */
180 uint32_t u8Rsvd0 : 8; /**< Bits 11:4 - Reserved. */
181 uint32_t u8DestIdLo : 8; /**< Bits 19:12 - Destination Id (bits 7:0). */
182 uint32_t u12Addr : 12; /**< Bits 31:20 - Address. */
183 uint32_t u8Rsvd : 8; /**< Bits 39:32 - Reserved. */
184 uint32_t u24DestIdHi : 24; /**< Bits 63:40 - Destination Id (bits 31:8). */
185 } x2apic;
186
187 /*
188 * Intel IOMMU Remappable Interrupt Format.
189 * See Intel VT-d spec. 5.1.2.2 "Interrupt Requests in Remappable Format".
190 */
191 struct
192 {
193 uint32_t u2Ign0 : 2; /**< Bits 1:0 - Ignored (read as 0, writes ignored). */
194 uint32_t u1IntrIndexHi : 1; /**< Bit 2 - Interrupt Index[15]. */
195 uint32_t fShv : 1; /**< Bit 3 - Sub-Handle Valid. */
196 uint32_t fIntrFormat : 1; /**< Bit 4 - Interrupt Format (1=remappable, 0=compatibility). */
197 uint32_t u14IntrIndexLo : 15; /**< Bits 19:5 - Interrupt Index[14:0]. */
198 uint32_t u12Addr : 12; /**< Bits 31:20 - Address. */
199 uint32_t u32Rsvd0; /**< Bits 63:32 - Reserved. */
200 } dmar_remap;
201
202 /** The 32-bit unsigned integer view. */
203 uint32_t au32[2];
204
205 /** The 64-bit unsigned integer view. */
206 uint64_t u64;
207} MSIADDR;
208AssertCompileSize(MSIADDR, 8);
209/** Pointer to an MSI address register. */
210typedef MSIADDR *PMSIADDR;
211/** Pointer to a const MSI address register. */
212typedef MSIADDR const *PCMSIADDR;
213
214/** Mask of valid bits in the MSI address register. According to the AMD IOMMU spec.
215 * and presumably the PCI spec., the top 32-bits are not reserved. From a PCI/IOMMU
216 * standpoint this makes sense. However, when dealing with the CPU side of things
217 * we might want to ensure the upper bits are reserved. Does x86/x64 really
218 * support a 64-bit MSI address? */
219#define VBOX_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
220#define VBOX_MSI_ADDR_ADDR_MASK UINT64_C(0x00000000fff00000)
221
222/**
223 * MSI Data Register.
224 */
225typedef union MSIDATA
226{
227 /*
228 * Intel and AMD xAPIC format.
229 * See Intel spec. 10.11.2 "Message Data Register Format".
230 * This also conforms to the AMD IOMMU spec. which omits specifying
231 * individual fields but specifies reserved bits.
232 */
233 struct
234 {
235 uint32_t u8Vector : 8; /**< Bits 7:0 - Vector. */
236 uint32_t u3DeliveryMode : 3; /**< Bits 10:8 - Delivery Mode. */
237 uint32_t u3Rsvd0 : 3; /**< Bits 13:11 - Reserved. */
238 uint32_t u1Level : 1; /**< Bit 14 - Level. */
239 uint32_t u1TriggerMode : 1; /**< Bit 15 - Trigger Mode (0=edge, 1=level). */
240 uint32_t u16Rsvd0 : 16; /**< Bits 31:16 - Reserved. */
241 } n;
242
243 /*
244 * Intel x2APIC Format.
245 * See Intel VT-d spec. 5.1.6.2 "Programming in Intel 64 x2APIC Mode".
246 */
247 struct
248 {
249 uint32_t u8Vector : 8; /**< Bits 7:0 - Vector. */
250 uint32_t u1DeliveryMode : 1; /**< Bit 8 - Delivery Mode (0=fixed, 1=lowest priority). */
251 uint32_t u23Rsvd0 : 23; /**< Bits 31:9 - Reserved. */
252 } x2apic;
253
254 /*
255 * Intel IOMMU Remappable Interrupt Format.
256 * See Intel VT-d spec. 5.1.2.2 "Interrupt Requests in Remappable Format".
257 */
258 struct
259 {
260 uint16_t u16SubHandle;
261 uint16_t u16Rsvd0;
262 } dmar_remap;
263
264 /** The 32-bit unsigned integer view. */
265 uint32_t u32;
266} MSIDATA;
267AssertCompileSize(MSIDATA, 4);
268/** Pointer to an MSI data register. */
269typedef MSIDATA *PMSIDATA;
270/** Pointer to a const MSI data register. */
271typedef MSIDATA const *PCMSIDATA;
272
273/** Mask of valid bits in the MSI data register. */
274#define VBOX_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
275
276/**
277 * MSI Message (Address and Data Register Pair).
278 */
279typedef struct MSIMSG
280{
281 /** The MSI Address Register. */
282 MSIADDR Addr;
283 /** The MSI Data Register. */
284 MSIDATA Data;
285} MSIMSG;
286
287#endif /* !VBOX_INCLUDED_msi_h */
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