VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 3191

Last change on this file since 3191 was 2981, checked in by vboxsync, 18 years ago

InnoTek -> innotek: all the headers and comments.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 8.9 KB
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1/** @file
2 * PCI - The PCI Controller And Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * If you received this file as part of a commercial VirtualBox
17 * distribution, then only the terms of your commercial VirtualBox
18 * license agreement apply instead of the previous paragraph.
19 */
20
21
22#ifndef __VBox_pci_h__
23#define __VBox_pci_h__
24
25
26#include <VBox/cdefs.h>
27#include <VBox/types.h>
28
29/** @defgroup grp_pci PCI - The PCI Controller.
30 * @{
31 */
32
33/** Pointer to a PCI device. */
34typedef struct PCIDevice *PPCIDEVICE;
35
36
37/**
38 * PCI configuration word 4 (command) and word 6 (status).
39 */
40typedef enum PCICONFIGCOMMAND
41{
42 /** Supports/uses memory accesses. */
43 PCI_COMMAND_IOACCESS = 0x0001,
44 PCI_COMMAND_MEMACCESS = 0x0002,
45 PCI_COMMAND_BUSMASTER = 0x0004
46} PCICONFIGCOMMAND;
47
48
49/**
50 * PCI Address space specification.
51 * This is used when registering a I/O region.
52 */
53typedef enum PCIADDRESSSPACE
54{
55 /** Memory. */
56 PCI_ADDRESS_SPACE_MEM = 0x00,
57 /** I/O space. */
58 PCI_ADDRESS_SPACE_IO = 0x01,
59 /** Prefetch memory. */
60 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
61} PCIADDRESSSPACE;
62
63
64/**
65 * Callback function for mapping an PCI I/O region.
66 *
67 * @return VBox status code.
68 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
69 * @param iRegion The region number.
70 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
71 * I/O port, else it's a physical address.
72 * This address is *NOT* relative to pci_mem_base like earlier!
73 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
74 */
75typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
76/** Pointer to a FNPCIIOREGIONMAP() function. */
77typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
78
79
80/** @name PCI Configuration Space Registers
81 * @{ */
82#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
83#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
84#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW */
85#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW */
86#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO */
87#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO */
88#define VBOX_PCI_CLASS_DEVICE 0x0a /**< 8-bit ?? */
89#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit ?? */
90#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit ?? */
91#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit ?? */
92#define VBOX_PCI_BIST 0x0f /**< 8-bit ?? */
93#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
94#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
95#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
96#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - bridge - primary bus number. */
97#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - bridge - secondary bus number. */
98#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - bridge - highest subordinate bus number. (behind the bridge) */
99#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - bridge - secondary latency timer. */
100#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
101#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - bridge - I/O range base. */
102#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - bridge - I/O range limit. */
103#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - bridge - secondary status register. */
104#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
105#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - bridge - memory range base. */
106#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - bridge - memory range limit. */
107#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
108#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - bridge - Prefetchable memory range base. */
109#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - bridge - Prefetchable memory range limit. */
110#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
111#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - bridge - Prefetchable memory range high base.*/
112#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - bridge - Prefetchable memory range high limit. */
113#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit ?? */
114#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit ?? */
115#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
116#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - bridge - memory range high base. */
117#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - bridge - memory range high limit. */
118#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit? ?? */
119#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - bridge */
120#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - Interrupt line. */
121#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - Interrupt pin. */
122#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit ?? */
123#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 8-bit? ?? - bridge */
124#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit ?? */
125/** @} */
126
127
128/**
129 * Callback function for reading from the PCI configuration space.
130 *
131 * @returns The register value.
132 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
133 * @param Address The configuration space register address. [0..255]
134 * @param cb The register size. [1,2,4]
135 */
136typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
137/** Pointer to a FNPCICONFIGREAD() function. */
138typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
139/** Pointer to a PFNPCICONFIGREAD. */
140typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
141
142/**
143 * Callback function for writing to the PCI configuration space.
144 *
145 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
146 * @param Address The configuration space register address. [0..255]
147 * @param u32Value The value that's being written. The number of bits actually used from
148 * this value is determined by the cb parameter.
149 * @param cb The register size. [1,2,4]
150 */
151typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
152/** Pointer to a FNPCICONFIGWRITE() function. */
153typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
154/** Pointer to a PFNPCICONFIGWRITE. */
155typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
156
157/** Fixed I/O region number for ROM. */
158#define PCI_ROM_SLOT 6
159/** Max number of I/O regions. */
160#define PCI_NUM_REGIONS 7
161
162/*
163 * Hack to include the PCIDEVICEINT structure at the right place
164 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
165 */
166#ifdef PCI_INCLUDE_PRIVATE
167# include "PCIInternal.h"
168#endif
169
170/**
171 * PCI Device structure.
172 */
173typedef struct PCIDevice
174{
175 /** PCI config space. */
176 uint8_t config[256];
177
178 /** Internal data. */
179 union
180 {
181#ifdef __PCIDEVICEINT_DECLARED__
182 PCIDEVICEINT s;
183#endif
184 char padding[224];
185 } Int;
186
187 /** Read only data.
188 * @{
189 */
190 /** PCI device number on the pci bus. */
191 int32_t devfn;
192 uint32_t Alignment0; /**< Alignment. */
193 /** Device name. */
194 R3PTRTYPE(const char *) name;
195 /** Pointer to the device instance which registered the device. */
196 PPDMDEVINSR3 pDevIns;
197 /** @} */
198} PCIDEVICE;
199
200
201/**
202 * Sets the vendor id config register.
203 * @param pPciDev The PCI device.
204 * @param u16VendorId The vendor id.
205 */
206DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
207{
208 u16VendorId = RT_H2LE_U16(u16VendorId);
209 pPciDev->config[VBOX_PCI_VENDOR_ID] = u16VendorId & 0xff;
210 pPciDev->config[VBOX_PCI_VENDOR_ID + 1] = u16VendorId >> 8;
211}
212
213/**
214 * Sets the vendor id config register.
215 * @param pPciDev The PCI device.
216 * @param u16VendorId The vendor id.
217 */
218DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
219{
220 u16DeviceId = RT_H2LE_U16(u16DeviceId);
221 pPciDev->config[VBOX_PCI_DEVICE_ID] = u16DeviceId & 0xff;
222 pPciDev->config[VBOX_PCI_DEVICE_ID + 1] = u16DeviceId >> 8;
223}
224
225
226/** @} */
227
228#endif
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