1 | /** @file
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2 | * PCI - The PCI Controller And Devices.
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2007 innotek GmbH
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License as published by the Free Software Foundation,
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12 | * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
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13 | * distribution. VirtualBox OSE is distributed in the hope that it will
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14 | * be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * If you received this file as part of a commercial VirtualBox
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17 | * distribution, then only the terms of your commercial VirtualBox
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18 | * license agreement apply instead of the previous paragraph.
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19 | */
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20 |
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21 |
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22 | #ifndef __VBox_pci_h__
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23 | #define __VBox_pci_h__
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24 |
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25 |
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26 | #include <VBox/cdefs.h>
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27 | #include <VBox/types.h>
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28 |
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29 | /** @defgroup grp_pci PCI - The PCI Controller.
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30 | * @{
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31 | */
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32 |
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33 | /** Pointer to a PCI device. */
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34 | typedef struct PCIDevice *PPCIDEVICE;
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35 |
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36 |
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37 | /**
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38 | * PCI configuration word 4 (command) and word 6 (status).
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39 | */
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40 | typedef enum PCICONFIGCOMMAND
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41 | {
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42 | /** Supports/uses memory accesses. */
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43 | PCI_COMMAND_IOACCESS = 0x0001,
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44 | PCI_COMMAND_MEMACCESS = 0x0002,
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45 | PCI_COMMAND_BUSMASTER = 0x0004
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46 | } PCICONFIGCOMMAND;
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47 |
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48 |
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49 | /**
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50 | * PCI Address space specification.
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51 | * This is used when registering a I/O region.
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52 | */
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53 | typedef enum PCIADDRESSSPACE
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54 | {
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55 | /** Memory. */
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56 | PCI_ADDRESS_SPACE_MEM = 0x00,
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57 | /** I/O space. */
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58 | PCI_ADDRESS_SPACE_IO = 0x01,
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59 | /** Prefetch memory. */
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60 | PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
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61 | } PCIADDRESSSPACE;
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62 |
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63 |
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64 | /**
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65 | * Callback function for mapping an PCI I/O region.
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66 | *
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67 | * @return VBox status code.
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68 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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69 | * @param iRegion The region number.
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70 | * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
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71 | * I/O port, else it's a physical address.
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72 | * This address is *NOT* relative to pci_mem_base like earlier!
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73 | * @param enmType One of the PCI_ADDRESS_SPACE_* values.
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74 | */
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75 | typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
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76 | /** Pointer to a FNPCIIOREGIONMAP() function. */
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77 | typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
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78 |
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79 |
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80 | /** @name PCI Configuration Space Registers
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81 | * @{ */
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82 | #define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
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83 | #define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
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84 | #define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW */
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85 | #define VBOX_PCI_STATUS 0x06 /**< 16-bit RW */
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86 | #define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO */
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87 | #define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO */
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88 | #define VBOX_PCI_CLASS_DEVICE 0x0a /**< 8-bit ?? */
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89 | #define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit ?? */
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90 | #define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit ?? */
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91 | #define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit ?? */
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92 | #define VBOX_PCI_BIST 0x0f /**< 8-bit ?? */
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93 | #define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
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94 | #define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
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95 | #define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
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96 | #define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - bridge - primary bus number. */
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97 | #define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - bridge - secondary bus number. */
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98 | #define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - bridge - highest subordinate bus number. (behind the bridge) */
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99 | #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - bridge - secondary latency timer. */
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100 | #define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
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101 | #define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - bridge - I/O range base. */
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102 | #define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - bridge - I/O range limit. */
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103 | #define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - bridge - secondary status register. */
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104 | #define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
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105 | #define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - bridge - memory range base. */
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106 | #define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - bridge - memory range limit. */
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107 | #define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
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108 | #define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - bridge - Prefetchable memory range base. */
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109 | #define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - bridge - Prefetchable memory range limit. */
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110 | #define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
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111 | #define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - bridge - Prefetchable memory range high base.*/
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112 | #define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - bridge - Prefetchable memory range high limit. */
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113 | #define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit ?? */
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114 | #define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit ?? */
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115 | #define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
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116 | #define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - bridge - memory range high base. */
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117 | #define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - bridge - memory range high limit. */
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118 | #define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit? ?? */
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119 | #define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - bridge */
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120 | #define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - Interrupt line. */
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121 | #define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - Interrupt pin. */
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122 | #define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit ?? */
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123 | #define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 8-bit? ?? - bridge */
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124 | #define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit ?? */
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125 | /** @} */
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126 |
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127 |
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128 | /**
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129 | * Callback function for reading from the PCI configuration space.
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130 | *
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131 | * @returns The register value.
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132 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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133 | * @param Address The configuration space register address. [0..255]
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134 | * @param cb The register size. [1,2,4]
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135 | */
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136 | typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
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137 | /** Pointer to a FNPCICONFIGREAD() function. */
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138 | typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
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139 | /** Pointer to a PFNPCICONFIGREAD. */
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140 | typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
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141 |
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142 | /**
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143 | * Callback function for writing to the PCI configuration space.
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144 | *
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145 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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146 | * @param Address The configuration space register address. [0..255]
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147 | * @param u32Value The value that's being written. The number of bits actually used from
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148 | * this value is determined by the cb parameter.
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149 | * @param cb The register size. [1,2,4]
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150 | */
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151 | typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
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152 | /** Pointer to a FNPCICONFIGWRITE() function. */
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153 | typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
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154 | /** Pointer to a PFNPCICONFIGWRITE. */
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155 | typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
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156 |
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157 | /** Fixed I/O region number for ROM. */
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158 | #define PCI_ROM_SLOT 6
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159 | /** Max number of I/O regions. */
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160 | #define PCI_NUM_REGIONS 7
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161 |
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162 | /*
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163 | * Hack to include the PCIDEVICEINT structure at the right place
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164 | * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
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165 | */
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166 | #ifdef PCI_INCLUDE_PRIVATE
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167 | # include "PCIInternal.h"
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168 | #endif
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169 |
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170 | /**
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171 | * PCI Device structure.
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172 | */
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173 | typedef struct PCIDevice
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174 | {
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175 | /** PCI config space. */
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176 | uint8_t config[256];
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177 |
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178 | /** Internal data. */
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179 | union
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180 | {
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181 | #ifdef __PCIDEVICEINT_DECLARED__
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182 | PCIDEVICEINT s;
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183 | #endif
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184 | char padding[224];
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185 | } Int;
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186 |
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187 | /** Read only data.
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188 | * @{
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189 | */
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190 | /** PCI device number on the pci bus. */
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191 | int32_t devfn;
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192 | uint32_t Alignment0; /**< Alignment. */
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193 | /** Device name. */
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194 | R3PTRTYPE(const char *) name;
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195 | /** Pointer to the device instance which registered the device. */
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196 | PPDMDEVINSR3 pDevIns;
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197 | /** @} */
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198 | } PCIDEVICE;
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199 |
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200 |
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201 | /**
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202 | * Sets the vendor id config register.
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203 | * @param pPciDev The PCI device.
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204 | * @param u16VendorId The vendor id.
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205 | */
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206 | DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
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207 | {
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208 | u16VendorId = RT_H2LE_U16(u16VendorId);
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209 | pPciDev->config[VBOX_PCI_VENDOR_ID] = u16VendorId & 0xff;
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210 | pPciDev->config[VBOX_PCI_VENDOR_ID + 1] = u16VendorId >> 8;
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211 | }
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212 |
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213 | /**
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214 | * Sets the vendor id config register.
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215 | * @param pPciDev The PCI device.
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216 | * @param u16VendorId The vendor id.
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217 | */
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218 | DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
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219 | {
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220 | u16DeviceId = RT_H2LE_U16(u16DeviceId);
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221 | pPciDev->config[VBOX_PCI_DEVICE_ID] = u16DeviceId & 0xff;
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222 | pPciDev->config[VBOX_PCI_DEVICE_ID + 1] = u16DeviceId >> 8;
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223 | }
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224 |
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225 |
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226 | /** @} */
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227 |
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228 | #endif
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