VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 34801

Last change on this file since 34801 was 34301, checked in by vboxsync, 14 years ago

PCI: interrupt mapping
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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @{
35 */
36
37/** Pointer to a PCI device. */
38typedef struct PCIDevice *PPCIDEVICE;
39
40
41/**
42 * PCI configuration word 4 (command) and word 6 (status).
43 */
44typedef enum PCICONFIGCOMMAND
45{
46 /** Supports/uses memory accesses. */
47 PCI_COMMAND_IOACCESS = 0x0001,
48 PCI_COMMAND_MEMACCESS = 0x0002,
49 PCI_COMMAND_BUSMASTER = 0x0004
50} PCICONFIGCOMMAND;
51
52
53/**
54 * PCI Address space specification.
55 * This is used when registering a I/O region.
56 */
57/** Note: There are all sorts of dirty dependencies on the values in the
58 * pci device. Be careful when changing this.
59 */
60typedef enum PCIADDRESSSPACE
61{
62 /** Memory. */
63 PCI_ADDRESS_SPACE_MEM = 0x00,
64 /** I/O space. */
65 PCI_ADDRESS_SPACE_IO = 0x01,
66 /** 32-bit BAR. */
67 PCI_ADDRESS_SPACE_BAR32 = 0x00,
68 /** 64-bit BAR. */
69 PCI_ADDRESS_SPACE_BAR64 = 0x04,
70 /** Prefetch memory. */
71 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
72} PCIADDRESSSPACE;
73
74
75/**
76 * Callback function for mapping an PCI I/O region.
77 *
78 * @return VBox status code.
79 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
80 * @param iRegion The region number.
81 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
82 * is an I/O port, otherwise it's a physical address.
83 *
84 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
85 * that the device deregister access handlers for it and update its internal
86 * state to reflect this.
87 *
88 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
89 *
90 * @remarks The address is *NOT* relative to pci_mem_base.
91 */
92typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
93/** Pointer to a FNPCIIOREGIONMAP() function. */
94typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
95
96
97/** @name PCI Configuration Space Registers
98 * @{ */
99/* Commented out values common for different header types */
100/* Common part of the header */
101#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
102#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
103#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
104#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
105#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
106#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
107#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
108#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
109#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
110#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
111#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
112#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
113#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
114#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
115#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
116#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
117
118/* Type 0 header, device */
119#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
120#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
121#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
122#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
123#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
124#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
125#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
126#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
127#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
128#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
129/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
130#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
131#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
132#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
133#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
134/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
135/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
136#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
137#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
138
139/* Type 1 header, PCI-to-PCI bridge */
140/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
141/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
142#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
143#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
144#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
145#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
146#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
147#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
148#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
149#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
150#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
151#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
152#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
153#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
154#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
155#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
156#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
157/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
158/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
159/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
160/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
161#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
162#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
163
164/* Type 2 header, PCI-to-CardBus bridge */
165#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
166#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
167#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
168#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
169#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
170#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
171/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
172/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
173#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
174#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
175#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
176#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
177#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
178#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
179#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
180#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
181/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
182/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
183/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
184/** @} */
185
186
187/* Possible values in status bitmask */
188#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
189#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
190#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
191#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
192#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
193#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
194#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
195#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
196#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
197#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
198#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
199#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
200#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
201#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
202
203
204/* Command bitmask */
205#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
206#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
207#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
208#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
209#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
210#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
211#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
212#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
213#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
214#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
215#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
216
217
218/* Capability list values (capability offset 0) */
219/* Next value pointer in offset 1, or 0 if none */
220#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
221#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
222#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
223#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
224#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
225#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
226#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
227#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
228#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
229#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
230#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
231#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
232#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
233#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
234#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
235#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
236#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
237#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
238#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
239
240/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
241#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
242#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
243#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
244#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
245#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
246#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
247#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
248#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
249#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
250#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
251#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
252#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
253#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
254#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
255
256
257/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
258#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
259#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
260#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
261/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
262 someone very similar to log_2().
263 000 1
264 001 2
265 010 4
266 011 8
267 100 16
268 101 32
269 110 Reserved
270 111 Reserved */
271#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
272#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
273
274/* MSI-X flags (2 bytes, capability offset 2) */
275#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
276#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
277
278/* Power management flags (2 bytes, capability offset 2) */
279#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
280#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
281#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
282#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
283#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
284#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
285#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
286#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
287#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
288#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
289#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
290#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
291#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
292#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
293
294/* Power management control flags (2 bytes, capability offset 4) */
295#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
296#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
297#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
298#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
299#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
300#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
301
302/* PCI-X config flags (2 bytes, capability offset 2) */
303#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
304#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
305#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
306#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
307#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
308#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
309#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
310#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
311
312/* PCI-X config flags (4 bytes, capability offset 4) */
313#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
314#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
315#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
316#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
317#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
318#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
319#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
320#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
321#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
322#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
323#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
324#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
325#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
326
327/* PCI Express config flags (2 bytes, capability offset 2) */
328#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
329#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
330#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
331#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
332#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
333#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
334#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
335#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
336#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
337#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
338#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
339#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
340#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
341
342/* PCI Express device capabilities (4 bytes, capability offset 4) */
343#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
344#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
345#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
346#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
347#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
348#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
349#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
350#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
351#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
352#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
353#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
354#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
355
356/* PCI Express device control (2 bytes, capability offset 8) */
357#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
358#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
359#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
360#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
361#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
362#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
363#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
364#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
365#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
366#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
367#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
368#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
369#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
370
371/* PCI Express device status (2 bytes, capability offset 10) */
372#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
373#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
374#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
375#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
376#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
377#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
378
379/* PCI Express link capabilities (4 bytes, capability offset 12) */
380#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
381#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
382#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
383#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
384#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
385#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
386#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
387#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
388#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
389#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
390
391/* PCI Express link control (2 bytes, capability offset 16) */
392#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
393#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
394#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
395#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
396#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
397#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
398#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
399#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
400#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
401#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
402
403/* PCI Express link status (2 bytes, capability offset 18) */
404#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
405#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
406#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
407#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
408#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
409#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
410#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
411#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
412
413/* PCI Express slot capabilities (4 bytes, capability offset 20) */
414#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
415#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
416#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
417#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
418#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
419#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
420#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
421#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
422#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
423#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
424#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
425#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
426
427/* PCI Express slot control (2 bytes, capability offset 24) */
428#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
429#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
430#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
431#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
432#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
433#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
434#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
435#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
436#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
437#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
438#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
439
440/* PCI Express slot status (2 bytes, capability offset 26) */
441#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
442#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
443#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
444#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
445#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
446#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
447#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
448#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
449#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
450
451/* PCI Express root control (2 bytes, capability offset 28) */
452#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
453#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
454#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
455#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
456#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
457
458/* PCI Express root capabilities (2 bytes, capability offset 30) */
459#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
460
461/* PCI Express root status (4 bytes, capability offset 32) */
462#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
463#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
464#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
465
466
467/**
468 * Callback function for reading from the PCI configuration space.
469 *
470 * @returns The register value.
471 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
472 * @param Address The configuration space register address. [0..4096]
473 * @param cb The register size. [1,2,4]
474 */
475typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
476/** Pointer to a FNPCICONFIGREAD() function. */
477typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
478/** Pointer to a PFNPCICONFIGREAD. */
479typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
480
481/**
482 * Callback function for writing to the PCI configuration space.
483 *
484 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
485 * @param Address The configuration space register address. [0..4096]
486 * @param u32Value The value that's being written. The number of bits actually used from
487 * this value is determined by the cb parameter.
488 * @param cb The register size. [1,2,4]
489 */
490typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
491/** Pointer to a FNPCICONFIGWRITE() function. */
492typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
493/** Pointer to a PFNPCICONFIGWRITE. */
494typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
495
496/** Fixed I/O region number for ROM. */
497#define PCI_ROM_SLOT 6
498#define VBOX_PCI_ROM_SLOT 6
499/** Max number of I/O regions. */
500#define PCI_NUM_REGIONS 7
501#define VBOX_PCI_NUM_REGIONS 7
502
503/*
504 * Hack to include the PCIDEVICEINT structure at the right place
505 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
506 */
507#ifdef PCI_INCLUDE_PRIVATE
508# include "PCIInternal.h"
509#endif
510
511/**
512 * PCI Device structure.
513 */
514typedef struct PCIDevice
515{
516 /** PCI config space. */
517 uint8_t config[256];
518
519 /** Internal data. */
520 union
521 {
522#ifdef PCIDEVICEINT_DECLARED
523 PCIDEVICEINT s;
524#endif
525 char padding[288];
526 } Int;
527
528 /** Read only data.
529 * @{
530 */
531 /** PCI device number on the pci bus. */
532 int32_t devfn;
533 uint32_t Alignment0; /**< Alignment. */
534 /** Device name. */
535 R3PTRTYPE(const char *) name;
536 /** Pointer to the device instance which registered the device. */
537 PPDMDEVINSR3 pDevIns;
538 /** @} */
539} PCIDEVICE;
540
541/* @todo: handle extended space access */
542DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t uOffset, uint8_t u8Value)
543{
544 pPciDev->config[uOffset] = u8Value;
545}
546
547DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset)
548{
549 return pPciDev->config[uOffset];
550}
551
552DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint16_t u16Value)
553{
554 *(uint16_t*)&pPciDev->config[uOffset] = RT_H2LE_U16(u16Value);
555}
556
557DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset)
558{
559 uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset];
560 return RT_H2LE_U16(u16Value);
561}
562
563DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint32_t u32Value)
564{
565 *(uint32_t*)&pPciDev->config[uOffset] = RT_H2LE_U32(u32Value);
566}
567
568DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset)
569{
570 uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset];
571 return RT_H2LE_U32(u32Value);
572}
573
574DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint64_t u64Value)
575{
576 *(uint64_t*)&pPciDev->config[uOffset] = RT_H2LE_U64(u64Value);
577}
578
579DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset)
580{
581 uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset];
582 return RT_H2LE_U64(u64Value);
583}
584
585/**
586 * Sets the vendor id config register.
587 * @param pPciDev The PCI device.
588 * @param u16VendorId The vendor id.
589 */
590DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
591{
592 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
593}
594
595/**
596 * Gets the vendor id config register.
597 * @returns the vendor id.
598 * @param pPciDev The PCI device.
599 */
600DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
601{
602 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
603}
604
605
606/**
607 * Sets the device id config register.
608 * @param pPciDev The PCI device.
609 * @param u16DeviceId The device id.
610 */
611DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
612{
613 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
614}
615
616/**
617 * Gets the device id config register.
618 * @returns the device id.
619 * @param pPciDev The PCI device.
620 */
621DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
622{
623 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
624}
625
626/**
627 * Sets the command config register.
628 *
629 * @param pPciDev The PCI device.
630 * @param u16Command The command register value.
631 */
632DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
633{
634 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
635}
636
637
638/**
639 * Gets the command config register.
640 * @returns The command register value.
641 * @param pPciDev The PCI device.
642 */
643DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
644{
645 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
646}
647
648/**
649 * Checks if INTx interrupts disabled in the command config register.
650 * @returns true if disabled.
651 * @param pPciDev The PCI device.
652 */
653DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
654{
655 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
656}
657
658/**
659 * Gets the status config register.
660 *
661 * @returns status config register.
662 * @param pPciDev The PCI device.
663 */
664DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
665{
666 return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
667}
668
669/**
670 * Sets the status config register.
671 *
672 * @param pPciDev The PCI device.
673 * @param u16Status The status register value.
674 */
675DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
676{
677 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
678}
679
680
681/**
682 * Sets the revision id config register.
683 *
684 * @param pPciDev The PCI device.
685 * @param u8RevisionId The revision id.
686 */
687DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
688{
689 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
690}
691
692
693/**
694 * Sets the register level programming class config register.
695 *
696 * @param pPciDev The PCI device.
697 * @param u8ClassProg The new value.
698 */
699DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
700{
701 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
702}
703
704
705/**
706 * Sets the sub-class (aka device class) config register.
707 *
708 * @param pPciDev The PCI device.
709 * @param u8SubClass The sub-class.
710 */
711DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
712{
713 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
714}
715
716
717/**
718 * Sets the base class config register.
719 *
720 * @param pPciDev The PCI device.
721 * @param u8BaseClass The base class.
722 */
723DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
724{
725 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
726}
727
728/**
729 * Sets the header type config register.
730 *
731 * @param pPciDev The PCI device.
732 * @param u8HdrType The header type.
733 */
734DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
735{
736 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
737}
738
739/**
740 * Gets the header type config register.
741 *
742 * @param pPciDev The PCI device.
743 * @returns u8HdrType The header type.
744 */
745DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
746{
747 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
748}
749
750/**
751 * Sets the BIST (built-in self-test) config register.
752 *
753 * @param pPciDev The PCI device.
754 * @param u8Bist The BIST value.
755 */
756DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
757{
758 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
759}
760
761/**
762 * Gets the BIST (built-in self-test) config register.
763 *
764 * @param pPciDev The PCI device.
765 * @returns u8Bist The BIST.
766 */
767DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
768{
769 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
770}
771
772
773/**
774 * Sets a base address config register.
775 *
776 * @param pPciDev The PCI device.
777 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
778 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
779 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
780 * @param u32Addr The address value.
781 */
782DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
783{
784 if (fIOSpace)
785 {
786 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
787 u32Addr |= RT_BIT_32(0);
788 }
789 else
790 {
791 Assert(!(u32Addr & 0xf));
792 if (fPrefetchable)
793 u32Addr |= RT_BIT_32(3);
794 if (f64Bit)
795 u32Addr |= 0x2 << 1;
796 }
797 switch (iReg)
798 {
799 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
800 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
801 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
802 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
803 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
804 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
805 default: AssertFailedReturnVoid();
806 }
807
808 PCIDevSetDWord(pPciDev, iReg, u32Addr);
809}
810
811
812/**
813 * Sets the sub-system vendor id config register.
814 *
815 * @param pPciDev The PCI device.
816 * @param u16SubSysVendorId The sub-system vendor id.
817 */
818DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
819{
820 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
821}
822
823/**
824 * Gets the sub-system vendor id config register.
825 * @returns the sub-system vendor id.
826 * @param pPciDev The PCI device.
827 */
828DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
829{
830 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
831}
832
833
834/**
835 * Sets the sub-system id config register.
836 *
837 * @param pPciDev The PCI device.
838 * @param u16SubSystemId The sub-system id.
839 */
840DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
841{
842 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
843}
844
845/**
846 * Gets the sub-system id config register.
847 * @returns the sub-system id.
848 * @param pPciDev The PCI device.
849 */
850DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
851{
852 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
853}
854
855/**
856 * Sets offset to capability list.
857 *
858 * @param pPciDev The PCI device.
859 * @param u8Offset The offset to capability list.
860 */
861DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
862{
863 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
864}
865
866/**
867 * Returns offset to capability list.
868 *
869 * @returns offset to capability list.
870 * @param pPciDev The PCI device.
871 */
872DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
873{
874 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
875}
876
877/**
878 * Sets the interrupt line config register.
879 *
880 * @param pPciDev The PCI device.
881 * @param u8Line The interrupt line.
882 */
883DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
884{
885 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
886}
887
888/**
889 * Gets the interrupt line config register.
890 *
891 * @returns The interrupt line.
892 * @param pPciDev The PCI device.
893 */
894DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
895{
896 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
897}
898
899/**
900 * Sets the interrupt pin config register.
901 *
902 * @param pPciDev The PCI device.
903 * @param u8Pin The interrupt pin.
904 */
905DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
906{
907 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
908}
909
910/**
911 * Gets the interrupt pin config register.
912 *
913 * @returns The interrupt pin.
914 * @param pPciDev The PCI device.
915 */
916DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
917{
918 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
919}
920
921#ifdef PCIDEVICEINT_DECLARED
922DECLINLINE(void) PCISetRequestedDevfunc(PPCIDEVICE pDev)
923{
924 pDev->Int.s.uFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
925}
926
927DECLINLINE(void) PCIClearRequestedDevfunc(PPCIDEVICE pDev)
928{
929 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
930}
931
932DECLINLINE(bool) PCIIsRequestedDevfunc(PPCIDEVICE pDev)
933{
934 return (pDev->Int.s.uFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
935}
936
937DECLINLINE(void) PCISetPci2PciBridge(PPCIDEVICE pDev)
938{
939 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
940}
941
942DECLINLINE(bool) PCIIsPci2PciBridge(PPCIDEVICE pDev)
943{
944 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
945}
946
947DECLINLINE(void) PCISetPciExpress(PPCIDEVICE pDev)
948{
949 pDev->Int.s.uFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
950}
951
952DECLINLINE(bool) PCIIsPciExpress(PPCIDEVICE pDev)
953{
954 return (pDev->Int.s.uFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
955}
956
957DECLINLINE(void) PCISetMsiCapable(PPCIDEVICE pDev)
958{
959 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSI_CAPABLE;
960}
961
962DECLINLINE(void) PCIClearMsiCapable(PPCIDEVICE pDev)
963{
964 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
965}
966
967DECLINLINE(bool) PCIIsMsiCapable(PPCIDEVICE pDev)
968{
969 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
970}
971
972DECLINLINE(void) PCISetMsixCapable(PPCIDEVICE pDev)
973{
974 pDev->Int.s.uFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
975}
976
977DECLINLINE(void) PCIClearMsixCapable(PPCIDEVICE pDev)
978{
979 pDev->Int.s.uFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
980}
981
982DECLINLINE(bool) PCIIsMsixCapable(PPCIDEVICE pDev)
983{
984 return (pDev->Int.s.uFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
985}
986#endif
987
988/** @} */
989
990#endif
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