VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 41745

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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @{
35 */
36
37/** Pointer to a PCI device. */
38typedef struct PCIDevice *PPCIDEVICE;
39
40
41/**
42 * PCI configuration word 4 (command) and word 6 (status).
43 */
44typedef enum PCICONFIGCOMMAND
45{
46 /** Supports/uses memory accesses. */
47 PCI_COMMAND_IOACCESS = 0x0001,
48 PCI_COMMAND_MEMACCESS = 0x0002,
49 PCI_COMMAND_BUSMASTER = 0x0004
50} PCICONFIGCOMMAND;
51
52
53/**
54 * PCI Address space specification.
55 * This is used when registering a I/O region.
56 */
57/**
58 * Defined by the PCI specification.
59 */
60typedef enum PCIADDRESSSPACE
61{
62 /** Memory. */
63 PCI_ADDRESS_SPACE_MEM = 0x00,
64 /** I/O space. */
65 PCI_ADDRESS_SPACE_IO = 0x01,
66 /** 32-bit BAR. */
67 PCI_ADDRESS_SPACE_BAR32 = 0x00,
68 /** 64-bit BAR. */
69 PCI_ADDRESS_SPACE_BAR64 = 0x04,
70 /** Prefetch memory. */
71 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
72} PCIADDRESSSPACE;
73
74
75/**
76 * Callback function for mapping an PCI I/O region.
77 *
78 * @return VBox status code.
79 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
80 * @param iRegion The region number.
81 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
82 * is an I/O port, otherwise it's a physical address.
83 *
84 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
85 * that the device deregister access handlers for it and update its internal
86 * state to reflect this.
87 *
88 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
89 *
90 */
91typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
92/** Pointer to a FNPCIIOREGIONMAP() function. */
93typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
94
95
96/** @name PCI Configuration Space Registers
97 * @{ */
98/* Commented out values common for different header types */
99/* Common part of the header */
100#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
101#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
102#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
103#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
104#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
105#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
106#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
107#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
108#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
109#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
110#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
111#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
112#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
113#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
114#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
115#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
116
117/* Type 0 header, device */
118#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
119#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
120#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
121#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
122#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
123#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
124#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
125#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
126#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
127#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
128/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
129#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
130#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
131#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
132#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
133/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
134/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
135#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
136#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
137
138/* Type 1 header, PCI-to-PCI bridge */
139/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
140/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
141#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
142#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
143#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
144#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
145#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
146#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
147#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
148#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
149#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
150#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
151#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
152#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
153#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
154#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
155#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
156/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
157/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
158/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
159/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
160#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
161#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
162
163/* Type 2 header, PCI-to-CardBus bridge */
164#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
165#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
166#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
167#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
168#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
169#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
170/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
171/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
172#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
173#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
174#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
175#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
176#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
177#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
178#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
179#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
180/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
181/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
182/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
183/** @} */
184
185
186/* Possible values in status bitmask */
187#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
188#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
189#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
190#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
191#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
192#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
193#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
194#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
195#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
196#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
197#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
198#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
199#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
200#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
201
202
203/* Command bitmask */
204#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
205#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
206#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
207#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
208#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
209#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
210#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
211#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
212#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
213#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
214#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
215
216
217/* Capability list values (capability offset 0) */
218/* Next value pointer in offset 1, or 0 if none */
219#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
220#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
221#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
222#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
223#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
224#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
225#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
226#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
227#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
228#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
229#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
230#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
231#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
232#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
233#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
234#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
235#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
236#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
237#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
238
239/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
240#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
241#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
242#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
243#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
244#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
245#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
246#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
247#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
248#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
249#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
250#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
251#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
252#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
253#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
254
255
256/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
257#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
258#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
259#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
260/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
261 someone very similar to log_2().
262 000 1
263 001 2
264 010 4
265 011 8
266 100 16
267 101 32
268 110 Reserved
269 111 Reserved */
270#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
271#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
272
273/* MSI-X flags (2 bytes, capability offset 2) */
274#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
275#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
276
277/* Power management flags (2 bytes, capability offset 2) */
278#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
279#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
280#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
281#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
282#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
283#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
284#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
285#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
286#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
287#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
288#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
289#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
290#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
291#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
292
293/* Power management control flags (2 bytes, capability offset 4) */
294#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
295#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
296#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
297#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
298#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
299#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
300
301/* PCI-X config flags (2 bytes, capability offset 2) */
302#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
303#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
304#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
305#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
306#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
307#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
308#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
309#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
310
311/* PCI-X config flags (4 bytes, capability offset 4) */
312#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
313#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
314#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
315#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
316#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
317#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
318#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
319#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
320#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
321#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
322#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
323#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
324#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
325
326/* PCI Express config flags (2 bytes, capability offset 2) */
327#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
328#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
329#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
330#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
331#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
332#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
333#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
334#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
335#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
336#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
337#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
338#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
339#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
340
341/* PCI Express device capabilities (4 bytes, capability offset 4) */
342#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
343#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
344#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
345#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
346#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
347#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
348#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
349#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
350#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
351#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
352#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
353#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
354
355/* PCI Express device control (2 bytes, capability offset 8) */
356#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
357#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
358#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
359#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
360#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
361#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
362#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
363#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
364#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
365#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
366#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
367#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
368#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
369
370/* PCI Express device status (2 bytes, capability offset 10) */
371#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
372#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
373#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
374#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
375#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
376#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
377
378/* PCI Express link capabilities (4 bytes, capability offset 12) */
379#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
380#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
381#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
382#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
383#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
384#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
385#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
386#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
387#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
388#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
389
390/* PCI Express link control (2 bytes, capability offset 16) */
391#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
392#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
393#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
394#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
395#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
396#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
397#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
398#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
399#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
400#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
401
402/* PCI Express link status (2 bytes, capability offset 18) */
403#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
404#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
405#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
406#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
407#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
408#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
409#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
410#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
411
412/* PCI Express slot capabilities (4 bytes, capability offset 20) */
413#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
414#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
415#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
416#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
417#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
418#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
419#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
420#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
421#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
422#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
423#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
424#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
425
426/* PCI Express slot control (2 bytes, capability offset 24) */
427#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
428#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
429#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
430#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
431#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
432#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
433#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
434#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
435#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
436#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
437#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
438
439/* PCI Express slot status (2 bytes, capability offset 26) */
440#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
441#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
442#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
443#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
444#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
445#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
446#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
447#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
448#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
449
450/* PCI Express root control (2 bytes, capability offset 28) */
451#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
452#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
453#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
454#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
455#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
456
457/* PCI Express root capabilities (2 bytes, capability offset 30) */
458#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
459
460/* PCI Express root status (4 bytes, capability offset 32) */
461#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
462#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
463#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
464
465
466/**
467 * Callback function for reading from the PCI configuration space.
468 *
469 * @returns The register value.
470 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
471 * @param Address The configuration space register address. [0..4096]
472 * @param cb The register size. [1,2,4]
473 */
474typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
475/** Pointer to a FNPCICONFIGREAD() function. */
476typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
477/** Pointer to a PFNPCICONFIGREAD. */
478typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
479
480/**
481 * Callback function for writing to the PCI configuration space.
482 *
483 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
484 * @param Address The configuration space register address. [0..4096]
485 * @param u32Value The value that's being written. The number of bits actually used from
486 * this value is determined by the cb parameter.
487 * @param cb The register size. [1,2,4]
488 */
489typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
490/** Pointer to a FNPCICONFIGWRITE() function. */
491typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
492/** Pointer to a PFNPCICONFIGWRITE. */
493typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
494
495/** Fixed I/O region number for ROM. */
496#define PCI_ROM_SLOT 6
497#define VBOX_PCI_ROM_SLOT 6
498/** Max number of I/O regions. */
499#define PCI_NUM_REGIONS 7
500#define VBOX_PCI_NUM_REGIONS 7
501
502/*
503 * Hack to include the PCIDEVICEINT structure at the right place
504 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
505 */
506#ifdef PCI_INCLUDE_PRIVATE
507# include "PCIInternal.h"
508#endif
509
510/**
511 * PCI Device structure.
512 */
513typedef struct PCIDevice
514{
515 /** PCI config space. */
516 uint8_t config[256];
517
518 /** Internal data. */
519 union
520 {
521#ifdef PCIDEVICEINT_DECLARED
522 PCIDEVICEINT s;
523#endif
524 char padding[328];
525 } Int;
526
527 /** Read only data.
528 * @{
529 */
530 /** PCI device number on the pci bus. */
531 int32_t devfn;
532 uint32_t Alignment0; /**< Alignment. */
533 /** Device name. */
534 R3PTRTYPE(const char *) name;
535 /** Pointer to the device instance which registered the device. */
536 PPDMDEVINSR3 pDevIns;
537 /** @} */
538} PCIDEVICE;
539
540/* @todo: handle extended space access */
541DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t uOffset, uint8_t u8Value)
542{
543 pPciDev->config[uOffset] = u8Value;
544}
545
546DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t uOffset)
547{
548 return pPciDev->config[uOffset];
549}
550
551DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint16_t u16Value)
552{
553 *(uint16_t*)&pPciDev->config[uOffset] = RT_H2LE_U16(u16Value);
554}
555
556DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t uOffset)
557{
558 uint16_t u16Value = *(uint16_t*)&pPciDev->config[uOffset];
559 return RT_H2LE_U16(u16Value);
560}
561
562DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint32_t u32Value)
563{
564 *(uint32_t*)&pPciDev->config[uOffset] = RT_H2LE_U32(u32Value);
565}
566
567DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t uOffset)
568{
569 uint32_t u32Value = *(uint32_t*)&pPciDev->config[uOffset];
570 return RT_H2LE_U32(u32Value);
571}
572
573DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t uOffset, uint64_t u64Value)
574{
575 *(uint64_t*)&pPciDev->config[uOffset] = RT_H2LE_U64(u64Value);
576}
577
578DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t uOffset)
579{
580 uint64_t u64Value = *(uint64_t*)&pPciDev->config[uOffset];
581 return RT_H2LE_U64(u64Value);
582}
583
584/**
585 * Sets the vendor id config register.
586 * @param pPciDev The PCI device.
587 * @param u16VendorId The vendor id.
588 */
589DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
590{
591 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
592}
593
594/**
595 * Gets the vendor id config register.
596 * @returns the vendor id.
597 * @param pPciDev The PCI device.
598 */
599DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
600{
601 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
602}
603
604
605/**
606 * Sets the device id config register.
607 * @param pPciDev The PCI device.
608 * @param u16DeviceId The device id.
609 */
610DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
611{
612 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
613}
614
615/**
616 * Gets the device id config register.
617 * @returns the device id.
618 * @param pPciDev The PCI device.
619 */
620DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
621{
622 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
623}
624
625/**
626 * Sets the command config register.
627 *
628 * @param pPciDev The PCI device.
629 * @param u16Command The command register value.
630 */
631DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
632{
633 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
634}
635
636
637/**
638 * Gets the command config register.
639 * @returns The command register value.
640 * @param pPciDev The PCI device.
641 */
642DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
643{
644 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
645}
646
647/**
648 * Checks if INTx interrupts disabled in the command config register.
649 * @returns true if disabled.
650 * @param pPciDev The PCI device.
651 */
652DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
653{
654 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
655}
656
657/**
658 * Gets the status config register.
659 *
660 * @returns status config register.
661 * @param pPciDev The PCI device.
662 */
663DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
664{
665 return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
666}
667
668/**
669 * Sets the status config register.
670 *
671 * @param pPciDev The PCI device.
672 * @param u16Status The status register value.
673 */
674DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
675{
676 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
677}
678
679
680/**
681 * Sets the revision id config register.
682 *
683 * @param pPciDev The PCI device.
684 * @param u8RevisionId The revision id.
685 */
686DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
687{
688 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
689}
690
691
692/**
693 * Sets the register level programming class config register.
694 *
695 * @param pPciDev The PCI device.
696 * @param u8ClassProg The new value.
697 */
698DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
699{
700 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
701}
702
703
704/**
705 * Sets the sub-class (aka device class) config register.
706 *
707 * @param pPciDev The PCI device.
708 * @param u8SubClass The sub-class.
709 */
710DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
711{
712 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
713}
714
715
716/**
717 * Sets the base class config register.
718 *
719 * @param pPciDev The PCI device.
720 * @param u8BaseClass The base class.
721 */
722DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
723{
724 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
725}
726
727/**
728 * Sets the header type config register.
729 *
730 * @param pPciDev The PCI device.
731 * @param u8HdrType The header type.
732 */
733DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
734{
735 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
736}
737
738/**
739 * Gets the header type config register.
740 *
741 * @param pPciDev The PCI device.
742 * @returns u8HdrType The header type.
743 */
744DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
745{
746 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
747}
748
749/**
750 * Sets the BIST (built-in self-test) config register.
751 *
752 * @param pPciDev The PCI device.
753 * @param u8Bist The BIST value.
754 */
755DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
756{
757 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
758}
759
760/**
761 * Gets the BIST (built-in self-test) config register.
762 *
763 * @param pPciDev The PCI device.
764 * @returns u8Bist The BIST.
765 */
766DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
767{
768 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
769}
770
771
772/**
773 * Sets a base address config register.
774 *
775 * @param pPciDev The PCI device.
776 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
777 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
778 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
779 * @param u32Addr The address value.
780 */
781DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
782{
783 if (fIOSpace)
784 {
785 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
786 u32Addr |= RT_BIT_32(0);
787 }
788 else
789 {
790 Assert(!(u32Addr & 0xf));
791 if (fPrefetchable)
792 u32Addr |= RT_BIT_32(3);
793 if (f64Bit)
794 u32Addr |= 0x2 << 1;
795 }
796 switch (iReg)
797 {
798 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
799 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
800 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
801 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
802 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
803 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
804 default: AssertFailedReturnVoid();
805 }
806
807 PCIDevSetDWord(pPciDev, iReg, u32Addr);
808}
809
810DECLINLINE(uint32_t) PCIDevGetRegionReg(int iRegion)
811{
812 return (iRegion == VBOX_PCI_ROM_SLOT) ?
813 VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
814}
815
816/**
817 * Sets the sub-system vendor id config register.
818 *
819 * @param pPciDev The PCI device.
820 * @param u16SubSysVendorId The sub-system vendor id.
821 */
822DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
823{
824 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
825}
826
827/**
828 * Gets the sub-system vendor id config register.
829 * @returns the sub-system vendor id.
830 * @param pPciDev The PCI device.
831 */
832DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
833{
834 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
835}
836
837
838/**
839 * Sets the sub-system id config register.
840 *
841 * @param pPciDev The PCI device.
842 * @param u16SubSystemId The sub-system id.
843 */
844DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
845{
846 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
847}
848
849/**
850 * Gets the sub-system id config register.
851 * @returns the sub-system id.
852 * @param pPciDev The PCI device.
853 */
854DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
855{
856 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
857}
858
859/**
860 * Sets offset to capability list.
861 *
862 * @param pPciDev The PCI device.
863 * @param u8Offset The offset to capability list.
864 */
865DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
866{
867 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
868}
869
870/**
871 * Returns offset to capability list.
872 *
873 * @returns offset to capability list.
874 * @param pPciDev The PCI device.
875 */
876DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
877{
878 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
879}
880
881/**
882 * Sets the interrupt line config register.
883 *
884 * @param pPciDev The PCI device.
885 * @param u8Line The interrupt line.
886 */
887DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
888{
889 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
890}
891
892/**
893 * Gets the interrupt line config register.
894 *
895 * @returns The interrupt line.
896 * @param pPciDev The PCI device.
897 */
898DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
899{
900 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
901}
902
903/**
904 * Sets the interrupt pin config register.
905 *
906 * @param pPciDev The PCI device.
907 * @param u8Pin The interrupt pin.
908 */
909DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
910{
911 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
912}
913
914/**
915 * Gets the interrupt pin config register.
916 *
917 * @returns The interrupt pin.
918 * @param pPciDev The PCI device.
919 */
920DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
921{
922 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
923}
924
925#ifdef PCIDEVICEINT_DECLARED
926DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev)
927{
928 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
929}
930
931DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev)
932{
933 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
934}
935
936DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev)
937{
938 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
939}
940
941DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev)
942{
943 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
944}
945
946DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev)
947{
948 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
949}
950
951DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev)
952{
953 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
954}
955
956DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev)
957{
958 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
959}
960
961DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev)
962{
963 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
964}
965
966DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev)
967{
968 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
969}
970
971DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev)
972{
973 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
974}
975
976DECLINLINE(void) pciDevSetMsi64Capable(PPCIDEVICE pDev)
977{
978 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI64_CAPABLE;
979}
980
981DECLINLINE(void) pciDevClearMsi64Capable(PPCIDEVICE pDev)
982{
983 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI64_CAPABLE;
984}
985
986DECLINLINE(bool) pciDevIsMsi64Capable(PPCIDEVICE pDev)
987{
988 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI64_CAPABLE) != 0;
989}
990
991DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev)
992{
993 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
994}
995
996DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev)
997{
998 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
999}
1000
1001DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev)
1002{
1003 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
1004}
1005
1006DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev)
1007{
1008 pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH;
1009}
1010
1011DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev)
1012{
1013 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH;
1014}
1015
1016DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev)
1017{
1018 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0;
1019}
1020
1021#endif /* PCIDEVICEINT_DECLARED */
1022
1023#if defined(__cplusplus) && defined(IN_RING3)
1024/* For RTStrPrintf(). */
1025#include <iprt/string.h>
1026
1027/**
1028 * Class representing PCI address. PCI device consist of
1029 * bus, device and function numbers. Generally device PCI
1030 * address could be changed during runtime, but only by
1031 * an OS PCI driver.
1032 *
1033 * @remarks C++ classes (structs included) are not generally accepted in
1034 * VMM devices or drivers. An exception may be granted for this class
1035 * if it's contained to ring-3 and that this is a one time exception
1036 * which sets no precedent.
1037 */
1038struct PciBusAddress
1039{
1040 /** @todo: think if we'll need domain, which is higher
1041 * word of the address. */
1042 int miBus;
1043 int miDevice;
1044 int miFn;
1045
1046 PciBusAddress()
1047 {
1048 clear();
1049 }
1050
1051 PciBusAddress(int iBus, int iDevice, int iFn)
1052 {
1053 init(iBus, iDevice, iFn);
1054 }
1055
1056 PciBusAddress(int32_t iAddr)
1057 {
1058 clear();
1059 fromLong(iAddr);
1060 }
1061
1062 PciBusAddress& clear()
1063 {
1064 miBus = miDevice = miFn = -1;
1065 return *this;
1066 }
1067
1068 void init(int iBus, int iDevice, int iFn)
1069 {
1070 miBus = iBus;
1071 miDevice = iDevice;
1072 miFn = iFn;
1073 }
1074
1075 void init(const PciBusAddress &a)
1076 {
1077 miBus = a.miBus;
1078 miDevice = a.miDevice;
1079 miFn = a.miFn;
1080 }
1081
1082 bool operator<(const PciBusAddress &a) const
1083 {
1084 if (miBus < a.miBus)
1085 return true;
1086
1087 if (miBus > a.miBus)
1088 return false;
1089
1090 if (miDevice < a.miDevice)
1091 return true;
1092
1093 if (miDevice > a.miDevice)
1094 return false;
1095
1096 if (miFn < a.miFn)
1097 return true;
1098
1099 if (miFn > a.miFn)
1100 return false;
1101
1102 return false;
1103 }
1104
1105 bool operator==(const PciBusAddress &a) const
1106 {
1107 return (miBus == a.miBus)
1108 && (miDevice == a.miDevice)
1109 && (miFn == a.miFn);
1110 }
1111
1112 bool operator!=(const PciBusAddress &a) const
1113 {
1114 return (miBus != a.miBus)
1115 || (miDevice != a.miDevice)
1116 || (miFn != a.miFn);
1117 }
1118
1119 bool valid() const
1120 {
1121 return (miBus != -1)
1122 && (miDevice != -1)
1123 && (miFn != -1);
1124 }
1125
1126 int32_t asLong() const
1127 {
1128 Assert(valid());
1129 return (miBus << 8) | (miDevice << 3) | miFn;
1130 }
1131
1132 PciBusAddress& fromLong(int32_t value)
1133 {
1134 miBus = (value >> 8) & 0xff;
1135 miDevice = (value & 0xff) >> 3;
1136 miFn = (value & 7);
1137 return *this;
1138 }
1139
1140 /** Create string representation of this PCI address. */
1141 bool format(char* szBuf, int32_t cBufSize)
1142 {
1143 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
1144 return false;
1145
1146 if (valid())
1147 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
1148 else
1149 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
1150
1151 return true;
1152 }
1153
1154 static const size_t cMaxAddrSize = 10;
1155};
1156#endif /* __cplusplus */
1157
1158/** @} */
1159
1160#endif
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