VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 64307

Last change on this file since 64307 was 64274, checked in by vboxsync, 8 years ago

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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @ingroup grp_devdrv
35 * @{
36 */
37
38/** Pointer to a PCI device. */
39typedef struct PCIDevice *PPCIDEVICE;
40
41
42/**
43 * PCI configuration word 4 (command) and word 6 (status).
44 */
45typedef enum PCICONFIGCOMMAND
46{
47 /** Supports/uses memory accesses. */
48 PCI_COMMAND_IOACCESS = 0x0001,
49 PCI_COMMAND_MEMACCESS = 0x0002,
50 PCI_COMMAND_BUSMASTER = 0x0004
51} PCICONFIGCOMMAND;
52
53
54/**
55 * PCI Address space specification.
56 * This is used when registering a I/O region.
57 */
58/**
59 * Defined by the PCI specification.
60 */
61typedef enum PCIADDRESSSPACE
62{
63 /** Memory. */
64 PCI_ADDRESS_SPACE_MEM = 0x00,
65 /** I/O space. */
66 PCI_ADDRESS_SPACE_IO = 0x01,
67 /** 32-bit BAR. */
68 PCI_ADDRESS_SPACE_BAR32 = 0x00,
69 /** 64-bit BAR. */
70 PCI_ADDRESS_SPACE_BAR64 = 0x04,
71 /** Prefetch memory. */
72 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
73} PCIADDRESSSPACE;
74
75
76/**
77 * Callback function for mapping an PCI I/O region.
78 *
79 * @return VBox status code.
80 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
81 * @param iRegion The region number.
82 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
83 * is an I/O port, otherwise it's a physical address.
84 *
85 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
86 * that the device deregister access handlers for it and update its internal
87 * state to reflect this.
88 *
89 * @param cb Size of the region in bytes.
90 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
91 *
92 * @remarks Called with the PDM lock held. The device lock is NOT take because
93 * that is very likely be a lock order violation.
94 */
95typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress,
96 RTGCPHYS cb, PCIADDRESSSPACE enmType);
97/** Pointer to a FNPCIIOREGIONMAP() function. */
98typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
99
100
101/** @name PCI Configuration Space Registers
102 * @{ */
103/* Commented out values common for different header types */
104/* Common part of the header */
105#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
106#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
107#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
108#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
109#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
110#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
111#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
112#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
113#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
114#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
115#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
116#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
117#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
118#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
119#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
120#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
121
122/* Type 0 header, device */
123#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
124#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
125#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
126#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
127#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
128#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
129#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
130#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
131#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
132#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
133/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
134#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
135#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
136#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
137#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
138/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
139/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
140#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
141#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
142
143/* Type 1 header, PCI-to-PCI bridge */
144/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
145/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
146#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
147#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
148#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
149#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
150#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
151#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
152#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
153#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
154#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
155#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
156#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
157#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
158#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
159#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
160#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
161/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
162/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
163/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
164/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
165#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
166#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
167
168/* Type 2 header, PCI-to-CardBus bridge */
169#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
170#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
171#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
172#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
173#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
174#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
175/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
176/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
177#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
178#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
179#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
180#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
181#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
182#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
183#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
184#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
185/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
186/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
187/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
188/** @} */
189
190
191/* Possible values in status bitmask */
192#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
193#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
194#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
195#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
196#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
197#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
198#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
199#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
200#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
201#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
202#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
203#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
204#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
205#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
206
207
208/* Command bitmask */
209#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
210#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
211#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
212#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
213#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
214#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
215#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
216#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
217#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
218#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
219#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
220
221
222/* Capability list values (capability offset 0) */
223/* Next value pointer in offset 1, or 0 if none */
224#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
225#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
226#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
227#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
228#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
229#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
230#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
231#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
232#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
233#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
234#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
235#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
236#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
237#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
238#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
239#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
240#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
241#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
242#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
243
244/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
245#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
246#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
247#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
248#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
249#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
250#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
251#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
252#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
253#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
254#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
255#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
256#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
257#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
258#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
259
260
261/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
262#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
263#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
264#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
265/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
266 someone very similar to log_2().
267 000 1
268 001 2
269 010 4
270 011 8
271 100 16
272 101 32
273 110 Reserved
274 111 Reserved */
275#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
276#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
277
278/* MSI-X flags (2 bytes, capability offset 2) */
279#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
280#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
281
282/* Power management flags (2 bytes, capability offset 2) */
283#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
284#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
285#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
286#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
287#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
288#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
289#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
290#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
291#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
292#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
293#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
294#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
295#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
296#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
297
298/* Power management control flags (2 bytes, capability offset 4) */
299#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
300#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
301#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
302#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
303#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
304#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
305
306/* PCI-X config flags (2 bytes, capability offset 2) */
307#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
308#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
309#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
310#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
311#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
312#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
313#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
314#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
315
316/* PCI-X config flags (4 bytes, capability offset 4) */
317#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
318#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
319#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
320#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
321#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
322#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
323#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
324#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
325#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
326#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
327#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
328#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
329#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
330
331/* PCI Express config flags (2 bytes, capability offset 2) */
332#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
333#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
334#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
335#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
336#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
337#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
338#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
339#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
340#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
341#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
342#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
343#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
344#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
345
346/* PCI Express device capabilities (4 bytes, capability offset 4) */
347#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
348#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
349#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
350#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
351#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
352#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
353#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
354#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
355#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
356#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
357#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
358#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
359
360/* PCI Express device control (2 bytes, capability offset 8) */
361#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
362#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
363#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
364#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
365#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
366#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
367#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
368#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
369#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
370#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
371#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
372#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
373#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
374
375/* PCI Express device status (2 bytes, capability offset 10) */
376#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
377#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
378#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
379#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
380#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
381#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
382
383/* PCI Express link capabilities (4 bytes, capability offset 12) */
384#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
385#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
386#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
387#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
388#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
389#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
390#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
391#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
392#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
393#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
394
395/* PCI Express link control (2 bytes, capability offset 16) */
396#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
397#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
398#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
399#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
400#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
401#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
402#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
403#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
404#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
405#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
406
407/* PCI Express link status (2 bytes, capability offset 18) */
408#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
409#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
410#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
411#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
412#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
413#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
414#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
415#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
416
417/* PCI Express slot capabilities (4 bytes, capability offset 20) */
418#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
419#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
420#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
421#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
422#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
423#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
424#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
425#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
426#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
427#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
428#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
429#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
430
431/* PCI Express slot control (2 bytes, capability offset 24) */
432#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
433#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
434#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
435#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
436#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
437#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
438#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
439#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
440#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
441#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
442#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
443
444/* PCI Express slot status (2 bytes, capability offset 26) */
445#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
446#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
447#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
448#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
449#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
450#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
451#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
452#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
453#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
454
455/* PCI Express root control (2 bytes, capability offset 28) */
456#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
457#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
458#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
459#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
460#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
461
462/* PCI Express root capabilities (2 bytes, capability offset 30) */
463#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
464
465/* PCI Express root status (4 bytes, capability offset 32) */
466#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
467#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
468#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
469
470
471/**
472 * Callback function for reading from the PCI configuration space.
473 *
474 * @returns The register value.
475 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
476 * @param Address The configuration space register address. [0..4096]
477 * @param cb The register size. [1,2,4]
478 *
479 * @remarks Called with the PDM lock held. The device lock is NOT take because
480 * that is very likely be a lock order violation.
481 */
482typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
483/** Pointer to a FNPCICONFIGREAD() function. */
484typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
485/** Pointer to a PFNPCICONFIGREAD. */
486typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
487
488/**
489 * Callback function for writing to the PCI configuration space.
490 *
491 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
492 * @param Address The configuration space register address. [0..4096]
493 * @param u32Value The value that's being written. The number of bits actually used from
494 * this value is determined by the cb parameter.
495 * @param cb The register size. [1,2,4]
496 *
497 * @remarks Called with the PDM lock held. The device lock is NOT take because
498 * that is very likely be a lock order violation.
499 */
500typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
501/** Pointer to a FNPCICONFIGWRITE() function. */
502typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
503/** Pointer to a PFNPCICONFIGWRITE. */
504typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
505
506/** Fixed I/O region number for ROM. */
507#define PCI_ROM_SLOT 6
508#define VBOX_PCI_ROM_SLOT 6
509/** Max number of I/O regions. */
510#define PCI_NUM_REGIONS 7
511#define VBOX_PCI_NUM_REGIONS 7
512
513/*
514 * Hack to include the PCIDEVICEINT structure at the right place
515 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
516 */
517#ifdef PCI_INCLUDE_PRIVATE
518# include "PCIInternal.h"
519#endif
520
521/**
522 * PCI Device structure.
523 */
524typedef struct PCIDevice
525{
526 /** PCI config space. */
527 uint8_t config[256];
528
529 /** Internal data. */
530 union
531 {
532#ifdef PCIDEVICEINT_DECLARED
533 PCIDEVICEINT s;
534#endif
535 char padding[328];
536 } Int;
537
538 /** Read only data.
539 * @{
540 */
541 /** PCI device number on the pci bus. */
542 int32_t devfn;
543 uint32_t Alignment0; /**< Alignment. */
544 /** Device name. */
545 R3PTRTYPE(const char *) name;
546 /** Pointer to the device instance which registered the device. */
547 PPDMDEVINSR3 pDevIns;
548 /** @} */
549} PCIDEVICE;
550
551/** @todo handle extended space access. */
552
553DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t offReg, uint8_t u8Value)
554{
555 pPciDev->config[offReg] = u8Value;
556}
557
558DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t offReg)
559{
560 return pPciDev->config[offReg];
561}
562
563DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t offReg, uint16_t u16Value)
564{
565 *(uint16_t*)&pPciDev->config[offReg] = RT_H2LE_U16(u16Value);
566}
567
568DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t offReg)
569{
570 uint16_t u16Value = *(uint16_t*)&pPciDev->config[offReg];
571 return RT_H2LE_U16(u16Value);
572}
573
574DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t offReg, uint32_t u32Value)
575{
576 *(uint32_t*)&pPciDev->config[offReg] = RT_H2LE_U32(u32Value);
577}
578
579DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t offReg)
580{
581 uint32_t u32Value = *(uint32_t*)&pPciDev->config[offReg];
582 return RT_H2LE_U32(u32Value);
583}
584
585DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t offReg, uint64_t u64Value)
586{
587 *(uint64_t*)&pPciDev->config[offReg] = RT_H2LE_U64(u64Value);
588}
589
590DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t offReg)
591{
592 uint64_t u64Value = *(uint64_t*)&pPciDev->config[offReg];
593 return RT_H2LE_U64(u64Value);
594}
595
596/**
597 * Sets the vendor id config register.
598 * @param pPciDev The PCI device.
599 * @param u16VendorId The vendor id.
600 */
601DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
602{
603 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
604}
605
606/**
607 * Gets the vendor id config register.
608 * @returns the vendor id.
609 * @param pPciDev The PCI device.
610 */
611DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
612{
613 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
614}
615
616
617/**
618 * Sets the device id config register.
619 * @param pPciDev The PCI device.
620 * @param u16DeviceId The device id.
621 */
622DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
623{
624 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
625}
626
627/**
628 * Gets the device id config register.
629 * @returns the device id.
630 * @param pPciDev The PCI device.
631 */
632DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
633{
634 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
635}
636
637/**
638 * Sets the command config register.
639 *
640 * @param pPciDev The PCI device.
641 * @param u16Command The command register value.
642 */
643DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
644{
645 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
646}
647
648
649/**
650 * Gets the command config register.
651 * @returns The command register value.
652 * @param pPciDev The PCI device.
653 */
654DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
655{
656 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
657}
658
659/**
660 * Checks if the given PCI device is a bus master.
661 * @returns true if the device is a bus master, false if not.
662 * @param pPciDev The PCI device.
663 */
664DECLINLINE(bool) PCIDevIsBusmaster(PPCIDEVICE pPciDev)
665{
666 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_MASTER) != 0;
667}
668
669/**
670 * Checks if INTx interrupts disabled in the command config register.
671 * @returns true if disabled.
672 * @param pPciDev The PCI device.
673 */
674DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
675{
676 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
677}
678
679/**
680 * Gets the status config register.
681 *
682 * @returns status config register.
683 * @param pPciDev The PCI device.
684 */
685DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
686{
687 return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
688}
689
690/**
691 * Sets the status config register.
692 *
693 * @param pPciDev The PCI device.
694 * @param u16Status The status register value.
695 */
696DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
697{
698 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
699}
700
701
702/**
703 * Sets the revision id config register.
704 *
705 * @param pPciDev The PCI device.
706 * @param u8RevisionId The revision id.
707 */
708DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
709{
710 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
711}
712
713
714/**
715 * Sets the register level programming class config register.
716 *
717 * @param pPciDev The PCI device.
718 * @param u8ClassProg The new value.
719 */
720DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
721{
722 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
723}
724
725
726/**
727 * Sets the sub-class (aka device class) config register.
728 *
729 * @param pPciDev The PCI device.
730 * @param u8SubClass The sub-class.
731 */
732DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
733{
734 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
735}
736
737
738/**
739 * Sets the base class config register.
740 *
741 * @param pPciDev The PCI device.
742 * @param u8BaseClass The base class.
743 */
744DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
745{
746 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
747}
748
749/**
750 * Sets the header type config register.
751 *
752 * @param pPciDev The PCI device.
753 * @param u8HdrType The header type.
754 */
755DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
756{
757 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
758}
759
760/**
761 * Gets the header type config register.
762 *
763 * @param pPciDev The PCI device.
764 * @returns u8HdrType The header type.
765 */
766DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
767{
768 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
769}
770
771/**
772 * Sets the BIST (built-in self-test) config register.
773 *
774 * @param pPciDev The PCI device.
775 * @param u8Bist The BIST value.
776 */
777DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
778{
779 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
780}
781
782/**
783 * Gets the BIST (built-in self-test) config register.
784 *
785 * @param pPciDev The PCI device.
786 * @returns u8Bist The BIST.
787 */
788DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
789{
790 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
791}
792
793
794/**
795 * Sets a base address config register.
796 *
797 * @param pPciDev The PCI device.
798 * @param iReg Base address register number (0..5).
799 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
800 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
801 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
802 * @param u32Addr The address value.
803 */
804DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit,
805 uint32_t u32Addr)
806{
807 if (fIOSpace)
808 {
809 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
810 u32Addr |= RT_BIT_32(0);
811 }
812 else
813 {
814 Assert(!(u32Addr & 0xf));
815 if (fPrefetchable)
816 u32Addr |= RT_BIT_32(3);
817 if (f64Bit)
818 u32Addr |= 0x2 << 1;
819 }
820 switch (iReg)
821 {
822 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
823 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
824 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
825 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
826 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
827 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
828 default: AssertFailedReturnVoid();
829 }
830
831 PCIDevSetDWord(pPciDev, iReg, u32Addr);
832}
833
834/**
835 * Please document me. I don't seem to be getting as much as calculating
836 * the address of some PCI region.
837 */
838DECLINLINE(uint32_t) PCIDevGetRegionReg(uint32_t iRegion)
839{
840 return iRegion == VBOX_PCI_ROM_SLOT
841 ? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
842}
843
844/**
845 * Sets the sub-system vendor id config register.
846 *
847 * @param pPciDev The PCI device.
848 * @param u16SubSysVendorId The sub-system vendor id.
849 */
850DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
851{
852 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
853}
854
855/**
856 * Gets the sub-system vendor id config register.
857 * @returns the sub-system vendor id.
858 * @param pPciDev The PCI device.
859 */
860DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
861{
862 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
863}
864
865
866/**
867 * Sets the sub-system id config register.
868 *
869 * @param pPciDev The PCI device.
870 * @param u16SubSystemId The sub-system id.
871 */
872DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
873{
874 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
875}
876
877/**
878 * Gets the sub-system id config register.
879 * @returns the sub-system id.
880 * @param pPciDev The PCI device.
881 */
882DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
883{
884 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
885}
886
887/**
888 * Sets offset to capability list.
889 *
890 * @param pPciDev The PCI device.
891 * @param u8Offset The offset to capability list.
892 */
893DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
894{
895 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
896}
897
898/**
899 * Returns offset to capability list.
900 *
901 * @returns offset to capability list.
902 * @param pPciDev The PCI device.
903 */
904DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
905{
906 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
907}
908
909/**
910 * Sets the interrupt line config register.
911 *
912 * @param pPciDev The PCI device.
913 * @param u8Line The interrupt line.
914 */
915DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
916{
917 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
918}
919
920/**
921 * Gets the interrupt line config register.
922 *
923 * @returns The interrupt line.
924 * @param pPciDev The PCI device.
925 */
926DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
927{
928 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
929}
930
931/**
932 * Sets the interrupt pin config register.
933 *
934 * @param pPciDev The PCI device.
935 * @param u8Pin The interrupt pin.
936 */
937DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
938{
939 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
940}
941
942/**
943 * Gets the interrupt pin config register.
944 *
945 * @returns The interrupt pin.
946 * @param pPciDev The PCI device.
947 */
948DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
949{
950 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
951}
952
953#ifdef PCIDEVICEINT_DECLARED
954DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev)
955{
956 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
957}
958
959DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev)
960{
961 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
962}
963
964DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev)
965{
966 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
967}
968
969DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev)
970{
971 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
972}
973
974DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev)
975{
976 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
977}
978
979DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev)
980{
981 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
982}
983
984DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev)
985{
986 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
987}
988
989DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev)
990{
991 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
992}
993
994DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev)
995{
996 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
997}
998
999DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev)
1000{
1001 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
1002}
1003
1004DECLINLINE(void) pciDevSetMsi64Capable(PPCIDEVICE pDev)
1005{
1006 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI64_CAPABLE;
1007}
1008
1009DECLINLINE(void) pciDevClearMsi64Capable(PPCIDEVICE pDev)
1010{
1011 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI64_CAPABLE;
1012}
1013
1014DECLINLINE(bool) pciDevIsMsi64Capable(PPCIDEVICE pDev)
1015{
1016 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI64_CAPABLE) != 0;
1017}
1018
1019DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev)
1020{
1021 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
1022}
1023
1024DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev)
1025{
1026 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
1027}
1028
1029DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev)
1030{
1031 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
1032}
1033
1034DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev)
1035{
1036 pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH;
1037}
1038
1039DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev)
1040{
1041 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH;
1042}
1043
1044DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev)
1045{
1046 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0;
1047}
1048
1049#endif /* PCIDEVICEINT_DECLARED */
1050
1051#if defined(__cplusplus) && defined(IN_RING3)
1052/* For RTStrPrintf(). */
1053#include <iprt/string.h>
1054
1055/**
1056 * Class representing PCI address. PCI device consist of
1057 * bus, device and function numbers. Generally device PCI
1058 * address could be changed during runtime, but only by
1059 * an OS PCI driver.
1060 *
1061 * @remarks C++ classes (structs included) are not generally accepted in
1062 * VMM devices or drivers. An exception may be granted for this class
1063 * if it's contained to ring-3 and that this is a one time exception
1064 * which sets no precedent.
1065 */
1066struct PCIBusAddress
1067{
1068 /** @todo: think if we'll need domain, which is higher
1069 * word of the address. */
1070 int miBus;
1071 int miDevice;
1072 int miFn;
1073
1074 PCIBusAddress()
1075 {
1076 clear();
1077 }
1078
1079 PCIBusAddress(int iBus, int iDevice, int iFn)
1080 {
1081 init(iBus, iDevice, iFn);
1082 }
1083
1084 PCIBusAddress(int32_t iAddr)
1085 {
1086 clear();
1087 fromLong(iAddr);
1088 }
1089
1090 PCIBusAddress& clear()
1091 {
1092 miBus = miDevice = miFn = -1;
1093 return *this;
1094 }
1095
1096 void init(int iBus, int iDevice, int iFn)
1097 {
1098 miBus = iBus;
1099 miDevice = iDevice;
1100 miFn = iFn;
1101 }
1102
1103 void init(const PCIBusAddress &a)
1104 {
1105 miBus = a.miBus;
1106 miDevice = a.miDevice;
1107 miFn = a.miFn;
1108 }
1109
1110 bool operator<(const PCIBusAddress &a) const
1111 {
1112 if (miBus < a.miBus)
1113 return true;
1114
1115 if (miBus > a.miBus)
1116 return false;
1117
1118 if (miDevice < a.miDevice)
1119 return true;
1120
1121 if (miDevice > a.miDevice)
1122 return false;
1123
1124 if (miFn < a.miFn)
1125 return true;
1126
1127 if (miFn > a.miFn)
1128 return false;
1129
1130 return false;
1131 }
1132
1133 bool operator==(const PCIBusAddress &a) const
1134 {
1135 return (miBus == a.miBus)
1136 && (miDevice == a.miDevice)
1137 && (miFn == a.miFn);
1138 }
1139
1140 bool operator!=(const PCIBusAddress &a) const
1141 {
1142 return (miBus != a.miBus)
1143 || (miDevice != a.miDevice)
1144 || (miFn != a.miFn);
1145 }
1146
1147 bool valid() const
1148 {
1149 return (miBus != -1)
1150 && (miDevice != -1)
1151 && (miFn != -1);
1152 }
1153
1154 int32_t asLong() const
1155 {
1156 Assert(valid());
1157 return (miBus << 8) | (miDevice << 3) | miFn;
1158 }
1159
1160 PCIBusAddress& fromLong(int32_t value)
1161 {
1162 miBus = (value >> 8) & 0xff;
1163 miDevice = (value & 0xff) >> 3;
1164 miFn = (value & 7);
1165 return *this;
1166 }
1167
1168 /** Create string representation of this PCI address. */
1169 bool format(char* szBuf, int32_t cBufSize)
1170 {
1171 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
1172 return false;
1173
1174 if (valid())
1175 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
1176 else
1177 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
1178
1179 return true;
1180 }
1181
1182 static const size_t cMaxAddrSize = 10;
1183};
1184#endif /* __cplusplus */
1185
1186/** @} */
1187
1188#endif
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