VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 10819

Last change on this file since 10819 was 9330, checked in by vboxsync, 17 years ago

More PCI config register setters.
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1/** @file
2 * PCI - The PCI Controller And Devices.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_pci_h
31#define ___VBox_pci_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <iprt/assert.h>
36
37/** @defgroup grp_pci PCI - The PCI Controller.
38 * @{
39 */
40
41/** Pointer to a PCI device. */
42typedef struct PCIDevice *PPCIDEVICE;
43
44
45/**
46 * PCI configuration word 4 (command) and word 6 (status).
47 */
48typedef enum PCICONFIGCOMMAND
49{
50 /** Supports/uses memory accesses. */
51 PCI_COMMAND_IOACCESS = 0x0001,
52 PCI_COMMAND_MEMACCESS = 0x0002,
53 PCI_COMMAND_BUSMASTER = 0x0004
54} PCICONFIGCOMMAND;
55
56
57/**
58 * PCI Address space specification.
59 * This is used when registering a I/O region.
60 */
61/** Note: There are all sorts of dirty dependencies on the values in the
62 * pci device. Be careful when changing this.
63 * @todo we should introduce 32 & 64 bits physical address types
64 */
65typedef enum PCIADDRESSSPACE
66{
67 /** Memory. */
68 PCI_ADDRESS_SPACE_MEM = 0x00,
69 /** I/O space. */
70 PCI_ADDRESS_SPACE_IO = 0x01,
71 /** Prefetch memory. */
72 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
73} PCIADDRESSSPACE;
74
75
76/**
77 * Callback function for mapping an PCI I/O region.
78 *
79 * @return VBox status code.
80 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
81 * @param iRegion The region number.
82 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
83 * is an I/O port, otherwise it's a physical address.
84 *
85 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
86 * that the device deregister access handlers for it and update its internal
87 * state to reflect this.
88 *
89 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
90 *
91 * @remarks The address is *NOT* relative to pci_mem_base.
92 */
93typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
94/** Pointer to a FNPCIIOREGIONMAP() function. */
95typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
96
97
98/** @name PCI Configuration Space Registers
99 * @{ */
100#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
101#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
102#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW */
103#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW */
104#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO */
105#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
106#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
107#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
108#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
109#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit ?? */
110#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit ?? */
111#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit ?? */
112#define VBOX_PCI_BIST 0x0f /**< 8-bit ?? */
113#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
114#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
115#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
116#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - bridge - primary bus number. */
117#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - bridge - secondary bus number. */
118#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - bridge - highest subordinate bus number. (behind the bridge) */
119#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - bridge - secondary latency timer. */
120#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
121#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - bridge - I/O range base. */
122#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - bridge - I/O range limit. */
123#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - bridge - secondary status register. */
124#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
125#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - bridge - memory range base. */
126#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - bridge - memory range limit. */
127#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
128#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - bridge - Prefetchable memory range base. */
129#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - bridge - Prefetchable memory range limit. */
130#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
131#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - bridge - Prefetchable memory range high base.*/
132#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - bridge - Prefetchable memory range high limit. */
133#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit ?? */
134#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit ?? */
135#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
136#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - bridge - memory range high base. */
137#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - bridge - memory range high limit. */
138#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit? ?? */
139#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - bridge */
140#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - Interrupt line. */
141#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - Interrupt pin. */
142#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit ?? */
143#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 8-bit? ?? - bridge */
144#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit ?? */
145/** @} */
146
147
148/**
149 * Callback function for reading from the PCI configuration space.
150 *
151 * @returns The register value.
152 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
153 * @param Address The configuration space register address. [0..255]
154 * @param cb The register size. [1,2,4]
155 */
156typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
157/** Pointer to a FNPCICONFIGREAD() function. */
158typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
159/** Pointer to a PFNPCICONFIGREAD. */
160typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
161
162/**
163 * Callback function for writing to the PCI configuration space.
164 *
165 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
166 * @param Address The configuration space register address. [0..255]
167 * @param u32Value The value that's being written. The number of bits actually used from
168 * this value is determined by the cb parameter.
169 * @param cb The register size. [1,2,4]
170 */
171typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
172/** Pointer to a FNPCICONFIGWRITE() function. */
173typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
174/** Pointer to a PFNPCICONFIGWRITE. */
175typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
176
177/** Fixed I/O region number for ROM. */
178#define PCI_ROM_SLOT 6
179/** Max number of I/O regions. */
180#define PCI_NUM_REGIONS 7
181
182/*
183 * Hack to include the PCIDEVICEINT structure at the right place
184 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
185 */
186#ifdef PCI_INCLUDE_PRIVATE
187# include "PCIInternal.h"
188#endif
189
190/**
191 * PCI Device structure.
192 */
193typedef struct PCIDevice
194{
195 /** PCI config space. */
196 uint8_t config[256];
197
198 /** Internal data. */
199 union
200 {
201#ifdef __PCIDEVICEINT_DECLARED__
202 PCIDEVICEINT s;
203#endif
204 char padding[224];
205 } Int;
206
207 /** Read only data.
208 * @{
209 */
210 /** PCI device number on the pci bus. */
211 int32_t devfn;
212 uint32_t Alignment0; /**< Alignment. */
213 /** Device name. */
214 R3PTRTYPE(const char *) name;
215 /** Pointer to the device instance which registered the device. */
216 PPDMDEVINSR3 pDevIns;
217 /** @} */
218} PCIDEVICE;
219
220
221/**
222 * Sets the vendor id config register.
223 * @param pPciDev The PCI device.
224 * @param u16VendorId The vendor id.
225 */
226DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
227{
228 u16VendorId = RT_H2LE_U16(u16VendorId);
229 pPciDev->config[VBOX_PCI_VENDOR_ID] = u16VendorId & 0xff;
230 pPciDev->config[VBOX_PCI_VENDOR_ID + 1] = u16VendorId >> 8;
231}
232
233/**
234 * Gets the vendor id config register.
235 * @returns the vendor id.
236 * @param pPciDev The PCI device.
237 */
238DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
239{
240 return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_VENDOR_ID], pPciDev->config[VBOX_PCI_VENDOR_ID + 1]));
241}
242
243
244/**
245 * Sets the device id config register.
246 * @param pPciDev The PCI device.
247 * @param u16DeviceId The device id.
248 */
249DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
250{
251 u16DeviceId = RT_H2LE_U16(u16DeviceId);
252 pPciDev->config[VBOX_PCI_DEVICE_ID] = u16DeviceId & 0xff;
253 pPciDev->config[VBOX_PCI_DEVICE_ID + 1] = u16DeviceId >> 8;
254}
255
256/**
257 * Gets the device id config register.
258 * @returns the device id.
259 * @param pPciDev The PCI device.
260 */
261DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
262{
263 return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_DEVICE_ID], pPciDev->config[VBOX_PCI_DEVICE_ID + 1]));
264}
265
266
267/**
268 * Sets the command config register.
269 *
270 * @param pPciDev The PCI device.
271 * @param u16Command The command register value.
272 */
273DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
274{
275 u16Command = RT_H2LE_U16(u16Command);
276 pPciDev->config[VBOX_PCI_COMMAND] = u16Command & 0xff;
277 pPciDev->config[VBOX_PCI_COMMAND + 1] = u16Command >> 8;
278}
279
280
281/**
282 * Sets the status config register.
283 *
284 * @param pPciDev The PCI device.
285 * @param u16Status The status register value.
286 */
287DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
288{
289 u16Status = RT_H2LE_U16(u16Status);
290 pPciDev->config[VBOX_PCI_STATUS] = u16Status & 0xff;
291 pPciDev->config[VBOX_PCI_STATUS + 1] = u16Status >> 8;
292}
293
294
295/**
296 * Sets the revision id config register.
297 *
298 * @param pPciDev The PCI device.
299 * @param u8RevisionId The revision id.
300 */
301DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
302{
303 pPciDev->config[VBOX_PCI_REVISION_ID] = u8RevisionId;
304}
305
306
307/**
308 * Sets the register level programming class config register.
309 *
310 * @param pPciDev The PCI device.
311 * @param u8ClassProg The new value.
312 */
313DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
314{
315 pPciDev->config[VBOX_PCI_CLASS_PROG] = u8ClassProg;
316}
317
318
319/**
320 * Sets the sub-class (aka device class) config register.
321 *
322 * @param pPciDev The PCI device.
323 * @param u8SubClass The sub-class.
324 */
325DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
326{
327 pPciDev->config[VBOX_PCI_CLASS_SUB] = u8SubClass;
328}
329
330
331/**
332 * Sets the base class config register.
333 *
334 * @param pPciDev The PCI device.
335 * @param u8BaseClass The base class.
336 */
337DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
338{
339 pPciDev->config[VBOX_PCI_CLASS_BASE] = u8BaseClass;
340}
341
342
343/**
344 * Sets the header type config register.
345 *
346 * @param pPciDev The PCI device.
347 * @param u8HdrType The header type.
348 */
349DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
350{
351 pPciDev->config[VBOX_PCI_HEADER_TYPE] = u8HdrType;
352}
353
354
355/**
356 * Sets a base address config register.
357 *
358 * @param pPciDev The PCI device.
359 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
360 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
361 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
362 * @param u32Addr The address value.
363 */
364DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
365{
366 if (fIOSpace)
367 {
368 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
369 u32Addr |= RT_BIT_32(0);
370 }
371 else
372 {
373 Assert(!(u32Addr & 0xf));
374 if (fPrefetchable)
375 u32Addr |= RT_BIT_32(3);
376 if (f64Bit)
377 u32Addr |= 0x2 << 1;
378 }
379 switch (iReg)
380 {
381 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
382 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
383 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
384 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
385 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
386 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
387 default: AssertFailedReturnVoid();
388 }
389
390 u32Addr = RT_H2LE_U32(u32Addr);
391 pPciDev->config[iReg] = u32Addr & 0xff;
392 pPciDev->config[iReg + 1] = (u32Addr >> 16) & 0xff;
393 pPciDev->config[iReg + 2] = (u32Addr >> 16) & 0xff;
394 pPciDev->config[iReg + 3] = (u32Addr >> 24) & 0xff;
395}
396
397
398/**
399 * Sets the sub-system vendor id config register.
400 *
401 * @param pPciDev The PCI device.
402 * @param u16SubSysVendorId The sub-system vendor id.
403 */
404DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
405{
406 u16SubSysVendorId = RT_H2LE_U16(u16SubSysVendorId);
407 pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID] = u16SubSysVendorId & 0xff;
408 pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1] = u16SubSysVendorId >> 8;
409}
410
411/**
412 * Gets the sub-system vendor id config register.
413 * @returns the sub-system vendor id.
414 * @param pPciDev The PCI device.
415 */
416DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
417{
418 return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1]));
419}
420
421
422/**
423 * Sets the sub-system id config register.
424 *
425 * @param pPciDev The PCI device.
426 * @param u16SubSystemId The sub-system id.
427 */
428DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
429{
430 u16SubSystemId = RT_H2LE_U16(u16SubSystemId);
431 pPciDev->config[VBOX_PCI_SUBSYSTEM_ID] = u16SubSystemId & 0xff;
432 pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1] = u16SubSystemId >> 8;
433}
434
435/**
436 * Gets the sub-system id config register.
437 * @returns the sub-system id.
438 * @param pPciDev The PCI device.
439 */
440DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
441{
442 return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1]));
443}
444
445
446/**
447 * Sets the interrupt line config register.
448 *
449 * @param pPciDev The PCI device.
450 * @param u8Line The interrupt line.
451 */
452DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
453{
454 pPciDev->config[VBOX_PCI_INTERRUPT_LINE] = u8Line;
455}
456
457
458/**
459 * Sets the interrupt pin config register.
460 *
461 * @param pPciDev The PCI device.
462 * @param u8Pin The interrupt pin.
463 */
464DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
465{
466 pPciDev->config[VBOX_PCI_INTERRUPT_PIN] = u8Pin;
467}
468
469
470/** @} */
471
472#endif
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