1 | /** @file
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2 | * PCI - The PCI Controller And Devices.
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | *
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25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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27 | * additional information or have any questions.
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28 | */
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29 |
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30 | #ifndef ___VBox_pci_h
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31 | #define ___VBox_pci_h
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32 |
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33 | #include <VBox/cdefs.h>
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34 | #include <VBox/types.h>
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35 | #include <iprt/assert.h>
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36 |
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37 | /** @defgroup grp_pci PCI - The PCI Controller.
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38 | * @{
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39 | */
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40 |
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41 | /** Pointer to a PCI device. */
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42 | typedef struct PCIDevice *PPCIDEVICE;
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43 |
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44 |
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45 | /**
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46 | * PCI configuration word 4 (command) and word 6 (status).
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47 | */
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48 | typedef enum PCICONFIGCOMMAND
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49 | {
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50 | /** Supports/uses memory accesses. */
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51 | PCI_COMMAND_IOACCESS = 0x0001,
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52 | PCI_COMMAND_MEMACCESS = 0x0002,
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53 | PCI_COMMAND_BUSMASTER = 0x0004
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54 | } PCICONFIGCOMMAND;
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55 |
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56 |
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57 | /**
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58 | * PCI Address space specification.
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59 | * This is used when registering a I/O region.
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60 | */
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61 | /** Note: There are all sorts of dirty dependencies on the values in the
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62 | * pci device. Be careful when changing this.
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63 | * @todo we should introduce 32 & 64 bits physical address types
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64 | */
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65 | typedef enum PCIADDRESSSPACE
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66 | {
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67 | /** Memory. */
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68 | PCI_ADDRESS_SPACE_MEM = 0x00,
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69 | /** I/O space. */
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70 | PCI_ADDRESS_SPACE_IO = 0x01,
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71 | /** Prefetch memory. */
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72 | PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
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73 | } PCIADDRESSSPACE;
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74 |
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75 |
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76 | /**
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77 | * Callback function for mapping an PCI I/O region.
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78 | *
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79 | * @return VBox status code.
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80 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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81 | * @param iRegion The region number.
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82 | * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
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83 | * is an I/O port, otherwise it's a physical address.
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84 | *
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85 | * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
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86 | * that the device deregister access handlers for it and update its internal
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87 | * state to reflect this.
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88 | *
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89 | * @param enmType One of the PCI_ADDRESS_SPACE_* values.
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90 | *
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91 | * @remarks The address is *NOT* relative to pci_mem_base.
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92 | */
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93 | typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
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94 | /** Pointer to a FNPCIIOREGIONMAP() function. */
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95 | typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
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96 |
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97 |
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98 | /** @name PCI Configuration Space Registers
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99 | * @{ */
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100 | #define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
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101 | #define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
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102 | #define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW */
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103 | #define VBOX_PCI_STATUS 0x06 /**< 16-bit RW */
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104 | #define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO */
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105 | #define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
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106 | #define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
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107 | #define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
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108 | #define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
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109 | #define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit ?? */
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110 | #define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit ?? */
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111 | #define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit ?? */
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112 | #define VBOX_PCI_BIST 0x0f /**< 8-bit ?? */
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113 | #define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
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114 | #define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
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115 | #define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
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116 | #define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - bridge - primary bus number. */
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117 | #define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - bridge - secondary bus number. */
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118 | #define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - bridge - highest subordinate bus number. (behind the bridge) */
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119 | #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - bridge - secondary latency timer. */
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120 | #define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
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121 | #define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - bridge - I/O range base. */
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122 | #define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - bridge - I/O range limit. */
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123 | #define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - bridge - secondary status register. */
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124 | #define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
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125 | #define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - bridge - memory range base. */
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126 | #define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - bridge - memory range limit. */
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127 | #define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
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128 | #define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - bridge - Prefetchable memory range base. */
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129 | #define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - bridge - Prefetchable memory range limit. */
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130 | #define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
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131 | #define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - bridge - Prefetchable memory range high base.*/
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132 | #define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - bridge - Prefetchable memory range high limit. */
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133 | #define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit ?? */
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134 | #define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit ?? */
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135 | #define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
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136 | #define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - bridge - memory range high base. */
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137 | #define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - bridge - memory range high limit. */
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138 | #define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit? ?? */
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139 | #define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - bridge */
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140 | #define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - Interrupt line. */
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141 | #define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - Interrupt pin. */
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142 | #define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit ?? */
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143 | #define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 8-bit? ?? - bridge */
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144 | #define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit ?? */
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145 | /** @} */
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146 |
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147 |
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148 | /**
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149 | * Callback function for reading from the PCI configuration space.
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150 | *
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151 | * @returns The register value.
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152 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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153 | * @param Address The configuration space register address. [0..255]
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154 | * @param cb The register size. [1,2,4]
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155 | */
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156 | typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
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157 | /** Pointer to a FNPCICONFIGREAD() function. */
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158 | typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
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159 | /** Pointer to a PFNPCICONFIGREAD. */
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160 | typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
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161 |
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162 | /**
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163 | * Callback function for writing to the PCI configuration space.
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164 | *
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165 | * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
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166 | * @param Address The configuration space register address. [0..255]
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167 | * @param u32Value The value that's being written. The number of bits actually used from
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168 | * this value is determined by the cb parameter.
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169 | * @param cb The register size. [1,2,4]
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170 | */
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171 | typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
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172 | /** Pointer to a FNPCICONFIGWRITE() function. */
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173 | typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
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174 | /** Pointer to a PFNPCICONFIGWRITE. */
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175 | typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
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176 |
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177 | /** Fixed I/O region number for ROM. */
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178 | #define PCI_ROM_SLOT 6
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179 | /** Max number of I/O regions. */
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180 | #define PCI_NUM_REGIONS 7
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181 |
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182 | /*
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183 | * Hack to include the PCIDEVICEINT structure at the right place
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184 | * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
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185 | */
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186 | #ifdef PCI_INCLUDE_PRIVATE
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187 | # include "PCIInternal.h"
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188 | #endif
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189 |
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190 | /**
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191 | * PCI Device structure.
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192 | */
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193 | typedef struct PCIDevice
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194 | {
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195 | /** PCI config space. */
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196 | uint8_t config[256];
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197 |
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198 | /** Internal data. */
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199 | union
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200 | {
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201 | #ifdef __PCIDEVICEINT_DECLARED__
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202 | PCIDEVICEINT s;
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203 | #endif
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204 | char padding[256];
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205 | } Int;
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206 |
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207 | /** Read only data.
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208 | * @{
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209 | */
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210 | /** PCI device number on the pci bus. */
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211 | int32_t devfn;
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212 | uint32_t Alignment0; /**< Alignment. */
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213 | /** Device name. */
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214 | R3PTRTYPE(const char *) name;
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215 | /** Pointer to the device instance which registered the device. */
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216 | PPDMDEVINSR3 pDevIns;
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217 | /** @} */
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218 | } PCIDEVICE;
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219 |
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220 |
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221 | /**
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222 | * Sets the vendor id config register.
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223 | * @param pPciDev The PCI device.
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224 | * @param u16VendorId The vendor id.
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225 | */
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226 | DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
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227 | {
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228 | u16VendorId = RT_H2LE_U16(u16VendorId);
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229 | pPciDev->config[VBOX_PCI_VENDOR_ID] = u16VendorId & 0xff;
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230 | pPciDev->config[VBOX_PCI_VENDOR_ID + 1] = u16VendorId >> 8;
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231 | }
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232 |
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233 | /**
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234 | * Gets the vendor id config register.
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235 | * @returns the vendor id.
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236 | * @param pPciDev The PCI device.
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237 | */
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238 | DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
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239 | {
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240 | return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_VENDOR_ID], pPciDev->config[VBOX_PCI_VENDOR_ID + 1]));
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241 | }
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242 |
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243 |
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244 | /**
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245 | * Sets the device id config register.
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246 | * @param pPciDev The PCI device.
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247 | * @param u16DeviceId The device id.
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248 | */
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249 | DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
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250 | {
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251 | u16DeviceId = RT_H2LE_U16(u16DeviceId);
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252 | pPciDev->config[VBOX_PCI_DEVICE_ID] = u16DeviceId & 0xff;
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253 | pPciDev->config[VBOX_PCI_DEVICE_ID + 1] = u16DeviceId >> 8;
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254 | }
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255 |
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256 | /**
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257 | * Gets the device id config register.
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258 | * @returns the device id.
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259 | * @param pPciDev The PCI device.
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260 | */
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261 | DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
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262 | {
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263 | return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_DEVICE_ID], pPciDev->config[VBOX_PCI_DEVICE_ID + 1]));
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264 | }
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265 |
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266 |
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267 | /**
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268 | * Sets the command config register.
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269 | *
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270 | * @param pPciDev The PCI device.
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271 | * @param u16Command The command register value.
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272 | */
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273 | DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
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274 | {
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275 | u16Command = RT_H2LE_U16(u16Command);
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276 | pPciDev->config[VBOX_PCI_COMMAND] = u16Command & 0xff;
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277 | pPciDev->config[VBOX_PCI_COMMAND + 1] = u16Command >> 8;
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278 | }
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279 |
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280 |
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281 | /**
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282 | * Gets the command config register.
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283 | * @returns The command register value.
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284 | * @param pPciDev The PCI device.
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285 | */
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286 | DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
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287 | {
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288 | return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_COMMAND], pPciDev->config[VBOX_PCI_COMMAND + 1]));
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289 | }
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290 |
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291 |
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292 | /**
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293 | * Sets the status config register.
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294 | *
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295 | * @param pPciDev The PCI device.
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296 | * @param u16Status The status register value.
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297 | */
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298 | DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
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299 | {
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300 | u16Status = RT_H2LE_U16(u16Status);
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301 | pPciDev->config[VBOX_PCI_STATUS] = u16Status & 0xff;
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302 | pPciDev->config[VBOX_PCI_STATUS + 1] = u16Status >> 8;
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303 | }
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304 |
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305 |
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306 | /**
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307 | * Sets the revision id config register.
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308 | *
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309 | * @param pPciDev The PCI device.
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310 | * @param u8RevisionId The revision id.
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311 | */
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312 | DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
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313 | {
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314 | pPciDev->config[VBOX_PCI_REVISION_ID] = u8RevisionId;
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315 | }
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316 |
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317 |
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318 | /**
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319 | * Sets the register level programming class config register.
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320 | *
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321 | * @param pPciDev The PCI device.
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322 | * @param u8ClassProg The new value.
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323 | */
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324 | DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
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325 | {
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326 | pPciDev->config[VBOX_PCI_CLASS_PROG] = u8ClassProg;
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327 | }
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328 |
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329 |
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330 | /**
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331 | * Sets the sub-class (aka device class) config register.
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332 | *
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333 | * @param pPciDev The PCI device.
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334 | * @param u8SubClass The sub-class.
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335 | */
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336 | DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
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337 | {
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338 | pPciDev->config[VBOX_PCI_CLASS_SUB] = u8SubClass;
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339 | }
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340 |
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341 |
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342 | /**
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343 | * Sets the base class config register.
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344 | *
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345 | * @param pPciDev The PCI device.
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346 | * @param u8BaseClass The base class.
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347 | */
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348 | DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
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349 | {
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350 | pPciDev->config[VBOX_PCI_CLASS_BASE] = u8BaseClass;
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351 | }
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352 |
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353 |
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354 | /**
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355 | * Sets the header type config register.
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356 | *
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357 | * @param pPciDev The PCI device.
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358 | * @param u8HdrType The header type.
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359 | */
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360 | DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
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361 | {
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362 | pPciDev->config[VBOX_PCI_HEADER_TYPE] = u8HdrType;
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363 | }
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364 |
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365 |
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366 | /**
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367 | * Sets a base address config register.
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368 | *
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369 | * @param pPciDev The PCI device.
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370 | * @param fIOSpace Whether it's I/O (true) or memory (false) space.
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371 | * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
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372 | * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
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373 | * @param u32Addr The address value.
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374 | */
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375 | DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
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376 | {
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377 | if (fIOSpace)
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378 | {
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379 | Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
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380 | u32Addr |= RT_BIT_32(0);
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381 | }
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382 | else
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383 | {
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384 | Assert(!(u32Addr & 0xf));
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385 | if (fPrefetchable)
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386 | u32Addr |= RT_BIT_32(3);
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387 | if (f64Bit)
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388 | u32Addr |= 0x2 << 1;
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389 | }
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390 | switch (iReg)
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391 | {
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392 | case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
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393 | case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
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394 | case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
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395 | case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
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396 | case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
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397 | case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
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398 | default: AssertFailedReturnVoid();
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399 | }
|
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400 |
|
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401 | u32Addr = RT_H2LE_U32(u32Addr);
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402 | pPciDev->config[iReg] = u32Addr & 0xff;
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403 | pPciDev->config[iReg + 1] = (u32Addr >> 8) & 0xff;
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404 | pPciDev->config[iReg + 2] = (u32Addr >> 16) & 0xff;
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405 | pPciDev->config[iReg + 3] = (u32Addr >> 24) & 0xff;
|
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406 | }
|
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407 |
|
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408 |
|
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409 | /**
|
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410 | * Sets the sub-system vendor id config register.
|
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411 | *
|
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412 | * @param pPciDev The PCI device.
|
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413 | * @param u16SubSysVendorId The sub-system vendor id.
|
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414 | */
|
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415 | DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
|
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416 | {
|
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417 | u16SubSysVendorId = RT_H2LE_U16(u16SubSysVendorId);
|
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418 | pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID] = u16SubSysVendorId & 0xff;
|
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419 | pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1] = u16SubSysVendorId >> 8;
|
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420 | }
|
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421 |
|
---|
422 | /**
|
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423 | * Gets the sub-system vendor id config register.
|
---|
424 | * @returns the sub-system vendor id.
|
---|
425 | * @param pPciDev The PCI device.
|
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426 | */
|
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427 | DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
|
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428 | {
|
---|
429 | return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1]));
|
---|
430 | }
|
---|
431 |
|
---|
432 |
|
---|
433 | /**
|
---|
434 | * Sets the sub-system id config register.
|
---|
435 | *
|
---|
436 | * @param pPciDev The PCI device.
|
---|
437 | * @param u16SubSystemId The sub-system id.
|
---|
438 | */
|
---|
439 | DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
|
---|
440 | {
|
---|
441 | u16SubSystemId = RT_H2LE_U16(u16SubSystemId);
|
---|
442 | pPciDev->config[VBOX_PCI_SUBSYSTEM_ID] = u16SubSystemId & 0xff;
|
---|
443 | pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1] = u16SubSystemId >> 8;
|
---|
444 | }
|
---|
445 |
|
---|
446 | /**
|
---|
447 | * Gets the sub-system id config register.
|
---|
448 | * @returns the sub-system id.
|
---|
449 | * @param pPciDev The PCI device.
|
---|
450 | */
|
---|
451 | DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
|
---|
452 | {
|
---|
453 | return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1]));
|
---|
454 | }
|
---|
455 |
|
---|
456 |
|
---|
457 | /**
|
---|
458 | * Sets the interrupt line config register.
|
---|
459 | *
|
---|
460 | * @param pPciDev The PCI device.
|
---|
461 | * @param u8Line The interrupt line.
|
---|
462 | */
|
---|
463 | DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
|
---|
464 | {
|
---|
465 | pPciDev->config[VBOX_PCI_INTERRUPT_LINE] = u8Line;
|
---|
466 | }
|
---|
467 |
|
---|
468 |
|
---|
469 | /**
|
---|
470 | * Sets the interrupt pin config register.
|
---|
471 | *
|
---|
472 | * @param pPciDev The PCI device.
|
---|
473 | * @param u8Pin The interrupt pin.
|
---|
474 | */
|
---|
475 | DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
|
---|
476 | {
|
---|
477 | pPciDev->config[VBOX_PCI_INTERRUPT_PIN] = u8Pin;
|
---|
478 | }
|
---|
479 |
|
---|
480 |
|
---|
481 | /** @} */
|
---|
482 |
|
---|
483 | #endif
|
---|