pci.h@ 31911

Last change on this file since 31911 was 30898, checked in by vboxsync, 14 years ago
PCI: PCIDev{Get\|Set}CapabilityList have been added.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 17.5 KB

Line
1	/** @file
2	* PCI - The PCI Controller And Devices. (DEV)
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_pci_h
27	#define ___VBox_pci_h
28
29	#include <VBox/cdefs.h>
30	#include <VBox/types.h>
31	#include <iprt/assert.h>
32
33	/** @defgroup grp_pci PCI - The PCI Controller.
34	* @{
35	*/
36
37	/** Pointer to a PCI device. */
38	typedef struct PCIDevice *PPCIDEVICE;
39
40
41	/**
42	* PCI configuration word 4 (command) and word 6 (status).
43	*/
44	typedef enum PCICONFIGCOMMAND
45	{
46	/** Supports/uses memory accesses. */
47	PCI_COMMAND_IOACCESS = 0x0001,
48	PCI_COMMAND_MEMACCESS = 0x0002,
49	PCI_COMMAND_BUSMASTER = 0x0004
50	} PCICONFIGCOMMAND;
51
52
53	/**
54	* PCI Address space specification.
55	* This is used when registering a I/O region.
56	*/
57	/** Note: There are all sorts of dirty dependencies on the values in the
58	* pci device. Be careful when changing this.
59	* @todo we should introduce 32 & 64 bits physical address types
60	*/
61	typedef enum PCIADDRESSSPACE
62	{
63	/** Memory. */
64	PCI_ADDRESS_SPACE_MEM = 0x00,
65	/** I/O space. */
66	PCI_ADDRESS_SPACE_IO = 0x01,
67	/** Prefetch memory. */
68	PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
69	} PCIADDRESSSPACE;
70
71
72	/**
73	* Callback function for mapping an PCI I/O region.
74	*
75	* @return VBox status code.
76	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
77	* @param iRegion The region number.
78	* @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
79	* is an I/O port, otherwise it's a physical address.
80	*
81	* NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
82	* that the device deregister access handlers for it and update its internal
83	* state to reflect this.
84	*
85	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
86	*
87	* @remarks The address is NOT relative to pci_mem_base.
88	*/
89	typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /unsigned/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType);
90	/** Pointer to a FNPCIIOREGIONMAP() function. */
91	typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
92
93
94	/** @name PCI Configuration Space Registers
95	* @{ */
96	#define VBOX_PCI_VENDOR_ID 0x00 /*< 16-bit RO /
97	#define VBOX_PCI_DEVICE_ID 0x02 /*< 16-bit RO /
98	#define VBOX_PCI_COMMAND 0x04 /*< 16-bit RW /
99	#define VBOX_PCI_STATUS 0x06 /*< 16-bit RW /
100	#define VBOX_PCI_REVISION_ID 0x08 /*< 8-bit RO /
101	#define VBOX_PCI_CLASS_PROG 0x09 /*< 8-bit RO - - register-level programming class code (device specific). /
102	#define VBOX_PCI_CLASS_SUB 0x0a /*< 8-bit RO - - sub-class code. /
103	#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
104	#define VBOX_PCI_CLASS_BASE 0x0b /*< 8-bit RO - - base class code. /
105	#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /*< 8-bit ?? /
106	#define VBOX_PCI_LATENCY_TIMER 0x0d /*< 8-bit ?? /
107	#define VBOX_PCI_HEADER_TYPE 0x0e /*< 8-bit ?? /
108	#define VBOX_PCI_BIST 0x0f /*< 8-bit ?? /
109	#define VBOX_PCI_BASE_ADDRESS_0 0x10 /*< 32-bit RW /
110	#define VBOX_PCI_BASE_ADDRESS_1 0x14 /*< 32-bit RW /
111	#define VBOX_PCI_BASE_ADDRESS_2 0x18 /*< 32-bit RW /
112	#define VBOX_PCI_PRIMARY_BUS 0x18 /*< 8-bit ?? - bridge - primary bus number. /
113	#define VBOX_PCI_SECONDARY_BUS 0x19 /*< 8-bit ?? - bridge - secondary bus number. /
114	#define VBOX_PCI_SUBORDINATE_BUS 0x1a /*< 8-bit ?? - bridge - highest subordinate bus number. (behind the bridge) /
115	#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /*< 8-bit ?? - bridge - secondary latency timer. /
116	#define VBOX_PCI_BASE_ADDRESS_3 0x1c /*< 32-bit RW /
117	#define VBOX_PCI_IO_BASE 0x1c /*< 8-bit ?? - bridge - I/O range base. /
118	#define VBOX_PCI_IO_LIMIT 0x1d /*< 8-bit ?? - bridge - I/O range limit. /
119	#define VBOX_PCI_SEC_STATUS 0x1e /*< 16-bit ?? - bridge - secondary status register. /
120	#define VBOX_PCI_BASE_ADDRESS_4 0x20 /*< 32-bit RW /
121	#define VBOX_PCI_MEMORY_BASE 0x20 /*< 16-bit ?? - bridge - memory range base. /
122	#define VBOX_PCI_MEMORY_LIMIT 0x22 /*< 16-bit ?? - bridge - memory range limit. /
123	#define VBOX_PCI_BASE_ADDRESS_5 0x24 /*< 32-bit RW /
124	#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /*< 16-bit ?? - bridge - Prefetchable memory range base. /
125	#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /*< 16-bit ?? - bridge - Prefetchable memory range limit. /
126	#define VBOX_PCI_CARDBUS_CIS 0x28 /*< 32-bit ?? /
127	#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /*< 32-bit ?? - bridge - Prefetchable memory range high base./
128	#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /*< 32-bit ?? - bridge - Prefetchable memory range high limit. /
129	#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /*< 16-bit ?? /
130	#define VBOX_PCI_SUBSYSTEM_ID 0x2e /*< 16-bit ?? /
131	#define VBOX_PCI_ROM_ADDRESS 0x30 /*< 32-bit ?? /
132	#define VBOX_PCI_IO_BASE_UPPER16 0x30 /*< 16-bit ?? - bridge - memory range high base. /
133	#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /*< 16-bit ?? - bridge - memory range high limit. /
134	#define VBOX_PCI_CAPABILITY_LIST 0x34 /*< 8-bit? ?? /
135	#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /*< 32-bit ?? - bridge /
136	#define VBOX_PCI_INTERRUPT_LINE 0x3c /*< 8-bit RW - Interrupt line. /
137	#define VBOX_PCI_INTERRUPT_PIN 0x3d /*< 8-bit RO - Interrupt pin. /
138	#define VBOX_PCI_MIN_GNT 0x3e /*< 8-bit ?? /
139	#define VBOX_PCI_BRIDGE_CONTROL 0x3e /*< 8-bit? ?? - bridge /
140	#define VBOX_PCI_MAX_LAT 0x3f /*< 8-bit ?? /
141	/** @} */
142
143
144	/**
145	* Callback function for reading from the PCI configuration space.
146	*
147	* @returns The register value.
148	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
149	* @param Address The configuration space register address. [0..255]
150	* @param cb The register size. [1,2,4]
151	*/
152	typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
153	/** Pointer to a FNPCICONFIGREAD() function. */
154	typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
155	/** Pointer to a PFNPCICONFIGREAD. */
156	typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
157
158	/**
159	* Callback function for writing to the PCI configuration space.
160	*
161	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
162	* @param Address The configuration space register address. [0..255]
163	* @param u32Value The value that's being written. The number of bits actually used from
164	* this value is determined by the cb parameter.
165	* @param cb The register size. [1,2,4]
166	*/
167	typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
168	/** Pointer to a FNPCICONFIGWRITE() function. */
169	typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
170	/** Pointer to a PFNPCICONFIGWRITE. */
171	typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
172
173	/** Fixed I/O region number for ROM. */
174	#define PCI_ROM_SLOT 6
175	/** Max number of I/O regions. */
176	#define PCI_NUM_REGIONS 7
177
178	/*
179	* Hack to include the PCIDEVICEINT structure at the right place
180	* to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
181	*/
182	#ifdef PCI_INCLUDE_PRIVATE
183	# include "PCIInternal.h"
184	#endif
185
186	/**
187	* PCI Device structure.
188	*/
189	typedef struct PCIDevice
190	{
191	/** PCI config space. */
192	uint8_t config[256];
193
194	/** Internal data. */
195	union
196	{
197	#ifdef PCIDEVICEINT_DECLARED
198	PCIDEVICEINT s;
199	#endif
200	char padding[256];
201	} Int;
202
203	/** Read only data.
204	* @{
205	*/
206	/** PCI device number on the pci bus. */
207	int32_t devfn;
208	uint32_t Alignment0; /*< Alignment. /
209	/** Device name. */
210	R3PTRTYPE(const char *) name;
211	/** Pointer to the device instance which registered the device. */
212	PPDMDEVINSR3 pDevIns;
213	/** @} */
214	} PCIDEVICE;
215
216
217	/**
218	* Sets the vendor id config register.
219	* @param pPciDev The PCI device.
220	* @param u16VendorId The vendor id.
221	*/
222	DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
223	{
224	u16VendorId = RT_H2LE_U16(u16VendorId);
225	pPciDev->config[VBOX_PCI_VENDOR_ID] = u16VendorId & 0xff;
226	pPciDev->config[VBOX_PCI_VENDOR_ID + 1] = u16VendorId >> 8;
227	}
228
229	/**
230	* Gets the vendor id config register.
231	* @returns the vendor id.
232	* @param pPciDev The PCI device.
233	*/
234	DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
235	{
236	return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_VENDOR_ID], pPciDev->config[VBOX_PCI_VENDOR_ID + 1]));
237	}
238
239
240	/**
241	* Sets the device id config register.
242	* @param pPciDev The PCI device.
243	* @param u16DeviceId The device id.
244	*/
245	DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
246	{
247	u16DeviceId = RT_H2LE_U16(u16DeviceId);
248	pPciDev->config[VBOX_PCI_DEVICE_ID] = u16DeviceId & 0xff;
249	pPciDev->config[VBOX_PCI_DEVICE_ID + 1] = u16DeviceId >> 8;
250	}
251
252	/**
253	* Gets the device id config register.
254	* @returns the device id.
255	* @param pPciDev The PCI device.
256	*/
257	DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
258	{
259	return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_DEVICE_ID], pPciDev->config[VBOX_PCI_DEVICE_ID + 1]));
260	}
261
262
263	/**
264	* Sets the command config register.
265	*
266	* @param pPciDev The PCI device.
267	* @param u16Command The command register value.
268	*/
269	DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
270	{
271	u16Command = RT_H2LE_U16(u16Command);
272	pPciDev->config[VBOX_PCI_COMMAND] = u16Command & 0xff;
273	pPciDev->config[VBOX_PCI_COMMAND + 1] = u16Command >> 8;
274	}
275
276
277	/**
278	* Gets the command config register.
279	* @returns The command register value.
280	* @param pPciDev The PCI device.
281	*/
282	DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
283	{
284	return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_COMMAND], pPciDev->config[VBOX_PCI_COMMAND + 1]));
285	}
286
287
288	/**
289	* Sets the status config register.
290	*
291	* @param pPciDev The PCI device.
292	* @param u16Status The status register value.
293	*/
294	DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
295	{
296	u16Status = RT_H2LE_U16(u16Status);
297	pPciDev->config[VBOX_PCI_STATUS] = u16Status & 0xff;
298	pPciDev->config[VBOX_PCI_STATUS + 1] = u16Status >> 8;
299	}
300
301
302	/**
303	* Sets the revision id config register.
304	*
305	* @param pPciDev The PCI device.
306	* @param u8RevisionId The revision id.
307	*/
308	DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
309	{
310	pPciDev->config[VBOX_PCI_REVISION_ID] = u8RevisionId;
311	}
312
313
314	/**
315	* Sets the register level programming class config register.
316	*
317	* @param pPciDev The PCI device.
318	* @param u8ClassProg The new value.
319	*/
320	DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
321	{
322	pPciDev->config[VBOX_PCI_CLASS_PROG] = u8ClassProg;
323	}
324
325
326	/**
327	* Sets the sub-class (aka device class) config register.
328	*
329	* @param pPciDev The PCI device.
330	* @param u8SubClass The sub-class.
331	*/
332	DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
333	{
334	pPciDev->config[VBOX_PCI_CLASS_SUB] = u8SubClass;
335	}
336
337
338	/**
339	* Sets the base class config register.
340	*
341	* @param pPciDev The PCI device.
342	* @param u8BaseClass The base class.
343	*/
344	DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
345	{
346	pPciDev->config[VBOX_PCI_CLASS_BASE] = u8BaseClass;
347	}
348
349
350	/**
351	* Sets the header type config register.
352	*
353	* @param pPciDev The PCI device.
354	* @param u8HdrType The header type.
355	*/
356	DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
357	{
358	pPciDev->config[VBOX_PCI_HEADER_TYPE] = u8HdrType;
359	}
360
361
362	/**
363	* Sets a base address config register.
364	*
365	* @param pPciDev The PCI device.
366	* @param fIOSpace Whether it's I/O (true) or memory (false) space.
367	* @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
368	* @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
369	* @param u32Addr The address value.
370	*/
371	DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit, uint32_t u32Addr)
372	{
373	if (fIOSpace)
374	{
375	Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
376	u32Addr \|= RT_BIT_32(0);
377	}
378	else
379	{
380	Assert(!(u32Addr & 0xf));
381	if (fPrefetchable)
382	u32Addr \|= RT_BIT_32(3);
383	if (f64Bit)
384	u32Addr \|= 0x2 << 1;
385	}
386	switch (iReg)
387	{
388	case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
389	case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
390	case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
391	case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
392	case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
393	case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
394	default: AssertFailedReturnVoid();
395	}
396
397	u32Addr = RT_H2LE_U32(u32Addr);
398	pPciDev->config[iReg] = u32Addr & 0xff;
399	pPciDev->config[iReg + 1] = (u32Addr >> 8) & 0xff;
400	pPciDev->config[iReg + 2] = (u32Addr >> 16) & 0xff;
401	pPciDev->config[iReg + 3] = (u32Addr >> 24) & 0xff;
402	}
403
404
405	/**
406	* Sets the sub-system vendor id config register.
407	*
408	* @param pPciDev The PCI device.
409	* @param u16SubSysVendorId The sub-system vendor id.
410	*/
411	DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
412	{
413	u16SubSysVendorId = RT_H2LE_U16(u16SubSysVendorId);
414	pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID] = u16SubSysVendorId & 0xff;
415	pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1] = u16SubSysVendorId >> 8;
416	}
417
418	/**
419	* Gets the sub-system vendor id config register.
420	* @returns the sub-system vendor id.
421	* @param pPciDev The PCI device.
422	*/
423	DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
424	{
425	return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_VENDOR_ID + 1]));
426	}
427
428
429	/**
430	* Sets the sub-system id config register.
431	*
432	* @param pPciDev The PCI device.
433	* @param u16SubSystemId The sub-system id.
434	*/
435	DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
436	{
437	u16SubSystemId = RT_H2LE_U16(u16SubSystemId);
438	pPciDev->config[VBOX_PCI_SUBSYSTEM_ID] = u16SubSystemId & 0xff;
439	pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1] = u16SubSystemId >> 8;
440	}
441
442	/**
443	* Gets the sub-system id config register.
444	* @returns the sub-system id.
445	* @param pPciDev The PCI device.
446	*/
447	DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
448	{
449	return RT_LE2H_U16(RT_MAKE_U16(pPciDev->config[VBOX_PCI_SUBSYSTEM_ID], pPciDev->config[VBOX_PCI_SUBSYSTEM_ID + 1]));
450	}
451
452	/**
453	* Sets offset to capability list.
454	*
455	* @param pPciDev The PCI device.
456	* @param u8Offset The offset to capability list.
457	*/
458	DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
459	{
460	pPciDev->config[VBOX_PCI_CAPABILITY_LIST] = u8Offset;
461	}
462
463	/**
464	* Returns offset to capability list.
465	*
466	* @returns offset to capability list.
467	* @param pPciDev The PCI device.
468	*/
469	DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
470	{
471	return pPciDev->config[VBOX_PCI_CAPABILITY_LIST];
472	}
473
474	/**
475	* Sets the interrupt line config register.
476	*
477	* @param pPciDev The PCI device.
478	* @param u8Line The interrupt line.
479	*/
480	DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
481	{
482	pPciDev->config[VBOX_PCI_INTERRUPT_LINE] = u8Line;
483	}
484
485	/**
486	* Gets the interrupt line config register.
487	*
488	* @returns The interrupt line.
489	* @param pPciDev The PCI device.
490	*/
491	DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
492	{
493	return pPciDev->config[VBOX_PCI_INTERRUPT_LINE];
494	}
495
496	/**
497	* Sets the interrupt pin config register.
498	*
499	* @param pPciDev The PCI device.
500	* @param u8Pin The interrupt pin.
501	*/
502	DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
503	{
504	pPciDev->config[VBOX_PCI_INTERRUPT_PIN] = u8Pin;
505	}
506
507
508	/**
509	* Gets the interrupt pin config register.
510	*
511	* @returns The interrupt pin.
512	* @param pPciDev The PCI device.
513	*/
514	DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
515	{
516	return pPciDev->config[VBOX_PCI_INTERRUPT_PIN];
517	}
518
519
520	/** @} */
521
522	#endif
523

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