VirtualBox

source: vbox/trunk/include/VBox/pci.h@ 63807

Last change on this file since 63807 was 63690, checked in by vboxsync, 8 years ago

PCI,Devices: Changed range size in FNPCIIOREGIONMAP from uint32_t to RTGCPHYS.
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File size: 47.2 KB
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1/** @file
2 * PCI - The PCI Controller And Devices. (DEV)
3 */
4
5/*
6 * Copyright (C) 2006-2016 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_pci_h
27#define ___VBox_pci_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <iprt/assert.h>
32
33/** @defgroup grp_pci PCI - The PCI Controller.
34 * @ingroup grp_devdrv
35 * @{
36 */
37
38/** Pointer to a PCI device. */
39typedef struct PCIDevice *PPCIDEVICE;
40
41
42/**
43 * PCI configuration word 4 (command) and word 6 (status).
44 */
45typedef enum PCICONFIGCOMMAND
46{
47 /** Supports/uses memory accesses. */
48 PCI_COMMAND_IOACCESS = 0x0001,
49 PCI_COMMAND_MEMACCESS = 0x0002,
50 PCI_COMMAND_BUSMASTER = 0x0004
51} PCICONFIGCOMMAND;
52
53
54/**
55 * PCI Address space specification.
56 * This is used when registering a I/O region.
57 */
58/**
59 * Defined by the PCI specification.
60 */
61typedef enum PCIADDRESSSPACE
62{
63 /** Memory. */
64 PCI_ADDRESS_SPACE_MEM = 0x00,
65 /** I/O space. */
66 PCI_ADDRESS_SPACE_IO = 0x01,
67 /** 32-bit BAR. */
68 PCI_ADDRESS_SPACE_BAR32 = 0x00,
69 /** 64-bit BAR. */
70 PCI_ADDRESS_SPACE_BAR64 = 0x04,
71 /** Prefetch memory. */
72 PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
73} PCIADDRESSSPACE;
74
75
76/**
77 * Callback function for mapping an PCI I/O region.
78 *
79 * @return VBox status code.
80 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
81 * @param iRegion The region number.
82 * @param GCPhysAddress Physical address of the region. If enmType is PCI_ADDRESS_SPACE_IO, this
83 * is an I/O port, otherwise it's a physical address.
84 *
85 * NIL_RTGCPHYS indicates that a MMIO2 mapping is about to be unmapped and
86 * that the device deregister access handlers for it and update its internal
87 * state to reflect this.
88 *
89 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
90 *
91 * @remarks Called with the PDM lock held. The device lock is NOT take because
92 * that is very likely be a lock order violation.
93 */
94typedef DECLCALLBACK(int) FNPCIIOREGIONMAP(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress,
95 RTGCPHYS cb, PCIADDRESSSPACE enmType);
96/** Pointer to a FNPCIIOREGIONMAP() function. */
97typedef FNPCIIOREGIONMAP *PFNPCIIOREGIONMAP;
98
99
100/** @name PCI Configuration Space Registers
101 * @{ */
102/* Commented out values common for different header types */
103/* Common part of the header */
104#define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
105#define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
106#define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
107#define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
108#define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
109#define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
110#define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
111#define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
112#define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
113#define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
114#define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
115#define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
116#define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
117#define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
118#define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
119#define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
120
121/* Type 0 header, device */
122#define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
123#define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
124#define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
125#define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
126#define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
127#define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
128#define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
129#define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
130#define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
131#define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
132/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
133#define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
134#define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
135#define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
136#define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
137/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
138/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
139#define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
140#define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
141
142/* Type 1 header, PCI-to-PCI bridge */
143/* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
144/* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
145#define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
146#define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
147#define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
148#define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
149#define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
150#define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
151#define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
152#define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
153#define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
154#define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
155#define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
156#define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
157#define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
158#define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
159#define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
160/* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
161/* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
162/* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
163/* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
164#define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
165#define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
166
167/* Type 2 header, PCI-to-CardBus bridge */
168#define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
169#define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
170#define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
171#define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
172#define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
173#define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
174/* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
175/* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
176#define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
177#define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
178#define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
179#define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
180#define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
181#define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
182#define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
183#define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
184/* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
185/* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
186/* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
187/** @} */
188
189
190/* Possible values in status bitmask */
191#define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
192#define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
193#define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
194#define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
195#define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
196#define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
197#define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
198#define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
199#define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
200#define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
201#define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
202#define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
203#define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
204#define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
205
206
207/* Command bitmask */
208#define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
209#define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
210#define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
211#define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
212#define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
213#define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
214#define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
215#define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
216#define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
217#define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
218#define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
219
220
221/* Capability list values (capability offset 0) */
222/* Next value pointer in offset 1, or 0 if none */
223#define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
224#define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
225#define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
226#define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
227#define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
228#define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
229#define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
230#define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
231#define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
232#define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
233#define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
234#define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
235#define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
236#define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
237#define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
238#define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
239#define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
240#define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
241#define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
242
243/* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
244#define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
245#define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
246#define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
247#define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
248#define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
249#define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
250#define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
251#define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
252#define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
253#define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
254#define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
255#define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
256#define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
257#define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
258
259
260/* MSI flags, aka Message Control (2 bytes, capability offset 2) */
261#define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
262#define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
263#define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
264/* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
265 someone very similar to log_2().
266 000 1
267 001 2
268 010 4
269 011 8
270 100 16
271 101 32
272 110 Reserved
273 111 Reserved */
274#define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
275#define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
276
277/* MSI-X flags (2 bytes, capability offset 2) */
278#define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
279#define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
280
281/* Power management flags (2 bytes, capability offset 2) */
282#define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
283#define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
284#define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
285#define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
286#define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
287#define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
288#define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
289#define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
290#define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
291#define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
292#define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
293#define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
294#define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
295#define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
296
297/* Power management control flags (2 bytes, capability offset 4) */
298#define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
299#define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
300#define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
301#define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
302#define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
303#define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
304
305/* PCI-X config flags (2 bytes, capability offset 2) */
306#define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
307#define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
308#define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
309#define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
310#define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
311#define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
312#define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
313#define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
314
315/* PCI-X config flags (4 bytes, capability offset 4) */
316#define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
317#define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
318#define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
319#define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
320#define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
321#define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
322#define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
323#define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
324#define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
325#define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
326#define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
327#define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
328#define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
329
330/* PCI Express config flags (2 bytes, capability offset 2) */
331#define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
332#define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
333#define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
334#define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
335#define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
336#define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
337#define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
338#define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
339#define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
340#define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
341#define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
342#define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
343#define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
344
345/* PCI Express device capabilities (4 bytes, capability offset 4) */
346#define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
347#define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
348#define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
349#define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
350#define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
351#define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
352#define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
353#define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
354#define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
355#define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
356#define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
357#define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
358
359/* PCI Express device control (2 bytes, capability offset 8) */
360#define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
361#define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
362#define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
363#define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
364#define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
365#define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
366#define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
367#define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
368#define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
369#define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
370#define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
371#define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
372#define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
373
374/* PCI Express device status (2 bytes, capability offset 10) */
375#define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
376#define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
377#define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
378#define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
379#define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
380#define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
381
382/* PCI Express link capabilities (4 bytes, capability offset 12) */
383#define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
384#define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
385#define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
386#define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
387#define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
388#define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
389#define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
390#define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
391#define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
392#define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
393
394/* PCI Express link control (2 bytes, capability offset 16) */
395#define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
396#define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
397#define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
398#define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
399#define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
400#define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
401#define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
402#define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
403#define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
404#define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
405
406/* PCI Express link status (2 bytes, capability offset 18) */
407#define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
408#define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
409#define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
410#define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
411#define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
412#define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
413#define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
414#define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
415
416/* PCI Express slot capabilities (4 bytes, capability offset 20) */
417#define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
418#define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
419#define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
420#define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
421#define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
422#define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
423#define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
424#define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
425#define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
426#define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
427#define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
428#define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
429
430/* PCI Express slot control (2 bytes, capability offset 24) */
431#define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
432#define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
433#define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
434#define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
435#define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
436#define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
437#define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
438#define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
439#define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
440#define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
441#define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
442
443/* PCI Express slot status (2 bytes, capability offset 26) */
444#define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
445#define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
446#define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
447#define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
448#define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
449#define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
450#define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
451#define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
452#define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
453
454/* PCI Express root control (2 bytes, capability offset 28) */
455#define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
456#define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
457#define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
458#define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
459#define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
460
461/* PCI Express root capabilities (2 bytes, capability offset 30) */
462#define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
463
464/* PCI Express root status (4 bytes, capability offset 32) */
465#define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
466#define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
467#define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
468
469
470/**
471 * Callback function for reading from the PCI configuration space.
472 *
473 * @returns The register value.
474 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
475 * @param Address The configuration space register address. [0..4096]
476 * @param cb The register size. [1,2,4]
477 *
478 * @remarks Called with the PDM lock held. The device lock is NOT take because
479 * that is very likely be a lock order violation.
480 */
481typedef DECLCALLBACK(uint32_t) FNPCICONFIGREAD(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb);
482/** Pointer to a FNPCICONFIGREAD() function. */
483typedef FNPCICONFIGREAD *PFNPCICONFIGREAD;
484/** Pointer to a PFNPCICONFIGREAD. */
485typedef PFNPCICONFIGREAD *PPFNPCICONFIGREAD;
486
487/**
488 * Callback function for writing to the PCI configuration space.
489 *
490 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
491 * @param Address The configuration space register address. [0..4096]
492 * @param u32Value The value that's being written. The number of bits actually used from
493 * this value is determined by the cb parameter.
494 * @param cb The register size. [1,2,4]
495 *
496 * @remarks Called with the PDM lock held. The device lock is NOT take because
497 * that is very likely be a lock order violation.
498 */
499typedef DECLCALLBACK(void) FNPCICONFIGWRITE(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb);
500/** Pointer to a FNPCICONFIGWRITE() function. */
501typedef FNPCICONFIGWRITE *PFNPCICONFIGWRITE;
502/** Pointer to a PFNPCICONFIGWRITE. */
503typedef PFNPCICONFIGWRITE *PPFNPCICONFIGWRITE;
504
505/** Fixed I/O region number for ROM. */
506#define PCI_ROM_SLOT 6
507#define VBOX_PCI_ROM_SLOT 6
508/** Max number of I/O regions. */
509#define PCI_NUM_REGIONS 7
510#define VBOX_PCI_NUM_REGIONS 7
511
512/*
513 * Hack to include the PCIDEVICEINT structure at the right place
514 * to avoid duplications of FNPCIIOREGIONMAP and PCI_NUM_REGIONS.
515 */
516#ifdef PCI_INCLUDE_PRIVATE
517# include "PCIInternal.h"
518#endif
519
520/**
521 * PCI Device structure.
522 */
523typedef struct PCIDevice
524{
525 /** PCI config space. */
526 uint8_t config[256];
527
528 /** Internal data. */
529 union
530 {
531#ifdef PCIDEVICEINT_DECLARED
532 PCIDEVICEINT s;
533#endif
534 char padding[328];
535 } Int;
536
537 /** Read only data.
538 * @{
539 */
540 /** PCI device number on the pci bus. */
541 int32_t devfn;
542 uint32_t Alignment0; /**< Alignment. */
543 /** Device name. */
544 R3PTRTYPE(const char *) name;
545 /** Pointer to the device instance which registered the device. */
546 PPDMDEVINSR3 pDevIns;
547 /** @} */
548} PCIDEVICE;
549
550/** @todo handle extended space access. */
551
552DECLINLINE(void) PCIDevSetByte(PPCIDEVICE pPciDev, uint32_t offReg, uint8_t u8Value)
553{
554 pPciDev->config[offReg] = u8Value;
555}
556
557DECLINLINE(uint8_t) PCIDevGetByte(PPCIDEVICE pPciDev, uint32_t offReg)
558{
559 return pPciDev->config[offReg];
560}
561
562DECLINLINE(void) PCIDevSetWord(PPCIDEVICE pPciDev, uint32_t offReg, uint16_t u16Value)
563{
564 *(uint16_t*)&pPciDev->config[offReg] = RT_H2LE_U16(u16Value);
565}
566
567DECLINLINE(uint16_t) PCIDevGetWord(PPCIDEVICE pPciDev, uint32_t offReg)
568{
569 uint16_t u16Value = *(uint16_t*)&pPciDev->config[offReg];
570 return RT_H2LE_U16(u16Value);
571}
572
573DECLINLINE(void) PCIDevSetDWord(PPCIDEVICE pPciDev, uint32_t offReg, uint32_t u32Value)
574{
575 *(uint32_t*)&pPciDev->config[offReg] = RT_H2LE_U32(u32Value);
576}
577
578DECLINLINE(uint32_t) PCIDevGetDWord(PPCIDEVICE pPciDev, uint32_t offReg)
579{
580 uint32_t u32Value = *(uint32_t*)&pPciDev->config[offReg];
581 return RT_H2LE_U32(u32Value);
582}
583
584DECLINLINE(void) PCIDevSetQWord(PPCIDEVICE pPciDev, uint32_t offReg, uint64_t u64Value)
585{
586 *(uint64_t*)&pPciDev->config[offReg] = RT_H2LE_U64(u64Value);
587}
588
589DECLINLINE(uint64_t) PCIDevGetQWord(PPCIDEVICE pPciDev, uint32_t offReg)
590{
591 uint64_t u64Value = *(uint64_t*)&pPciDev->config[offReg];
592 return RT_H2LE_U64(u64Value);
593}
594
595/**
596 * Sets the vendor id config register.
597 * @param pPciDev The PCI device.
598 * @param u16VendorId The vendor id.
599 */
600DECLINLINE(void) PCIDevSetVendorId(PPCIDEVICE pPciDev, uint16_t u16VendorId)
601{
602 PCIDevSetWord(pPciDev, VBOX_PCI_VENDOR_ID, u16VendorId);
603}
604
605/**
606 * Gets the vendor id config register.
607 * @returns the vendor id.
608 * @param pPciDev The PCI device.
609 */
610DECLINLINE(uint16_t) PCIDevGetVendorId(PPCIDEVICE pPciDev)
611{
612 return PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID);
613}
614
615
616/**
617 * Sets the device id config register.
618 * @param pPciDev The PCI device.
619 * @param u16DeviceId The device id.
620 */
621DECLINLINE(void) PCIDevSetDeviceId(PPCIDEVICE pPciDev, uint16_t u16DeviceId)
622{
623 PCIDevSetWord(pPciDev, VBOX_PCI_DEVICE_ID, u16DeviceId);
624}
625
626/**
627 * Gets the device id config register.
628 * @returns the device id.
629 * @param pPciDev The PCI device.
630 */
631DECLINLINE(uint16_t) PCIDevGetDeviceId(PPCIDEVICE pPciDev)
632{
633 return PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID);
634}
635
636/**
637 * Sets the command config register.
638 *
639 * @param pPciDev The PCI device.
640 * @param u16Command The command register value.
641 */
642DECLINLINE(void) PCIDevSetCommand(PPCIDEVICE pPciDev, uint16_t u16Command)
643{
644 PCIDevSetWord(pPciDev, VBOX_PCI_COMMAND, u16Command);
645}
646
647
648/**
649 * Gets the command config register.
650 * @returns The command register value.
651 * @param pPciDev The PCI device.
652 */
653DECLINLINE(uint16_t) PCIDevGetCommand(PPCIDEVICE pPciDev)
654{
655 return PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
656}
657
658/**
659 * Checks if the given PCI device is a bus master.
660 * @returns true if the device is a bus master, false if not.
661 * @param pPciDev The PCI device.
662 */
663DECLINLINE(bool) PCIDevIsBusmaster(PPCIDEVICE pPciDev)
664{
665 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_MASTER) != 0;
666}
667
668/**
669 * Checks if INTx interrupts disabled in the command config register.
670 * @returns true if disabled.
671 * @param pPciDev The PCI device.
672 */
673DECLINLINE(bool) PCIDevIsIntxDisabled(PPCIDEVICE pPciDev)
674{
675 return (PCIDevGetCommand(pPciDev) & VBOX_PCI_COMMAND_INTX_DISABLE) != 0;
676}
677
678/**
679 * Gets the status config register.
680 *
681 * @returns status config register.
682 * @param pPciDev The PCI device.
683 */
684DECLINLINE(uint16_t) PCIDevGetStatus(PPCIDEVICE pPciDev)
685{
686 return PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
687}
688
689/**
690 * Sets the status config register.
691 *
692 * @param pPciDev The PCI device.
693 * @param u16Status The status register value.
694 */
695DECLINLINE(void) PCIDevSetStatus(PPCIDEVICE pPciDev, uint16_t u16Status)
696{
697 PCIDevSetWord(pPciDev, VBOX_PCI_STATUS, u16Status);
698}
699
700
701/**
702 * Sets the revision id config register.
703 *
704 * @param pPciDev The PCI device.
705 * @param u8RevisionId The revision id.
706 */
707DECLINLINE(void) PCIDevSetRevisionId(PPCIDEVICE pPciDev, uint8_t u8RevisionId)
708{
709 PCIDevSetByte(pPciDev, VBOX_PCI_REVISION_ID, u8RevisionId);
710}
711
712
713/**
714 * Sets the register level programming class config register.
715 *
716 * @param pPciDev The PCI device.
717 * @param u8ClassProg The new value.
718 */
719DECLINLINE(void) PCIDevSetClassProg(PPCIDEVICE pPciDev, uint8_t u8ClassProg)
720{
721 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_PROG, u8ClassProg);
722}
723
724
725/**
726 * Sets the sub-class (aka device class) config register.
727 *
728 * @param pPciDev The PCI device.
729 * @param u8SubClass The sub-class.
730 */
731DECLINLINE(void) PCIDevSetClassSub(PPCIDEVICE pPciDev, uint8_t u8SubClass)
732{
733 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_SUB, u8SubClass);
734}
735
736
737/**
738 * Sets the base class config register.
739 *
740 * @param pPciDev The PCI device.
741 * @param u8BaseClass The base class.
742 */
743DECLINLINE(void) PCIDevSetClassBase(PPCIDEVICE pPciDev, uint8_t u8BaseClass)
744{
745 PCIDevSetByte(pPciDev, VBOX_PCI_CLASS_BASE, u8BaseClass);
746}
747
748/**
749 * Sets the header type config register.
750 *
751 * @param pPciDev The PCI device.
752 * @param u8HdrType The header type.
753 */
754DECLINLINE(void) PCIDevSetHeaderType(PPCIDEVICE pPciDev, uint8_t u8HdrType)
755{
756 PCIDevSetByte(pPciDev, VBOX_PCI_HEADER_TYPE, u8HdrType);
757}
758
759/**
760 * Gets the header type config register.
761 *
762 * @param pPciDev The PCI device.
763 * @returns u8HdrType The header type.
764 */
765DECLINLINE(uint8_t) PCIDevGetHeaderType(PPCIDEVICE pPciDev)
766{
767 return PCIDevGetByte(pPciDev, VBOX_PCI_HEADER_TYPE);
768}
769
770/**
771 * Sets the BIST (built-in self-test) config register.
772 *
773 * @param pPciDev The PCI device.
774 * @param u8Bist The BIST value.
775 */
776DECLINLINE(void) PCIDevSetBIST(PPCIDEVICE pPciDev, uint8_t u8Bist)
777{
778 PCIDevSetByte(pPciDev, VBOX_PCI_BIST, u8Bist);
779}
780
781/**
782 * Gets the BIST (built-in self-test) config register.
783 *
784 * @param pPciDev The PCI device.
785 * @returns u8Bist The BIST.
786 */
787DECLINLINE(uint8_t) PCIDevGetBIST(PPCIDEVICE pPciDev)
788{
789 return PCIDevGetByte(pPciDev, VBOX_PCI_BIST);
790}
791
792
793/**
794 * Sets a base address config register.
795 *
796 * @param pPciDev The PCI device.
797 * @param iReg Base address register number (0..5).
798 * @param fIOSpace Whether it's I/O (true) or memory (false) space.
799 * @param fPrefetchable Whether the memory is prefetachable. Must be false if fIOSpace == true.
800 * @param f64Bit Whether the memory can be mapped anywhere in the 64-bit address space. Otherwise restrict to 32-bit.
801 * @param u32Addr The address value.
802 */
803DECLINLINE(void) PCIDevSetBaseAddress(PPCIDEVICE pPciDev, uint8_t iReg, bool fIOSpace, bool fPrefetchable, bool f64Bit,
804 uint32_t u32Addr)
805{
806 if (fIOSpace)
807 {
808 Assert(!(u32Addr & 0x3)); Assert(!fPrefetchable); Assert(!f64Bit);
809 u32Addr |= RT_BIT_32(0);
810 }
811 else
812 {
813 Assert(!(u32Addr & 0xf));
814 if (fPrefetchable)
815 u32Addr |= RT_BIT_32(3);
816 if (f64Bit)
817 u32Addr |= 0x2 << 1;
818 }
819 switch (iReg)
820 {
821 case 0: iReg = VBOX_PCI_BASE_ADDRESS_0; break;
822 case 1: iReg = VBOX_PCI_BASE_ADDRESS_1; break;
823 case 2: iReg = VBOX_PCI_BASE_ADDRESS_2; break;
824 case 3: iReg = VBOX_PCI_BASE_ADDRESS_3; break;
825 case 4: iReg = VBOX_PCI_BASE_ADDRESS_4; break;
826 case 5: iReg = VBOX_PCI_BASE_ADDRESS_5; break;
827 default: AssertFailedReturnVoid();
828 }
829
830 PCIDevSetDWord(pPciDev, iReg, u32Addr);
831}
832
833/**
834 * Please document me. I don't seem to be getting as much as calculating
835 * the address of some PCI region.
836 */
837DECLINLINE(uint32_t) PCIDevGetRegionReg(uint32_t iRegion)
838{
839 return iRegion == VBOX_PCI_ROM_SLOT
840 ? VBOX_PCI_ROM_ADDRESS : (VBOX_PCI_BASE_ADDRESS_0 + iRegion * 4);
841}
842
843/**
844 * Sets the sub-system vendor id config register.
845 *
846 * @param pPciDev The PCI device.
847 * @param u16SubSysVendorId The sub-system vendor id.
848 */
849DECLINLINE(void) PCIDevSetSubSystemVendorId(PPCIDEVICE pPciDev, uint16_t u16SubSysVendorId)
850{
851 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, u16SubSysVendorId);
852}
853
854/**
855 * Gets the sub-system vendor id config register.
856 * @returns the sub-system vendor id.
857 * @param pPciDev The PCI device.
858 */
859DECLINLINE(uint16_t) PCIDevGetSubSystemVendorId(PPCIDEVICE pPciDev)
860{
861 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID);
862}
863
864
865/**
866 * Sets the sub-system id config register.
867 *
868 * @param pPciDev The PCI device.
869 * @param u16SubSystemId The sub-system id.
870 */
871DECLINLINE(void) PCIDevSetSubSystemId(PPCIDEVICE pPciDev, uint16_t u16SubSystemId)
872{
873 PCIDevSetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID, u16SubSystemId);
874}
875
876/**
877 * Gets the sub-system id config register.
878 * @returns the sub-system id.
879 * @param pPciDev The PCI device.
880 */
881DECLINLINE(uint16_t) PCIDevGetSubSystemId(PPCIDEVICE pPciDev)
882{
883 return PCIDevGetWord(pPciDev, VBOX_PCI_SUBSYSTEM_ID);
884}
885
886/**
887 * Sets offset to capability list.
888 *
889 * @param pPciDev The PCI device.
890 * @param u8Offset The offset to capability list.
891 */
892DECLINLINE(void) PCIDevSetCapabilityList(PPCIDEVICE pPciDev, uint8_t u8Offset)
893{
894 PCIDevSetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST, u8Offset);
895}
896
897/**
898 * Returns offset to capability list.
899 *
900 * @returns offset to capability list.
901 * @param pPciDev The PCI device.
902 */
903DECLINLINE(uint8_t) PCIDevGetCapabilityList(PPCIDEVICE pPciDev)
904{
905 return PCIDevGetByte(pPciDev, VBOX_PCI_CAPABILITY_LIST);
906}
907
908/**
909 * Sets the interrupt line config register.
910 *
911 * @param pPciDev The PCI device.
912 * @param u8Line The interrupt line.
913 */
914DECLINLINE(void) PCIDevSetInterruptLine(PPCIDEVICE pPciDev, uint8_t u8Line)
915{
916 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE, u8Line);
917}
918
919/**
920 * Gets the interrupt line config register.
921 *
922 * @returns The interrupt line.
923 * @param pPciDev The PCI device.
924 */
925DECLINLINE(uint8_t) PCIDevGetInterruptLine(PPCIDEVICE pPciDev)
926{
927 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE);
928}
929
930/**
931 * Sets the interrupt pin config register.
932 *
933 * @param pPciDev The PCI device.
934 * @param u8Pin The interrupt pin.
935 */
936DECLINLINE(void) PCIDevSetInterruptPin(PPCIDEVICE pPciDev, uint8_t u8Pin)
937{
938 PCIDevSetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN, u8Pin);
939}
940
941/**
942 * Gets the interrupt pin config register.
943 *
944 * @returns The interrupt pin.
945 * @param pPciDev The PCI device.
946 */
947DECLINLINE(uint8_t) PCIDevGetInterruptPin(PPCIDEVICE pPciDev)
948{
949 return PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
950}
951
952#ifdef PCIDEVICEINT_DECLARED
953DECLINLINE(void) pciDevSetRequestedDevfunc(PPCIDEVICE pDev)
954{
955 pDev->Int.s.fFlags |= PCIDEV_FLAG_REQUESTED_DEVFUNC;
956}
957
958DECLINLINE(void) pciDevClearRequestedDevfunc(PPCIDEVICE pDev)
959{
960 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_REQUESTED_DEVFUNC;
961}
962
963DECLINLINE(bool) pciDevIsRequestedDevfunc(PPCIDEVICE pDev)
964{
965 return (pDev->Int.s.fFlags & PCIDEV_FLAG_REQUESTED_DEVFUNC) != 0;
966}
967
968DECLINLINE(void) pciDevSetPci2PciBridge(PPCIDEVICE pDev)
969{
970 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_TO_PCI_BRIDGE;
971}
972
973DECLINLINE(bool) pciDevIsPci2PciBridge(PPCIDEVICE pDev)
974{
975 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_TO_PCI_BRIDGE) != 0;
976}
977
978DECLINLINE(void) pciDevSetPciExpress(PPCIDEVICE pDev)
979{
980 pDev->Int.s.fFlags |= PCIDEV_FLAG_PCI_EXPRESS_DEVICE;
981}
982
983DECLINLINE(bool) pciDevIsPciExpress(PPCIDEVICE pDev)
984{
985 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PCI_EXPRESS_DEVICE) != 0;
986}
987
988DECLINLINE(void) pciDevSetMsiCapable(PPCIDEVICE pDev)
989{
990 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI_CAPABLE;
991}
992
993DECLINLINE(void) pciDevClearMsiCapable(PPCIDEVICE pDev)
994{
995 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI_CAPABLE;
996}
997
998DECLINLINE(bool) pciDevIsMsiCapable(PPCIDEVICE pDev)
999{
1000 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI_CAPABLE) != 0;
1001}
1002
1003DECLINLINE(void) pciDevSetMsi64Capable(PPCIDEVICE pDev)
1004{
1005 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSI64_CAPABLE;
1006}
1007
1008DECLINLINE(void) pciDevClearMsi64Capable(PPCIDEVICE pDev)
1009{
1010 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSI64_CAPABLE;
1011}
1012
1013DECLINLINE(bool) pciDevIsMsi64Capable(PPCIDEVICE pDev)
1014{
1015 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSI64_CAPABLE) != 0;
1016}
1017
1018DECLINLINE(void) pciDevSetMsixCapable(PPCIDEVICE pDev)
1019{
1020 pDev->Int.s.fFlags |= PCIDEV_FLAG_MSIX_CAPABLE;
1021}
1022
1023DECLINLINE(void) pciDevClearMsixCapable(PPCIDEVICE pDev)
1024{
1025 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_MSIX_CAPABLE;
1026}
1027
1028DECLINLINE(bool) pciDevIsMsixCapable(PPCIDEVICE pDev)
1029{
1030 return (pDev->Int.s.fFlags & PCIDEV_FLAG_MSIX_CAPABLE) != 0;
1031}
1032
1033DECLINLINE(void) pciDevSetPassthrough(PPCIDEVICE pDev)
1034{
1035 pDev->Int.s.fFlags |= PCIDEV_FLAG_PASSTHROUGH;
1036}
1037
1038DECLINLINE(void) pciDevClearPassthrough(PPCIDEVICE pDev)
1039{
1040 pDev->Int.s.fFlags &= ~PCIDEV_FLAG_PASSTHROUGH;
1041}
1042
1043DECLINLINE(bool) pciDevIsPassthrough(PPCIDEVICE pDev)
1044{
1045 return (pDev->Int.s.fFlags & PCIDEV_FLAG_PASSTHROUGH) != 0;
1046}
1047
1048#endif /* PCIDEVICEINT_DECLARED */
1049
1050#if defined(__cplusplus) && defined(IN_RING3)
1051/* For RTStrPrintf(). */
1052#include <iprt/string.h>
1053
1054/**
1055 * Class representing PCI address. PCI device consist of
1056 * bus, device and function numbers. Generally device PCI
1057 * address could be changed during runtime, but only by
1058 * an OS PCI driver.
1059 *
1060 * @remarks C++ classes (structs included) are not generally accepted in
1061 * VMM devices or drivers. An exception may be granted for this class
1062 * if it's contained to ring-3 and that this is a one time exception
1063 * which sets no precedent.
1064 */
1065struct PCIBusAddress
1066{
1067 /** @todo: think if we'll need domain, which is higher
1068 * word of the address. */
1069 int miBus;
1070 int miDevice;
1071 int miFn;
1072
1073 PCIBusAddress()
1074 {
1075 clear();
1076 }
1077
1078 PCIBusAddress(int iBus, int iDevice, int iFn)
1079 {
1080 init(iBus, iDevice, iFn);
1081 }
1082
1083 PCIBusAddress(int32_t iAddr)
1084 {
1085 clear();
1086 fromLong(iAddr);
1087 }
1088
1089 PCIBusAddress& clear()
1090 {
1091 miBus = miDevice = miFn = -1;
1092 return *this;
1093 }
1094
1095 void init(int iBus, int iDevice, int iFn)
1096 {
1097 miBus = iBus;
1098 miDevice = iDevice;
1099 miFn = iFn;
1100 }
1101
1102 void init(const PCIBusAddress &a)
1103 {
1104 miBus = a.miBus;
1105 miDevice = a.miDevice;
1106 miFn = a.miFn;
1107 }
1108
1109 bool operator<(const PCIBusAddress &a) const
1110 {
1111 if (miBus < a.miBus)
1112 return true;
1113
1114 if (miBus > a.miBus)
1115 return false;
1116
1117 if (miDevice < a.miDevice)
1118 return true;
1119
1120 if (miDevice > a.miDevice)
1121 return false;
1122
1123 if (miFn < a.miFn)
1124 return true;
1125
1126 if (miFn > a.miFn)
1127 return false;
1128
1129 return false;
1130 }
1131
1132 bool operator==(const PCIBusAddress &a) const
1133 {
1134 return (miBus == a.miBus)
1135 && (miDevice == a.miDevice)
1136 && (miFn == a.miFn);
1137 }
1138
1139 bool operator!=(const PCIBusAddress &a) const
1140 {
1141 return (miBus != a.miBus)
1142 || (miDevice != a.miDevice)
1143 || (miFn != a.miFn);
1144 }
1145
1146 bool valid() const
1147 {
1148 return (miBus != -1)
1149 && (miDevice != -1)
1150 && (miFn != -1);
1151 }
1152
1153 int32_t asLong() const
1154 {
1155 Assert(valid());
1156 return (miBus << 8) | (miDevice << 3) | miFn;
1157 }
1158
1159 PCIBusAddress& fromLong(int32_t value)
1160 {
1161 miBus = (value >> 8) & 0xff;
1162 miDevice = (value & 0xff) >> 3;
1163 miFn = (value & 7);
1164 return *this;
1165 }
1166
1167 /** Create string representation of this PCI address. */
1168 bool format(char* szBuf, int32_t cBufSize)
1169 {
1170 if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
1171 return false;
1172
1173 if (valid())
1174 RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
1175 else
1176 RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
1177
1178 return true;
1179 }
1180
1181 static const size_t cMaxAddrSize = 10;
1182};
1183#endif /* __cplusplus */
1184
1185/** @} */
1186
1187#endif
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