| 1 | /** @file
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| 2 | * PCI - The PCI Controller And Devices Constants. (DEV)
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2017 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_pci_h
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| 27 | #define ___VBox_pci_h
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| 28 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 29 | # pragma once
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| 30 | #endif
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| 31 |
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| 32 | #include <VBox/cdefs.h>
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| 33 | #include <VBox/types.h>
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| 34 | #include <iprt/assert.h>
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| 35 |
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| 36 | /** @defgroup grp_pci PCI - The PCI Controller.
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| 37 | * @ingroup grp_devdrv
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| 38 | * @{
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| 39 | */
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| 40 |
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| 41 |
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| 42 | /**
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| 43 | * PCI configuration word 4 (command) and word 6 (status).
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| 44 | */
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| 45 | typedef enum PCICONFIGCOMMAND
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| 46 | {
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| 47 | /** Supports/uses memory accesses. */
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| 48 | PCI_COMMAND_IOACCESS = 0x0001,
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| 49 | PCI_COMMAND_MEMACCESS = 0x0002,
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| 50 | PCI_COMMAND_BUSMASTER = 0x0004
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| 51 | } PCICONFIGCOMMAND;
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| 52 |
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| 53 |
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| 54 | /**
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| 55 | * PCI Address space specification.
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| 56 | * This is used when registering a I/O region.
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| 57 | */
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| 58 | /**
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| 59 | * Defined by the PCI specification.
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| 60 | */
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| 61 | typedef enum PCIADDRESSSPACE
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| 62 | {
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| 63 | /** Memory. */
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| 64 | PCI_ADDRESS_SPACE_MEM = 0x00,
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| 65 | /** I/O space. */
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| 66 | PCI_ADDRESS_SPACE_IO = 0x01,
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| 67 | /** 32-bit BAR. */
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| 68 | PCI_ADDRESS_SPACE_BAR32 = 0x00,
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| 69 | /** 64-bit BAR. */
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| 70 | PCI_ADDRESS_SPACE_BAR64 = 0x04,
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| 71 | /** Prefetch memory. */
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| 72 | PCI_ADDRESS_SPACE_MEM_PREFETCH = 0x08
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| 73 | } PCIADDRESSSPACE;
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| 74 |
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| 75 |
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| 76 |
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| 77 | /** @name PCI Configuration Space Registers
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| 78 | * @{ */
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| 79 | /* Commented out values common for different header types */
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| 80 | /* Common part of the header */
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| 81 | #define VBOX_PCI_VENDOR_ID 0x00 /**< 16-bit RO */
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| 82 | #define VBOX_PCI_DEVICE_ID 0x02 /**< 16-bit RO */
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| 83 | #define VBOX_PCI_COMMAND 0x04 /**< 16-bit RW, some bits RO */
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| 84 | #define VBOX_PCI_STATUS 0x06 /**< 16-bit RW, some bits RO */
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| 85 | #define VBOX_PCI_REVISION_ID 0x08 /**< 8-bit RO - - device revision */
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| 86 | #define VBOX_PCI_CLASS_PROG 0x09 /**< 8-bit RO - - register-level programming class code (device specific). */
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| 87 | #define VBOX_PCI_CLASS_SUB 0x0a /**< 8-bit RO - - sub-class code. */
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| 88 | #define VBOX_PCI_CLASS_DEVICE VBOX_PCI_CLASS_SUB
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| 89 | #define VBOX_PCI_CLASS_BASE 0x0b /**< 8-bit RO - - base class code. */
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| 90 | #define VBOX_PCI_CACHE_LINE_SIZE 0x0c /**< 8-bit RW - - system cache line size */
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| 91 | #define VBOX_PCI_LATENCY_TIMER 0x0d /**< 8-bit RW - - master latency timer, hardwired to 0 for PCIe */
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| 92 | #define VBOX_PCI_HEADER_TYPE 0x0e /**< 8-bit RO - - header type (0 - device, 1 - bridge, 2 - CardBus bridge) */
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| 93 | #define VBOX_PCI_BIST 0x0f /**< 8-bit RW - - built-in self test control */
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| 94 | #define VBOX_PCI_CAPABILITY_LIST 0x34 /**< 8-bit RO? - - linked list of new capabilities implemented by the device, 2 bottom bits reserved */
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| 95 | #define VBOX_PCI_INTERRUPT_LINE 0x3c /**< 8-bit RW - - interrupt line. */
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| 96 | #define VBOX_PCI_INTERRUPT_PIN 0x3d /**< 8-bit RO - - interrupt pin. */
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| 97 |
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| 98 | /* Type 0 header, device */
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| 99 | #define VBOX_PCI_BASE_ADDRESS_0 0x10 /**< 32-bit RW */
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| 100 | #define VBOX_PCI_BASE_ADDRESS_1 0x14 /**< 32-bit RW */
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| 101 | #define VBOX_PCI_BASE_ADDRESS_2 0x18 /**< 32-bit RW */
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| 102 | #define VBOX_PCI_BASE_ADDRESS_3 0x1c /**< 32-bit RW */
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| 103 | #define VBOX_PCI_BASE_ADDRESS_4 0x20 /**< 32-bit RW */
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| 104 | #define VBOX_PCI_BASE_ADDRESS_5 0x24 /**< 32-bit RW */
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| 105 | #define VBOX_PCI_CARDBUS_CIS 0x28 /**< 32-bit ?? */
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| 106 | #define VBOX_PCI_SUBSYSTEM_VENDOR_ID 0x2c /**< 16-bit RO */
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| 107 | #define VBOX_PCI_SUBSYSTEM_ID 0x2e /**< 16-bit RO */
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| 108 | #define VBOX_PCI_ROM_ADDRESS 0x30 /**< 32-bit ?? */
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| 109 | /* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
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| 110 | #define VBOX_PCI_RESERVED_35 0x35 /**< 8-bit ?? - - reserved */
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| 111 | #define VBOX_PCI_RESERVED_36 0x36 /**< 8-bit ?? - - reserved */
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| 112 | #define VBOX_PCI_RESERVED_37 0x37 /**< 8-bit ?? - - reserved */
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| 113 | #define VBOX_PCI_RESERVED_38 0x38 /**< 32-bit ?? - - reserved */
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| 114 | /* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
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| 115 | /* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
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| 116 | #define VBOX_PCI_MIN_GNT 0x3e /**< 8-bit RO - - burst period length (in 1/4 microsecond units) */
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| 117 | #define VBOX_PCI_MAX_LAT 0x3f /**< 8-bit RO - - how often the device needs access to the PCI bus (in 1/4 microsecond units) */
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| 118 |
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| 119 | /* Type 1 header, PCI-to-PCI bridge */
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| 120 | /* #define VBOX_PCI_BASE_ADDRESS_0 0x10 */ /**< 32-bit RW */
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| 121 | /* #define VBOX_PCI_BASE_ADDRESS_1 0x14 */ /**< 32-bit RW */
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| 122 | #define VBOX_PCI_PRIMARY_BUS 0x18 /**< 8-bit ?? - - primary bus number. */
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| 123 | #define VBOX_PCI_SECONDARY_BUS 0x19 /**< 8-bit ?? - - secondary bus number. */
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| 124 | #define VBOX_PCI_SUBORDINATE_BUS 0x1a /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
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| 125 | #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b /**< 8-bit ?? - - secondary latency timer. */
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| 126 | #define VBOX_PCI_IO_BASE 0x1c /**< 8-bit ?? - - I/O range base. */
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| 127 | #define VBOX_PCI_IO_LIMIT 0x1d /**< 8-bit ?? - - I/O range limit. */
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| 128 | #define VBOX_PCI_SEC_STATUS 0x1e /**< 16-bit ?? - - secondary status register. */
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| 129 | #define VBOX_PCI_MEMORY_BASE 0x20 /**< 16-bit ?? - - memory range base. */
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| 130 | #define VBOX_PCI_MEMORY_LIMIT 0x22 /**< 16-bit ?? - - memory range limit. */
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| 131 | #define VBOX_PCI_PREF_MEMORY_BASE 0x24 /**< 16-bit ?? - - prefetchable memory range base. */
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| 132 | #define VBOX_PCI_PREF_MEMORY_LIMIT 0x26 /**< 16-bit ?? - - prefetchable memory range limit. */
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| 133 | #define VBOX_PCI_PREF_BASE_UPPER32 0x28 /**< 32-bit ?? - - prefetchable memory range high base.*/
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| 134 | #define VBOX_PCI_PREF_LIMIT_UPPER32 0x2c /**< 32-bit ?? - - prefetchable memory range high limit. */
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| 135 | #define VBOX_PCI_IO_BASE_UPPER16 0x30 /**< 16-bit ?? - - memory range high base. */
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| 136 | #define VBOX_PCI_IO_LIMIT_UPPER16 0x32 /**< 16-bit ?? - - memory range high limit. */
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| 137 | /* #define VBOX_PCI_CAPABILITY_LIST 0x34 */ /**< 8-bit? ?? */
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| 138 | /* #define VBOX_PCI_RESERVED_35 0x35 */ /**< 8-bit ?? - - reserved */
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| 139 | /* #define VBOX_PCI_RESERVED_36 0x36 */ /**< 8-bit ?? - - reserved */
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| 140 | /* #define VBOX_PCI_RESERVED_37 0x37 */ /**< 8-bit ?? - - reserved */
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| 141 | #define VBOX_PCI_ROM_ADDRESS_BR 0x38 /**< 32-bit ?? - - expansion ROM base address */
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| 142 | #define VBOX_PCI_BRIDGE_CONTROL 0x3e /**< 16-bit? ?? - - bridge control */
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| 143 |
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| 144 | /* Type 2 header, PCI-to-CardBus bridge */
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| 145 | #define VBOX_PCI_CARDBUS_BASE_ADDRESS 0x10 /**< 32-bit RW - - CardBus Socket/ExCa base address */
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| 146 | #define VBOX_PCI_CARDBUS_CAPLIST 0x14 /**< 8-bit RO? - - offset of capabilities list */
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| 147 | #define VBOX_PCI_CARDBUS_RESERVED_15 0x15 /**< 8-bit ?? - - reserved */
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| 148 | #define VBOX_PCI_CARDBUS_SEC_STATUS 0x16 /**< 16-bit ?? - - secondary status */
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| 149 | #define VBOX_PCI_CARDBUS_PCIBUS_NUMBER 0x18 /**< 8-bit ?? - - PCI bus number */
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| 150 | #define VBOX_PCI_CARDBUS_CARDBUS_NUMBER 0x19 /**< 8-bit ?? - - CardBus bus number */
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| 151 | /* #define VBOX_PCI_SUBORDINATE_BUS 0x1a */ /**< 8-bit ?? - - highest subordinate bus number. (behind the bridge) */
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| 152 | /* #define VBOX_PCI_SEC_LATENCY_TIMER 0x1b */ /**< 8-bit ?? - - secondary latency timer. */
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| 153 | #define VBOX_PCI_CARDBUS_MEMORY_BASE0 0x1c /**< 32-bit RW - - memory base address 0 */
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| 154 | #define VBOX_PCI_CARDBUS_MEMORY_LIMIT0 0x20 /**< 32-bit RW - - memory limit 0 */
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| 155 | #define VBOX_PCI_CARDBUS_MEMORY_BASE1 0x24 /**< 32-bit RW - - memory base address 1 */
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| 156 | #define VBOX_PCI_CARDBUS_MEMORY_LIMIT1 0x28 /**< 32-bit RW - - memory limit 1 */
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| 157 | #define VBOX_PCI_CARDBUS_IO_BASE0 0x2c /**< 32-bit RW - - IO base address 0 */
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| 158 | #define VBOX_PCI_CARDBUS_IO_LIMIT0 0x30 /**< 32-bit RW - - IO limit 0 */
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| 159 | #define VBOX_PCI_CARDBUS_IO_BASE1 0x34 /**< 32-bit RW - - IO base address 1 */
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| 160 | #define VBOX_PCI_CARDBUS_IO_LIMIT1 0x38 /**< 32-bit RW - - IO limit 1 */
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| 161 | /* #define VBOX_PCI_INTERRUPT_LINE 0x3c */ /**< 8-bit RW - - interrupt line. */
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| 162 | /* #define VBOX_PCI_INTERRUPT_PIN 0x3d */ /**< 8-bit RO - - interrupt pin. */
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| 163 | /* #define VBOX_PCI_BRIDGE_CONTROL 0x3e */ /**< 16-bit? ?? - - bridge control */
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| 164 | /** @} */
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| 165 |
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| 166 |
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| 167 | /* Possible values in status bitmask */
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| 168 | #define VBOX_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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| 169 | #define VBOX_PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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| 170 | #define VBOX_PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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| 171 | #define VBOX_PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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| 172 | #define VBOX_PCI_STATUS_PARITY 0x100 /* Detected parity error */
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| 173 | #define VBOX_PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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| 174 | #define VBOX_PCI_STATUS_DEVSEL_FAST 0x000
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| 175 | #define VBOX_PCI_STATUS_DEVSEL_MEDIUM 0x200
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| 176 | #define VBOX_PCI_STATUS_DEVSEL_SLOW 0x400
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| 177 | #define VBOX_PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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| 178 | #define VBOX_PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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| 179 | #define VBOX_PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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| 180 | #define VBOX_PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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| 181 | #define VBOX_PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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| 182 |
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| 183 |
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| 184 | /* Command bitmask */
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| 185 | #define VBOX_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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| 186 | #define VBOX_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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| 187 | #define VBOX_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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| 188 | #define VBOX_PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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| 189 | #define VBOX_PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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| 190 | #define VBOX_PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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| 191 | #define VBOX_PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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| 192 | #define VBOX_PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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| 193 | #define VBOX_PCI_COMMAND_SERR 0x100 /* Enable SERR */
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| 194 | #define VBOX_PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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| 195 | #define VBOX_PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
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| 196 |
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| 197 |
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| 198 | /* Capability list values (capability offset 0) */
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| 199 | /* Next value pointer in offset 1, or 0 if none */
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| 200 | #define VBOX_PCI_CAP_ID_PM 0x01 /* Power Management */
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| 201 | #define VBOX_PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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| 202 | #define VBOX_PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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| 203 | #define VBOX_PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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| 204 | #define VBOX_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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| 205 | #define VBOX_PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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| 206 | #define VBOX_PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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| 207 | #define VBOX_PCI_CAP_ID_HT 0x08 /* HyperTransport */
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| 208 | #define VBOX_PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
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| 209 | #define VBOX_PCI_CAP_ID_DBG 0x0A /* Debug port */
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| 210 | #define VBOX_PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
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| 211 | #define VBOX_PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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| 212 | #define VBOX_PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
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| 213 | #define VBOX_PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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| 214 | #define VBOX_PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
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| 215 | #define VBOX_PCI_CAP_ID_EXP 0x10 /* PCI Express */
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| 216 | #define VBOX_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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| 217 | #define VBOX_PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
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| 218 | #define VBOX_PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
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| 219 |
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| 220 | /* Extended Capabilities (PCI-X 2.0 and Express), start at 0x100, next - bits [20..32] */
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| 221 | #define VBOX_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
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| 222 | #define VBOX_PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
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| 223 | #define VBOX_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
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| 224 | #define VBOX_PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
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| 225 | #define VBOX_PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
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| 226 | #define VBOX_PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
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| 227 | #define VBOX_PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
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| 228 | #define VBOX_PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
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| 229 | #define VBOX_PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
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| 230 | #define VBOX_PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
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| 231 | #define VBOX_PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
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| 232 | #define VBOX_PCI_EXT_CAP_ID_ARI 0x0e
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| 233 | #define VBOX_PCI_EXT_CAP_ID_ATS 0x0f
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| 234 | #define VBOX_PCI_EXT_CAP_ID_SRIOV 0x10
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| 235 |
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| 236 |
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| 237 | /* MSI flags, aka Message Control (2 bytes, capability offset 2) */
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| 238 | #define VBOX_PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
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| 239 | #define VBOX_PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
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| 240 | #define VBOX_PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking support */
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| 241 | /* Encoding for 3-bit patterns for message queue (per chapter 6.8.1 of PCI spec),
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| 242 | someone very similar to log_2().
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| 243 | 000 1
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| 244 | 001 2
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| 245 | 010 4
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| 246 | 011 8
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| 247 | 100 16
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| 248 | 101 32
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| 249 | 110 Reserved
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| 250 | 111 Reserved */
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| 251 | #define VBOX_PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured (i.e. vectors per device allocated) */
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| 252 | #define VBOX_PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available (i.e. vectors per device possible) */
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| 253 |
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| 254 | /* MSI-X flags (2 bytes, capability offset 2) */
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| 255 | #define VBOX_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
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| 256 | #define VBOX_PCI_MSIX_FLAGS_FUNCMASK 0x4000 /* Function mask */
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| 257 |
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| 258 | /* Power management flags (2 bytes, capability offset 2) */
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| 259 | #define VBOX_PCI_PM_CAP_VER_MASK 0x0007 /* Version mask */
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| 260 | #define VBOX_PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
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| 261 | #define VBOX_PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
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| 262 | #define VBOX_PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
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| 263 | #define VBOX_PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
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| 264 | #define VBOX_PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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| 265 | #define VBOX_PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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| 266 | #define VBOX_PCI_PM_CAP_PME 0x0800 /* PME pin supported */
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| 267 | #define VBOX_PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
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| 268 | #define VBOX_PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
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| 269 | #define VBOX_PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
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| 270 | #define VBOX_PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
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| 271 | #define VBOX_PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
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| 272 | #define VBOX_PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
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| 273 |
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| 274 | /* Power management control flags (2 bytes, capability offset 4) */
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| 275 | #define VBOX_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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| 276 | #define VBOX_PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
|
|---|
| 277 | #define VBOX_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
|
|---|
| 278 | #define VBOX_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
|---|
| 279 | #define VBOX_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
|---|
| 280 | #define VBOX_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
|---|
| 281 |
|
|---|
| 282 | /* PCI-X config flags (2 bytes, capability offset 2) */
|
|---|
| 283 | #define VBOX_PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
|
|---|
| 284 | #define VBOX_PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
|---|
| 285 | #define VBOX_PCI_X_CMD_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
|
|---|
| 286 | #define VBOX_PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
|
|---|
| 287 | #define VBOX_PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
|
|---|
| 288 | #define VBOX_PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
|
|---|
| 289 | #define VBOX_PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
|
|---|
| 290 | #define VBOX_PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
|
|---|
| 291 |
|
|---|
| 292 | /* PCI-X config flags (4 bytes, capability offset 4) */
|
|---|
| 293 | #define VBOX_PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
|
|---|
| 294 | #define VBOX_PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
|
|---|
| 295 | #define VBOX_PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
|
|---|
| 296 | #define VBOX_PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
|
|---|
| 297 | #define VBOX_PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
|
|---|
| 298 | #define VBOX_PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
|
|---|
| 299 | #define VBOX_PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity, 0 = simple device, 1 = bridge device */
|
|---|
| 300 | #define VBOX_PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count, 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
|
|---|
| 301 | #define VBOX_PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
|
|---|
| 302 | #define VBOX_PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
|
|---|
| 303 | #define VBOX_PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
|
|---|
| 304 | #define VBOX_PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
|
|---|
| 305 | #define VBOX_PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
|
|---|
| 306 |
|
|---|
| 307 | /* PCI Express config flags (2 bytes, capability offset 2) */
|
|---|
| 308 | #define VBOX_PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
|
|---|
| 309 | #define VBOX_PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
|---|
| 310 | #define VBOX_PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
|
|---|
| 311 | #define VBOX_PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
|
|---|
| 312 | #define VBOX_PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
|---|
| 313 | #define VBOX_PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
|---|
| 314 | #define VBOX_PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
|---|
| 315 | #define VBOX_PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
|---|
| 316 | #define VBOX_PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
|
|---|
| 317 | #define VBOX_PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
|
|---|
| 318 | #define VBOX_PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
|
|---|
| 319 | #define VBOX_PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
|---|
| 320 | #define VBOX_PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
|
|---|
| 321 |
|
|---|
| 322 | /* PCI Express device capabilities (4 bytes, capability offset 4) */
|
|---|
| 323 | #define VBOX_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
|
|---|
| 324 | #define VBOX_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
|
|---|
| 325 | #define VBOX_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
|
|---|
| 326 | #define VBOX_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
|
|---|
| 327 | #define VBOX_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
|
|---|
| 328 | #define VBOX_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
|
|---|
| 329 | #define VBOX_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
|
|---|
| 330 | #define VBOX_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
|
|---|
| 331 | #define VBOX_PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
|
|---|
| 332 | #define VBOX_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
|
|---|
| 333 | #define VBOX_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
|
|---|
| 334 | #define VBOX_PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
|
|---|
| 335 |
|
|---|
| 336 | /* PCI Express device control (2 bytes, capability offset 8) */
|
|---|
| 337 | #define VBOX_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
|
|---|
| 338 | #define VBOX_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
|
|---|
| 339 | #define VBOX_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
|
|---|
| 340 | #define VBOX_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
|
|---|
| 341 | #define VBOX_PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
|
|---|
| 342 | #define VBOX_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
|
|---|
| 343 | #define VBOX_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
|
|---|
| 344 | #define VBOX_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
|
|---|
| 345 | #define VBOX_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
|
|---|
| 346 | #define VBOX_PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
|
|---|
| 347 | #define VBOX_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
|
|---|
| 348 | #define VBOX_PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
|
|---|
| 349 | #define VBOX_PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
|
|---|
| 350 |
|
|---|
| 351 | /* PCI Express device status (2 bytes, capability offset 10) */
|
|---|
| 352 | #define VBOX_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
|
|---|
| 353 | #define VBOX_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
|
|---|
| 354 | #define VBOX_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
|
|---|
| 355 | #define VBOX_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
|
|---|
| 356 | #define VBOX_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
|
|---|
| 357 | #define VBOX_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
|
|---|
| 358 |
|
|---|
| 359 | /* PCI Express link capabilities (4 bytes, capability offset 12) */
|
|---|
| 360 | #define VBOX_PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
|
|---|
| 361 | #define VBOX_PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
|
|---|
| 362 | #define VBOX_PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
|
|---|
| 363 | #define VBOX_PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
|
|---|
| 364 | #define VBOX_PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
|
|---|
| 365 | #define VBOX_PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
|
|---|
| 366 | #define VBOX_PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
|
|---|
| 367 | #define VBOX_PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
|
|---|
| 368 | #define VBOX_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
|
|---|
| 369 | #define VBOX_PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
|
|---|
| 370 |
|
|---|
| 371 | /* PCI Express link control (2 bytes, capability offset 16) */
|
|---|
| 372 | #define VBOX_PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
|
|---|
| 373 | #define VBOX_PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
|
|---|
| 374 | #define VBOX_PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
|
|---|
| 375 | #define VBOX_PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
|
|---|
| 376 | #define VBOX_PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
|
|---|
| 377 | #define VBOX_PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
|
|---|
| 378 | #define VBOX_PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
|
|---|
| 379 | #define VBOX_PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
|
|---|
| 380 | #define VBOX_PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
|
|---|
| 381 | #define VBOX_PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
|
|---|
| 382 |
|
|---|
| 383 | /* PCI Express link status (2 bytes, capability offset 18) */
|
|---|
| 384 | #define VBOX_PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
|
|---|
| 385 | #define VBOX_PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
|
|---|
| 386 | #define VBOX_PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
|
|---|
| 387 | #define VBOX_PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
|
|---|
| 388 | #define VBOX_PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
|
|---|
| 389 | #define VBOX_PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
|
|---|
| 390 | #define VBOX_PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
|
|---|
| 391 | #define VBOX_PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
|
|---|
| 392 |
|
|---|
| 393 | /* PCI Express slot capabilities (4 bytes, capability offset 20) */
|
|---|
| 394 | #define VBOX_PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
|
|---|
| 395 | #define VBOX_PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
|
|---|
| 396 | #define VBOX_PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
|
|---|
| 397 | #define VBOX_PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
|
|---|
| 398 | #define VBOX_PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
|
|---|
| 399 | #define VBOX_PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
|
|---|
| 400 | #define VBOX_PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
|
|---|
| 401 | #define VBOX_PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
|
|---|
| 402 | #define VBOX_PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
|
|---|
| 403 | #define VBOX_PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
|
|---|
| 404 | #define VBOX_PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
|
|---|
| 405 | #define VBOX_PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
|---|
| 406 |
|
|---|
| 407 | /* PCI Express slot control (2 bytes, capability offset 24) */
|
|---|
| 408 | #define VBOX_PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
|
|---|
| 409 | #define VBOX_PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
|
|---|
| 410 | #define VBOX_PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
|
|---|
| 411 | #define VBOX_PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
|
|---|
| 412 | #define VBOX_PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
|
|---|
| 413 | #define VBOX_PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
|
|---|
| 414 | #define VBOX_PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
|
|---|
| 415 | #define VBOX_PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
|
|---|
| 416 | #define VBOX_PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
|
|---|
| 417 | #define VBOX_PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
|
|---|
| 418 | #define VBOX_PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
|
|---|
| 419 |
|
|---|
| 420 | /* PCI Express slot status (2 bytes, capability offset 26) */
|
|---|
| 421 | #define VBOX_PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
|
|---|
| 422 | #define VBOX_PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
|
|---|
| 423 | #define VBOX_PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
|
|---|
| 424 | #define VBOX_PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
|
|---|
| 425 | #define VBOX_PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
|
|---|
| 426 | #define VBOX_PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
|
|---|
| 427 | #define VBOX_PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
|
|---|
| 428 | #define VBOX_PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
|
|---|
| 429 | #define VBOX_PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
|
|---|
| 430 |
|
|---|
| 431 | /* PCI Express root control (2 bytes, capability offset 28) */
|
|---|
| 432 | #define VBOX_PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
|
|---|
| 433 | #define VBOX_PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
|
|---|
| 434 | #define VBOX_PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
|
|---|
| 435 | #define VBOX_PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
|
|---|
| 436 | #define VBOX_PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
|
|---|
| 437 |
|
|---|
| 438 | /* PCI Express root capabilities (2 bytes, capability offset 30) */
|
|---|
| 439 | #define VBOX_PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
|
|---|
| 440 |
|
|---|
| 441 | /* PCI Express root status (4 bytes, capability offset 32) */
|
|---|
| 442 | #define VBOX_PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
|
|---|
| 443 | #define VBOX_PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
|
|---|
| 444 | #define VBOX_PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
|
|---|
| 445 |
|
|---|
| 446 |
|
|---|
| 447 | /** Fixed I/O region number for ROM. */
|
|---|
| 448 | #define VBOX_PCI_ROM_SLOT 6
|
|---|
| 449 | /** Max number of I/O regions. */
|
|---|
| 450 | #define VBOX_PCI_NUM_REGIONS 7
|
|---|
| 451 |
|
|---|
| 452 | #define PCI_ROM_SLOT VBOX_PCI_ROM_SLOT /**< deprecated */
|
|---|
| 453 | #define PCI_NUM_REGIONS VBOX_PCI_NUM_REGIONS /**< deprecated */
|
|---|
| 454 |
|
|---|
| 455 | /** Number of functions per device. */
|
|---|
| 456 | #define VBOX_PCI_MAX_FUNCTIONS 8
|
|---|
| 457 | /** Number of devices per bus. */
|
|---|
| 458 | #define VBOX_PCI_MAX_DEVICES 32
|
|---|
| 459 | /** The device number shift count for a device+function number. */
|
|---|
| 460 | #define VBOX_PCI_DEVFN_DEV_SHIFT 3
|
|---|
| 461 | /** The device number shift count for a device+function number. */
|
|---|
| 462 | #define VBOX_PCI_DEVFN_FUN_MASK 0x7
|
|---|
| 463 | /** Make a device+function number. */
|
|---|
| 464 | #define VBOX_PCI_DEVFN_MAKE(a_uPciDevNo, a_uPciFunNo) (((a_uPciDevNo) << VBOX_PCI_DEVFN_DEV_SHIFT) | (a_uPciFunNo))
|
|---|
| 465 |
|
|---|
| 466 |
|
|---|
| 467 | #if defined(__cplusplus) && defined(IN_RING3)
|
|---|
| 468 | /* For RTStrPrintf(). */
|
|---|
| 469 | # include <iprt/string.h>
|
|---|
| 470 |
|
|---|
| 471 | /**
|
|---|
| 472 | * Class representing PCI address. PCI device consist of
|
|---|
| 473 | * bus, device and function numbers. Generally device PCI
|
|---|
| 474 | * address could be changed during runtime, but only by
|
|---|
| 475 | * an OS PCI driver.
|
|---|
| 476 | *
|
|---|
| 477 | * @remarks C++ classes (structs included) are not generally accepted in
|
|---|
| 478 | * VMM devices or drivers. An exception may be granted for this class
|
|---|
| 479 | * if it's contained to ring-3 and that this is a one time exception
|
|---|
| 480 | * which sets no precedent.
|
|---|
| 481 | */
|
|---|
| 482 | struct PCIBusAddress
|
|---|
| 483 | {
|
|---|
| 484 | /** @todo: think if we'll need domain, which is higher
|
|---|
| 485 | * word of the address. */
|
|---|
| 486 | int miBus;
|
|---|
| 487 | int miDevice;
|
|---|
| 488 | int miFn;
|
|---|
| 489 |
|
|---|
| 490 | PCIBusAddress()
|
|---|
| 491 | {
|
|---|
| 492 | clear();
|
|---|
| 493 | }
|
|---|
| 494 |
|
|---|
| 495 | PCIBusAddress(int iBus, int iDevice, int iFn)
|
|---|
| 496 | {
|
|---|
| 497 | init(iBus, iDevice, iFn);
|
|---|
| 498 | }
|
|---|
| 499 |
|
|---|
| 500 | PCIBusAddress(int32_t iAddr)
|
|---|
| 501 | {
|
|---|
| 502 | clear();
|
|---|
| 503 | fromLong(iAddr);
|
|---|
| 504 | }
|
|---|
| 505 |
|
|---|
| 506 | PCIBusAddress& clear()
|
|---|
| 507 | {
|
|---|
| 508 | miBus = miDevice = miFn = -1;
|
|---|
| 509 | return *this;
|
|---|
| 510 | }
|
|---|
| 511 |
|
|---|
| 512 | void init(int iBus, int iDevice, int iFn)
|
|---|
| 513 | {
|
|---|
| 514 | miBus = iBus;
|
|---|
| 515 | miDevice = iDevice;
|
|---|
| 516 | miFn = iFn;
|
|---|
| 517 | }
|
|---|
| 518 |
|
|---|
| 519 | void init(const PCIBusAddress &a)
|
|---|
| 520 | {
|
|---|
| 521 | miBus = a.miBus;
|
|---|
| 522 | miDevice = a.miDevice;
|
|---|
| 523 | miFn = a.miFn;
|
|---|
| 524 | }
|
|---|
| 525 |
|
|---|
| 526 | bool operator<(const PCIBusAddress &a) const
|
|---|
| 527 | {
|
|---|
| 528 | if (miBus < a.miBus)
|
|---|
| 529 | return true;
|
|---|
| 530 |
|
|---|
| 531 | if (miBus > a.miBus)
|
|---|
| 532 | return false;
|
|---|
| 533 |
|
|---|
| 534 | if (miDevice < a.miDevice)
|
|---|
| 535 | return true;
|
|---|
| 536 |
|
|---|
| 537 | if (miDevice > a.miDevice)
|
|---|
| 538 | return false;
|
|---|
| 539 |
|
|---|
| 540 | if (miFn < a.miFn)
|
|---|
| 541 | return true;
|
|---|
| 542 |
|
|---|
| 543 | if (miFn > a.miFn)
|
|---|
| 544 | return false;
|
|---|
| 545 |
|
|---|
| 546 | return false;
|
|---|
| 547 | }
|
|---|
| 548 |
|
|---|
| 549 | bool operator==(const PCIBusAddress &a) const
|
|---|
| 550 | {
|
|---|
| 551 | return (miBus == a.miBus)
|
|---|
| 552 | && (miDevice == a.miDevice)
|
|---|
| 553 | && (miFn == a.miFn);
|
|---|
| 554 | }
|
|---|
| 555 |
|
|---|
| 556 | bool operator!=(const PCIBusAddress &a) const
|
|---|
| 557 | {
|
|---|
| 558 | return (miBus != a.miBus)
|
|---|
| 559 | || (miDevice != a.miDevice)
|
|---|
| 560 | || (miFn != a.miFn);
|
|---|
| 561 | }
|
|---|
| 562 |
|
|---|
| 563 | bool valid() const
|
|---|
| 564 | {
|
|---|
| 565 | return (miBus != -1)
|
|---|
| 566 | && (miDevice != -1)
|
|---|
| 567 | && (miFn != -1);
|
|---|
| 568 | }
|
|---|
| 569 |
|
|---|
| 570 | int32_t asLong() const
|
|---|
| 571 | {
|
|---|
| 572 | Assert(valid());
|
|---|
| 573 | return (miBus << 8) | (miDevice << 3) | miFn;
|
|---|
| 574 | }
|
|---|
| 575 |
|
|---|
| 576 | PCIBusAddress& fromLong(int32_t value)
|
|---|
| 577 | {
|
|---|
| 578 | miBus = (value >> 8) & 0xff;
|
|---|
| 579 | miDevice = (value & 0xff) >> 3;
|
|---|
| 580 | miFn = (value & 7);
|
|---|
| 581 | return *this;
|
|---|
| 582 | }
|
|---|
| 583 |
|
|---|
| 584 | /** Create string representation of this PCI address. */
|
|---|
| 585 | bool format(char* szBuf, int32_t cBufSize)
|
|---|
| 586 | {
|
|---|
| 587 | if (cBufSize < (/* bus */ 2 + /* : */ 1 + /* device */ 2 + /* . */ 1 + /* function*/ 1 + /* \0 */1))
|
|---|
| 588 | return false;
|
|---|
| 589 |
|
|---|
| 590 | if (valid())
|
|---|
| 591 | RTStrPrintf(szBuf, cBufSize, "%02x:%02x.%01x", miBus, miDevice, miFn);
|
|---|
| 592 | else
|
|---|
| 593 | RTStrPrintf(szBuf, cBufSize, "%s", "<bad>");
|
|---|
| 594 |
|
|---|
| 595 | return true;
|
|---|
| 596 | }
|
|---|
| 597 |
|
|---|
| 598 | static const size_t cMaxAddrSize = 10;
|
|---|
| 599 | };
|
|---|
| 600 |
|
|---|
| 601 | #endif /* __cplusplus && IN_RING3 */
|
|---|
| 602 |
|
|---|
| 603 | /** @} */
|
|---|
| 604 |
|
|---|
| 605 | #endif
|
|---|
