VirtualBox

source: vbox/trunk/include/VBox/pgm.h@ 14711

Last change on this file since 14711 was 14346, checked in by vboxsync, 16 years ago

Implemented check for monitored page accesses, fixing TSS out of sync problem with VA in TLB. Enabled VA in TLB by default in new REM>
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 27.6 KB
Line 
1/** @file
2 * PGM - Page Monitor / Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_pgm_h
31#define ___VBox_pgm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/sup.h>
36#include <VBox/vmapi.h>
37#include <VBox/x86.h>
38#include <VBox/hwacc_vmx.h>
39
40__BEGIN_DECLS
41
42/** @defgroup grp_pgm The Page Monitor / Manager API
43 * @{
44 */
45
46/** Chunk size for dynamically allocated physical memory. */
47#define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
48/** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
49#define PGM_DYNAMIC_CHUNK_SHIFT 20
50/** Dynamic chunk offset mask. */
51#define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
52/** Dynamic chunk base mask. */
53#define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
54
55
56/**
57 * FNPGMRELOCATE callback mode.
58 */
59typedef enum PGMRELOCATECALL
60{
61 /** The callback is for checking if the suggested address is suitable. */
62 PGMRELOCATECALL_SUGGEST = 1,
63 /** The callback is for executing the relocation. */
64 PGMRELOCATECALL_RELOCATE
65} PGMRELOCATECALL;
66
67
68/**
69 * Callback function which will be called when PGM is trying to find
70 * a new location for the mapping.
71 *
72 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
73 * In 1) the callback should say if it objects to a suggested new location. If it
74 * accepts the new location, it is called again for doing it's relocation.
75 *
76 *
77 * @returns true if the location is ok.
78 * @returns false if another location should be found.
79 * @param GCPtrOld The old virtual address.
80 * @param GCPtrNew The new virtual address.
81 * @param enmMode Used to indicate the callback mode.
82 * @param pvUser User argument.
83 * @remark The return value is no a failure indicator, it's an acceptance
84 * indicator. Relocation can not fail!
85 */
86typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
87/** Pointer to a relocation callback function. */
88typedef FNPGMRELOCATE *PFNPGMRELOCATE;
89
90
91/**
92 * Physical page access handler type.
93 */
94typedef enum PGMPHYSHANDLERTYPE
95{
96 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
97 PGMPHYSHANDLERTYPE_MMIO = 1,
98 /** Handler all write access to a physical page range. */
99 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
100 /** Handler all access to a physical page range. */
101 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
102
103} PGMPHYSHANDLERTYPE;
104
105/**
106 * \#PF Handler callback for physical access handler ranges in RC.
107 *
108 * @returns VBox status code (appropriate for RC return).
109 * @param pVM VM Handle.
110 * @param uErrorCode CPU Error code.
111 * @param pRegFrame Trap register frame.
112 * NULL on DMA and other non CPU access.
113 * @param pvFault The fault address (cr2).
114 * @param GCPhysFault The GC physical address corresponding to pvFault.
115 * @param pvUser User argument.
116 */
117typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
118/** Pointer to PGM access callback. */
119typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
120
121/**
122 * \#PF Handler callback for physical access handler ranges in R0.
123 *
124 * @returns VBox status code (appropriate for R0 return).
125 * @param pVM VM Handle.
126 * @param uErrorCode CPU Error code.
127 * @param pRegFrame Trap register frame.
128 * NULL on DMA and other non CPU access.
129 * @param pvFault The fault address (cr2).
130 * @param GCPhysFault The GC physical address corresponding to pvFault.
131 * @param pvUser User argument.
132 */
133typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
134/** Pointer to PGM access callback. */
135typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
136
137/**
138 * Guest Access type
139 */
140typedef enum PGMACCESSTYPE
141{
142 /** Read access. */
143 PGMACCESSTYPE_READ = 1,
144 /** Write access. */
145 PGMACCESSTYPE_WRITE
146} PGMACCESSTYPE;
147
148/**
149 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
150 *
151 * The handler can not raise any faults, it's mainly for monitoring write access
152 * to certain pages.
153 *
154 * @returns VINF_SUCCESS if the handler have carried out the operation.
155 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
156 * @param pVM VM Handle.
157 * @param GCPhys The physical address the guest is writing to.
158 * @param pvPhys The HC mapping of that address.
159 * @param pvBuf What the guest is reading/writing.
160 * @param cbBuf How much it's reading/writing.
161 * @param enmAccessType The access type.
162 * @param pvUser User argument.
163 */
164typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
165/** Pointer to PGM access callback. */
166typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
167
168
169/**
170 * Virtual access handler type.
171 */
172typedef enum PGMVIRTHANDLERTYPE
173{
174 /** Write access handled. */
175 PGMVIRTHANDLERTYPE_WRITE = 1,
176 /** All access handled. */
177 PGMVIRTHANDLERTYPE_ALL,
178 /** Hypervisor write access handled.
179 * This is used to catch the guest trying to write to LDT, TSS and any other
180 * system structure which the brain dead intel guys let unprivilegde code find. */
181 PGMVIRTHANDLERTYPE_HYPERVISOR
182} PGMVIRTHANDLERTYPE;
183
184/**
185 * \#PF Handler callback for virtual access handler ranges, RC.
186 *
187 * Important to realize that a physical page in a range can have aliases, and
188 * for ALL and WRITE handlers these will also trigger.
189 *
190 * @returns VBox status code (appropriate for GC return).
191 * @param pVM VM Handle.
192 * @param uErrorCode CPU Error code.
193 * @param pRegFrame Trap register frame.
194 * @param pvFault The fault address (cr2).
195 * @param pvRange The base address of the handled virtual range.
196 * @param offRange The offset of the access into this range.
197 * (If it's a EIP range this's the EIP, if not it's pvFault.)
198 */
199typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
200/** Pointer to PGM access callback. */
201typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
202
203/**
204 * \#PF Handler callback for virtual access handler ranges, R3.
205 *
206 * Important to realize that a physical page in a range can have aliases, and
207 * for ALL and WRITE handlers these will also trigger.
208 *
209 * @returns VINF_SUCCESS if the handler have carried out the operation.
210 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
211 * @param pVM VM Handle.
212 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
213 * @param pvPtr The HC mapping of that address.
214 * @param pvBuf What the guest is reading/writing.
215 * @param cbBuf How much it's reading/writing.
216 * @param enmAccessType The access type.
217 * @param pvUser User argument.
218 */
219typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
220/** Pointer to PGM access callback. */
221typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
222
223
224/**
225 * \#PF Handler callback for invalidation of virtual access handler ranges.
226 *
227 * @param pVM VM Handle.
228 * @param GCPtr The virtual address the guest has changed.
229 */
230typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
231/** Pointer to PGM invalidation callback. */
232typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
233
234/**
235 * Paging mode.
236 */
237typedef enum PGMMODE
238{
239 /** The usual invalid value. */
240 PGMMODE_INVALID = 0,
241 /** Real mode. */
242 PGMMODE_REAL,
243 /** Protected mode, no paging. */
244 PGMMODE_PROTECTED,
245 /** 32-bit paging. */
246 PGMMODE_32_BIT,
247 /** PAE paging. */
248 PGMMODE_PAE,
249 /** PAE paging with NX enabled. */
250 PGMMODE_PAE_NX,
251 /** 64-bit AMD paging (long mode). */
252 PGMMODE_AMD64,
253 /** 64-bit AMD paging (long mode) with NX enabled. */
254 PGMMODE_AMD64_NX,
255 /** Nested paging mode (shadow only; guest physical to host physical). */
256 PGMMODE_NESTED,
257 /** Extended paging (Intel) mode. */
258 PGMMODE_EPT,
259 /** The max number of modes */
260 PGMMODE_MAX,
261 /** 32bit hackishness. */
262 PGMMODE_32BIT_HACK = 0x7fffffff
263} PGMMODE;
264
265/** Macro for checking if the guest is using paging.
266 * @param uType PGMMODE_*
267 * @remark ASSUMES certain order of the PGMMODE_* values.
268 */
269#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
270
271/**
272 * The current ROM page protection.
273 */
274typedef enum PGMROMPROT
275{
276 /** The customary invalid value. */
277 PGMROMPROT_INVALID = 0,
278 /** Read from the virgin ROM page, ignore writes.
279 * Map the virgin page, use write access handler to ignore writes. */
280 PGMROMPROT_READ_ROM_WRITE_IGNORE,
281 /** Read from the virgin ROM page, write to the shadow RAM.
282 * Map the virgin page, use write access handler change the RAM. */
283 PGMROMPROT_READ_ROM_WRITE_RAM,
284 /** Read from the shadow ROM page, ignore writes.
285 * Map the shadow page read-only, use write access handler to ignore writes. */
286 PGMROMPROT_READ_RAM_WRITE_IGNORE,
287 /** Read from the shadow ROM page, ignore writes.
288 * Map the shadow page read-write, disabled write access handler. */
289 PGMROMPROT_READ_RAM_WRITE_RAM,
290 /** The end of valid values. */
291 PGMROMPROT_END,
292 /** The usual 32-bit type size hack. */
293 PGMROMPROT_32BIT_HACK = 0x7fffffff
294} PGMROMPROT;
295
296/**
297 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
298 *
299 * @returns boolean.
300 * @param enmProt The PGMROMPROT value, must be valid.
301 */
302#define PGMROMPROT_IS_ROM(enmProt) \
303 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
304 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
305
306
307VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM);
308VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode);
309VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM);
310VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM);
311VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM);
312VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM);
313VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
314VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM);
315VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
316VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
317VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
318VMMDECL(int) PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
319VMMDECL(int) PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
320VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
321VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
322VMMDECL(int) PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
323VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
324VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
325VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
326VMMDECL(int) PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
327VMMDECL(int) PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
328VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
329VMMDECL(int) PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
330VMMDECL(bool) PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
331VMMDECL(int) PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
332VMMDECL(int) PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
333VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
334
335VMMDECL(int) PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
336VMMDECL(int) PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
337VMMDECL(int) PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
338VMMDECL(int) PGMUpdateCR3(PVM pVM, uint64_t cr3);
339VMMDECL(int) PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
340VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM);
341VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM);
342VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
343VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
344VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
345 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
346 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
347 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
348 R3PTRTYPE(const char *) pszDesc);
349VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
350VMMDECL(bool) PGMHandlerIsAddressMonitored(PVM pVM, RTGCPTR GCPtr);
351VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
352VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
353 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
354 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
355 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
356 R3PTRTYPE(const char *) pszDesc);
357VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
358VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
359VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
360VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
361VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
362VMMDECL(int) PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
363VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
364VMMDECL(bool) PGMPhysIsA20Enabled(PVM pVM);
365VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
366VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
367VMMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
368VMMDECL(int) PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
369VMMDECL(int) PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
370VMMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM);
371VMMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM);
372VMMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM);
373
374/**
375 * Page mapping lock.
376 *
377 * @remarks This doesn't work in structures shared between
378 * ring-3, ring-0 and/or GC.
379 */
380typedef struct PGMPAGEMAPLOCK
381{
382 /** @todo see PGMPhysIsPageMappingLockValid for possibly incorrect assumptions */
383#ifdef IN_RC
384 /** Just a dummy for the time being. */
385 uint32_t u32Dummy;
386#else
387 /** Pointer to the PGMPAGE. */
388 void *pvPage;
389 /** Pointer to the PGMCHUNKR3MAP. */
390 void *pvMap;
391#endif
392} PGMPAGEMAPLOCK;
393/** Pointer to a page mapping lock. */
394typedef PGMPAGEMAPLOCK *PPGMPAGEMAPLOCK;
395
396VMMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
397VMMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
398VMMDECL(int) PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
399VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
400VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
401
402/**
403 * Checks if the lock structure is valid
404 *
405 * @param pVM The VM handle.
406 * @param pLock The lock structure initialized by the mapping function.
407 */
408DECLINLINE(bool) PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
409{
410 /** @todo -> complete/change this */
411#ifdef IN_RC
412 return !!(pLock->u32Dummy);
413#else
414 return !!(pLock->pvPage);
415#endif
416}
417
418VMMDECL(int) PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr);
419VMMDECL(RTHCPTR) PGMPhysGCPhys2HCPtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
420VMMDECL(int) PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr);
421VMMDECL(int) PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint64_t cr3, unsigned fFlags, PRTHCPTR pHCPtr);
422VMMDECL(void) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
423VMMDECL(void) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
424#ifndef IN_RC /* Only ring 0 & 3. */
425VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
426VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
427VMMDECL(int) PGMPhysSimpleReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
428VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
429VMMDECL(int) PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
430VMMDECL(int) PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
431VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
432#endif /* !IN_RC */
433VMMDECL(int) PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
434#ifdef VBOX_STRICT
435VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
436VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
437VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
438#endif /* VBOX_STRICT */
439
440#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
441VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
442VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
443VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
444VMMDECL(int) PGMDynMapHCPageOff(PVM pVM, RTHCPHYS HCPhys, void **ppv);
445VMMDECL(void) PGMDynMapStartAutoSet(PVMCPU pVCpu);
446VMMDECL(void) PGMDynMapReleaseAutoSet(PVMCPU pVCpu);
447VMMDECL(void) PGMDynMapMigrateAutoSet(PVMCPU pVCpu);
448#endif
449
450
451#ifdef IN_RC
452/** @defgroup grp_pgm_gc The PGM Guest Context API
453 * @ingroup grp_pgm
454 * @{
455 */
456/** @} */
457#endif /* IN_RC */
458
459
460#ifdef IN_RING0
461/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
462 * @ingroup grp_pgm
463 * @{
464 */
465VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM);
466VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
467# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
468VMMR0DECL(int) PGMR0DynMapInit(void);
469VMMR0DECL(void) PGMR0DynMapTerm(void);
470VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
471VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
472# endif
473/** @} */
474#endif /* IN_RING0 */
475
476
477
478#ifdef IN_RING3
479/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
480 * @ingroup grp_pgm
481 * @{
482 */
483VMMR3DECL(int) PGMR3Init(PVM pVM);
484VMMR3DECL(int) PGMR3InitCPU(PVM pVM);
485VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
486VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
487VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
488VMMR3DECL(void) PGMR3Reset(PVM pVM);
489VMMR3DECL(int) PGMR3Term(PVM pVM);
490VMMR3DECL(int) PGMR3TermCPU(PVM pVM);
491VMMR3DECL(int) PGMR3LockCall(PVM pVM);
492VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
493VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
494
495#ifndef VBOX_WITH_NEW_PHYS_CODE
496VMMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS GCPhys);
497#endif /* !VBOX_WITH_NEW_PHYS_CODE */
498VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
499VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
500 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
501 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
502 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
503 R3PTRTYPE(const char *) pszDesc);
504VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
505VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
506VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
507VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
508VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
509VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
510VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
511
512/** @group PGMR3PhysRegisterRom flags.
513 * @{ */
514/** Inidicates that ROM shadowing should be enabled. */
515#define PGMPHYS_ROM_FLAG_SHADOWED RT_BIT_32(0)
516/** Indicates that what pvBinary points to won't go away
517 * and can be used for strictness checks. */
518#define PGMPHYS_ROM_FLAG_PERMANENT_BINARY RT_BIT_32(1)
519/** @} */
520
521VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
522 const void *pvBinary, uint32_t fFlags, const char *pszDesc);
523VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
524VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
525#ifndef VBOX_WITH_NEW_PHYS_CODE
526VMMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
527#endif /* !VBOX_WITH_NEW_PHYS_CODE */
528VMMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask);
529VMMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable);
530VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
531VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
532VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
533VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
534VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
535VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
536VMMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
537VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
538VMMR3DECL(int) PGMR3MapActivate(PVM pVM);
539VMMR3DECL(int) PGMR3MapDeactivate(PVM pVM);
540
541VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
542 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
543 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
544 const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
545VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
546 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
547 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
548 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
549 R3PTRTYPE(const char *) pszDesc);
550VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
551 PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
552 PFNPGMR3VIRTHANDLER pfnHandlerR3,
553 const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
554VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
555VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
556VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
557#ifdef ___VBox_dbgf_h /** @todo fix this! */
558VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
559#endif
560VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
561
562VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
563VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
564VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
565VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
566VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
567VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
568VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
569VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
570VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
571VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
572VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
573
574VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
575
576VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
577VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
578VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
579VMMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
580VMMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, RTGCPTR GCPtr, RTGCPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
581/** @} */
582#endif /* IN_RING3 */
583
584__END_DECLS
585
586/** @} */
587#endif
588
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette