VirtualBox

source: vbox/trunk/include/VBox/pgm.h@ 24130

Last change on this file since 24130 was 24061, checked in by vboxsync, 15 years ago

DBGF,DBGPlugInDiggers: Extended DBGFR3MemScan with an alignment restriction. Added DBGFR3CpuGetMode. Started on the WinNT debug digger - can detect the 32-bit kernel, locate the module list and report the nt version.
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1/** @file
2 * PGM - Page Monitor / Monitor. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_pgm_h
31#define ___VBox_pgm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/sup.h>
36#include <VBox/vmapi.h>
37#include <VBox/x86.h>
38#include <VBox/hwacc_vmx.h>
39
40RT_C_DECLS_BEGIN
41
42/** @defgroup grp_pgm The Page Monitor / Manager API
43 * @{
44 */
45
46/** Chunk size for dynamically allocated physical memory. */
47#define PGM_DYNAMIC_CHUNK_SIZE (1*1024*1024)
48/** Shift GC physical address by 20 bits to get the offset into the pvHCChunkHC array. */
49#define PGM_DYNAMIC_CHUNK_SHIFT 20
50/** Dynamic chunk offset mask. */
51#define PGM_DYNAMIC_CHUNK_OFFSET_MASK 0xfffff
52/** Dynamic chunk base mask. */
53#define PGM_DYNAMIC_CHUNK_BASE_MASK (~(RTGCPHYS)PGM_DYNAMIC_CHUNK_OFFSET_MASK)
54
55
56/**
57 * FNPGMRELOCATE callback mode.
58 */
59typedef enum PGMRELOCATECALL
60{
61 /** The callback is for checking if the suggested address is suitable. */
62 PGMRELOCATECALL_SUGGEST = 1,
63 /** The callback is for executing the relocation. */
64 PGMRELOCATECALL_RELOCATE
65} PGMRELOCATECALL;
66
67
68/**
69 * Callback function which will be called when PGM is trying to find
70 * a new location for the mapping.
71 *
72 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
73 * In 1) the callback should say if it objects to a suggested new location. If it
74 * accepts the new location, it is called again for doing it's relocation.
75 *
76 *
77 * @returns true if the location is ok.
78 * @returns false if another location should be found.
79 * @param GCPtrOld The old virtual address.
80 * @param GCPtrNew The new virtual address.
81 * @param enmMode Used to indicate the callback mode.
82 * @param pvUser User argument.
83 * @remark The return value is no a failure indicator, it's an acceptance
84 * indicator. Relocation can not fail!
85 */
86typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
87/** Pointer to a relocation callback function. */
88typedef FNPGMRELOCATE *PFNPGMRELOCATE;
89
90
91/**
92 * Physical page access handler type.
93 */
94typedef enum PGMPHYSHANDLERTYPE
95{
96 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
97 PGMPHYSHANDLERTYPE_MMIO = 1,
98 /** Handler all write access to a physical page range. */
99 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
100 /** Handler all access to a physical page range. */
101 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
102
103} PGMPHYSHANDLERTYPE;
104
105/**
106 * \#PF Handler callback for physical access handler ranges in RC.
107 *
108 * @returns VBox status code (appropriate for RC return).
109 * @param pVM VM Handle.
110 * @param uErrorCode CPU Error code.
111 * @param pRegFrame Trap register frame.
112 * NULL on DMA and other non CPU access.
113 * @param pvFault The fault address (cr2).
114 * @param GCPhysFault The GC physical address corresponding to pvFault.
115 * @param pvUser User argument.
116 */
117typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
118/** Pointer to PGM access callback. */
119typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
120
121/**
122 * \#PF Handler callback for physical access handler ranges in R0.
123 *
124 * @returns VBox status code (appropriate for R0 return).
125 * @param pVM VM Handle.
126 * @param uErrorCode CPU Error code.
127 * @param pRegFrame Trap register frame.
128 * NULL on DMA and other non CPU access.
129 * @param pvFault The fault address (cr2).
130 * @param GCPhysFault The GC physical address corresponding to pvFault.
131 * @param pvUser User argument.
132 */
133typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
134/** Pointer to PGM access callback. */
135typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
136
137/**
138 * Guest Access type
139 */
140typedef enum PGMACCESSTYPE
141{
142 /** Read access. */
143 PGMACCESSTYPE_READ = 1,
144 /** Write access. */
145 PGMACCESSTYPE_WRITE
146} PGMACCESSTYPE;
147
148/**
149 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
150 *
151 * The handler can not raise any faults, it's mainly for monitoring write access
152 * to certain pages.
153 *
154 * @returns VINF_SUCCESS if the handler have carried out the operation.
155 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
156 * @param pVM VM Handle.
157 * @param GCPhys The physical address the guest is writing to.
158 * @param pvPhys The HC mapping of that address.
159 * @param pvBuf What the guest is reading/writing.
160 * @param cbBuf How much it's reading/writing.
161 * @param enmAccessType The access type.
162 * @param pvUser User argument.
163 */
164typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
165/** Pointer to PGM access callback. */
166typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
167
168
169/**
170 * Virtual access handler type.
171 */
172typedef enum PGMVIRTHANDLERTYPE
173{
174 /** Write access handled. */
175 PGMVIRTHANDLERTYPE_WRITE = 1,
176 /** All access handled. */
177 PGMVIRTHANDLERTYPE_ALL,
178 /** Hypervisor write access handled.
179 * This is used to catch the guest trying to write to LDT, TSS and any other
180 * system structure which the brain dead intel guys let unprivilegde code find. */
181 PGMVIRTHANDLERTYPE_HYPERVISOR
182} PGMVIRTHANDLERTYPE;
183
184/**
185 * \#PF Handler callback for virtual access handler ranges, RC.
186 *
187 * Important to realize that a physical page in a range can have aliases, and
188 * for ALL and WRITE handlers these will also trigger.
189 *
190 * @returns VBox status code (appropriate for GC return).
191 * @param pVM VM Handle.
192 * @param uErrorCode CPU Error code.
193 * @param pRegFrame Trap register frame.
194 * @param pvFault The fault address (cr2).
195 * @param pvRange The base address of the handled virtual range.
196 * @param offRange The offset of the access into this range.
197 * (If it's a EIP range this's the EIP, if not it's pvFault.)
198 */
199typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
200/** Pointer to PGM access callback. */
201typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
202
203/**
204 * \#PF Handler callback for virtual access handler ranges, R3.
205 *
206 * Important to realize that a physical page in a range can have aliases, and
207 * for ALL and WRITE handlers these will also trigger.
208 *
209 * @returns VINF_SUCCESS if the handler have carried out the operation.
210 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
211 * @param pVM VM Handle.
212 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
213 * @param pvPtr The HC mapping of that address.
214 * @param pvBuf What the guest is reading/writing.
215 * @param cbBuf How much it's reading/writing.
216 * @param enmAccessType The access type.
217 * @param pvUser User argument.
218 */
219typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
220/** Pointer to PGM access callback. */
221typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
222
223
224/**
225 * \#PF Handler callback for invalidation of virtual access handler ranges.
226 *
227 * @param pVM VM Handle.
228 * @param GCPtr The virtual address the guest has changed.
229 */
230typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
231/** Pointer to PGM invalidation callback. */
232typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
233
234/**
235 * Paging mode.
236 */
237typedef enum PGMMODE
238{
239 /** The usual invalid value. */
240 PGMMODE_INVALID = 0,
241 /** Real mode. */
242 PGMMODE_REAL,
243 /** Protected mode, no paging. */
244 PGMMODE_PROTECTED,
245 /** 32-bit paging. */
246 PGMMODE_32_BIT,
247 /** PAE paging. */
248 PGMMODE_PAE,
249 /** PAE paging with NX enabled. */
250 PGMMODE_PAE_NX,
251 /** 64-bit AMD paging (long mode). */
252 PGMMODE_AMD64,
253 /** 64-bit AMD paging (long mode) with NX enabled. */
254 PGMMODE_AMD64_NX,
255 /** Nested paging mode (shadow only; guest physical to host physical). */
256 PGMMODE_NESTED,
257 /** Extended paging (Intel) mode. */
258 PGMMODE_EPT,
259 /** The max number of modes */
260 PGMMODE_MAX,
261 /** 32bit hackishness. */
262 PGMMODE_32BIT_HACK = 0x7fffffff
263} PGMMODE;
264
265/** Macro for checking if the guest is using paging.
266 * @param enmMode PGMMODE_*.
267 * @remark ASSUMES certain order of the PGMMODE_* values.
268 */
269#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
270
271/** Macro for checking if it's one of the long mode modes.
272 * @param enmMode PGMMODE_*.
273 */
274#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX || (enmMode) == PGMMODE_AMD64)
275
276/**
277 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
278 *
279 * @returns boolean.
280 * @param enmProt The PGMROMPROT value, must be valid.
281 */
282#define PGMROMPROT_IS_ROM(enmProt) \
283 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
284 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
285
286VMMDECL(bool) PGMIsLocked(PVM pVM);
287VMMDECL(bool) PGMIsLockOwner(PVM pVM);
288
289VMMDECL(int) PGMRegisterStringFormatTypes(void);
290VMMDECL(void) PGMDeregisterStringFormatTypes(void);
291VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
292VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
293VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
294VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
295VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
296VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
297VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
298VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
299VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
300VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
301VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
302VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
303VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
304VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
305VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
306#ifndef IN_RING0
307VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
308VMMDECL(int) PGMMapResolveConflicts(PVM pVM);
309#endif
310#ifdef VBOX_STRICT
311VMMDECL(void) PGMMapCheck(PVM pVM);
312#endif
313VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
314VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
315VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
316VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
317VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
318VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
319VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
320VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdPt);
321
322VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
323VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
324VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
325VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
326VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
327VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
328VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
329VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
330VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
331VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
332 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
333 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
334 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
335 R3PTRTYPE(const char *) pszDesc);
336VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
337VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
338VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
339 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
340 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
341 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
342 R3PTRTYPE(const char *) pszDesc);
343VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
344VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
345VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
346VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
347VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
348VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
349VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
350VMMDECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
351VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
352VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
353VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
354VMMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
355VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
356VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
357VMMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM);
358VMMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM);
359VMMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM);
360
361VMMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
362VMMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
363VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
364VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
365VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
366VMMDECL(int) PGMPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTR3PTR pR3Ptr);
367#ifdef VBOX_STRICT
368VMMDECL(RTR3PTR) PGMPhysGCPhys2R3PtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
369#endif
370VMMDECL(int) PGMPhysGCPtr2R3Ptr(PVMCPU pVCpu, RTGCPTR GCPtr, PRTR3PTR pR3Ptr);
371VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
372VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
373VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
374VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
375VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
376VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
377VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
378VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
379VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
380VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
381VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
382VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
383#ifdef VBOX_STRICT
384VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
385VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
386VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
387#endif /* VBOX_STRICT */
388
389#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
390VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
391VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
392# ifdef IN_RC
393VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
394VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
395VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage);
396# ifdef VBOX_STRICT
397VMMDECL(void) PGMDynCheckLocks(PVM pVM);
398# endif
399# endif
400VMMDECL(void) PGMDynMapStartAutoSet(PVMCPU pVCpu);
401VMMDECL(void) PGMDynMapReleaseAutoSet(PVMCPU pVCpu);
402VMMDECL(void) PGMDynMapFlushAutoSet(PVMCPU pVCpu);
403VMMDECL(void) PGMDynMapMigrateAutoSet(PVMCPU pVCpu);
404VMMDECL(uint32_t) PGMDynMapPushAutoSubset(PVMCPU pVCpu);
405VMMDECL(void) PGMDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
406#endif
407
408
409#ifdef IN_RC
410/** @defgroup grp_pgm_gc The PGM Guest Context API
411 * @ingroup grp_pgm
412 * @{
413 */
414/** @} */
415#endif /* IN_RC */
416
417
418#ifdef IN_RING0
419/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
420 * @ingroup grp_pgm
421 * @{
422 */
423VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
424VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
425# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
426VMMR0DECL(int) PGMR0DynMapInit(void);
427VMMR0DECL(void) PGMR0DynMapTerm(void);
428VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
429VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
430VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
431# endif
432/** @} */
433#endif /* IN_RING0 */
434
435
436
437#ifdef IN_RING3
438/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
439 * @ingroup grp_pgm
440 * @{
441 */
442VMMR3DECL(int) PGMR3Init(PVM pVM);
443VMMR3DECL(int) PGMR3InitCPU(PVM pVM);
444VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
445VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
446VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
447VMMR3DECL(void) PGMR3Reset(PVM pVM);
448VMMR3DECL(int) PGMR3Term(PVM pVM);
449VMMR3DECL(int) PGMR3TermCPU(PVM pVM);
450VMMR3DECL(int) PGMR3LockCall(PVM pVM);
451VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
452
453VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
454VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
455 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
456 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
457 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
458 R3PTRTYPE(const char *) pszDesc);
459VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
460VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
461VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
462VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
463VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
464VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
465VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
466VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
467
468/** @group PGMR3PhysRegisterRom flags.
469 * @{ */
470/** Inidicates that ROM shadowing should be enabled. */
471#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
472/** Indicates that what pvBinary points to won't go away
473 * and can be used for strictness checks. */
474#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
475/** @} */
476
477VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
478 const void *pvBinary, uint32_t fFlags, const char *pszDesc);
479VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
480VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
481VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
482/** @name PGMR3MapPT flags.
483 * @{ */
484/** The mapping may be unmapped later. The default is permanent mappings. */
485#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
486/** @} */
487VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
488VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
489VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
490VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
491VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
492VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
493VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM);
494VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
495VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
496
497VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
498 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
499 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
500 const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
501VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
502 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
503 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
504 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
505 R3PTRTYPE(const char *) pszDesc);
506VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
507 PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
508 PFNPGMR3VIRTHANDLER pfnHandlerR3,
509 const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
510VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
511VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
512VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
513#ifdef ___VBox_dbgf_h /** @todo fix this! */
514VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
515#endif
516VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
517
518VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
519VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
520VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
521VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
522VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
523VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
524VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
525VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
526VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
527VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
528VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
529VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
530VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
531VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
532VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
533VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
534
535
536VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM);
537
538VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
539
540VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
541VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
542VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
543VMMR3DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
544VMMR3DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
545VMMR3DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
546VMMR3DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
547VMMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
548VMMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
549/** @} */
550#endif /* IN_RING3 */
551
552RT_C_DECLS_END
553
554/** @} */
555#endif
556
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