rawpci.h@ 36549

Last change on this file since 36549 was 36528, checked in by vboxsync, 14 years ago
PCI: fully reworked interrupts, now HDA audio device can be reasonably passed to the guest
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 17.9 KB

Line
1	/** @file
2	* Raw PCI Devices (aka PCI pass-through). (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2010-2011 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_rawpci_h
27	#define ___VBox_rawpci_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31
32	RT_C_DECLS_BEGIN
33
34	/**
35	* Handle for the raw PCI device.
36	*/
37	typedef uint32_t PCIRAWDEVHANDLE;
38
39	/**
40	* Handle for the ISR.
41	*/
42	typedef uint32_t PCIRAWISRHANDLE;
43
44	/**
45	* Physical memory action enumeration.
46	*/
47	typedef enum PCIRAWMEMINFOACTION
48	{
49	/** Pages mapped. */
50	PCIRAW_MEMINFO_MAP,
51	/** Pages unmapped. */
52	PCIRAW_MEMINFO_UNMAP,
53	/** The usual 32-bit type blow up. */
54	PCIRAW_MEMINFO_32BIT_HACK = 0x7fffffff
55	} PCIRAWMEMINFOACTION;
56
57	/**
58	* Per-VM capability flag bits.
59	*/
60	typedef enum PCIRAWVMFLAGS
61	{
62	/** If we can use IOMMU in this VM. */
63	PCIRAW_VMFLAGS_HAS_IOMMU = (1 << 0),
64	PCIRAW_VMFLAGS_32BIT_HACK = 0x7fffffff
65	} PCIRAWVMFLAGS;
66
67	/* Forward declaration. */
68	struct RAWPCIPERVM;
69
70	/**
71	* Callback to notify raw PCI subsystem about mapping/unmapping of
72	* host pages to the guest. Typical usecase is to register physical
73	* RAM pages with IOMMU, so that it could allow DMA for PCI devices
74	* directly from the guest RAM.
75	* Region shall be one or more contigous (both host and guest) pages
76	* of physical memory.
77	*
78	* @returns VBox status code.
79	*
80	* @param pVM VM pointer.
81	* @param HostStart Physical address of region start on the host.
82	* @param GuestStart Physical address of region start on the guest.
83	* @param cMemSize Region size in bytes.
84	* @param Action Action performed (i.e. if page was mapped or unmapped).
85	*/
86	typedef DECLCALLBACK(int) FNRAWPCICONTIGPHYSMEMINFO(struct RAWPCIPERVM* pVmData, RTHCPHYS HostStart, RTGCPHYS GuestStart, uint64_t cMemSize, PCIRAWMEMINFOACTION Action);
87	typedef FNRAWPCICONTIGPHYSMEMINFO *PFNRAWPCICONTIGPHYSMEMINFO;
88
89	/** Data being part of the VM structure. */
90	typedef struct RAWPCIPERVM
91	{
92	/** Shall only be interpreted by the host PCI driver. */
93	RTR0PTR pDriverData;
94	/** Callback called when mapping of host pages to the guest changes. */
95	PFNRAWPCICONTIGPHYSMEMINFO pfnContigMemInfo;
96	/** Flags describing VM capabilities (such as IOMMU presence). */
97	uint32_t fVmCaps;
98	} RAWPCIPERVM;
99	typedef RAWPCIPERVM *PRAWPCIPERVM;
100
101	/** Parameters buffer for PCIRAWR0_DO_OPEN_DEVICE call */
102	typedef struct
103	{
104	/* in */
105	uint32_t PciAddress;
106	uint32_t fFlags;
107	/* out */
108	PCIRAWDEVHANDLE Device;
109	uint32_t fDevFlags;
110	} PCIRAWREQOPENDEVICE;
111
112	/** Parameters buffer for PCIRAWR0_DO_CLOSE_DEVICE call */
113	typedef struct
114	{
115	/* in */
116	uint32_t fFlags;
117	} PCIRAWREQCLOSEDEVICE;
118
119	/** Parameters buffer for PCIRAWR0_DO_GET_REGION_INFO call */
120	typedef struct
121	{
122	/* in */
123	int32_t iRegion;
124	/* out */
125	RTGCPHYS RegionStart;
126	uint64_t u64RegionSize;
127	bool fPresent;
128	uint32_t fFlags;
129	} PCIRAWREQGETREGIONINFO;
130
131	/** Parameters buffer for PCIRAWR0_DO_MAP_REGION call. */
132	typedef struct
133	{
134	/* in */
135	RTGCPHYS StartAddress;
136	uint64_t iRegionSize;
137	int32_t iRegion;
138	uint32_t fFlags;
139	/* out */
140	RTR3PTR pvAddressR3;
141	RTR0PTR pvAddressR0;
142	} PCIRAWREQMAPREGION;
143
144	/** Parameters buffer for PCIRAWR0_DO_UNMAP_REGION call. */
145	typedef struct
146	{
147	/* in */
148	RTGCPHYS StartAddress;
149	uint64_t iRegionSize;
150	RTR3PTR pvAddressR3;
151	RTR0PTR pvAddressR0;
152	int32_t iRegion;
153	} PCIRAWREQUNMAPREGION;
154
155	/** Parameters buffer for PCIRAWR0_DO_PIO_WRITE call. */
156	typedef struct
157	{
158	/* in */
159	uint16_t iPort;
160	uint16_t cb;
161	uint32_t iValue;
162	} PCIRAWREQPIOWRITE;
163
164	/** Parameters buffer for PCIRAWR0_DO_PIO_READ call. */
165	typedef struct
166	{
167	/* in */
168	uint16_t iPort;
169	uint16_t cb;
170	/* out */
171	uint32_t iValue;
172	} PCIRAWREQPIOREAD;
173
174	/** Memory operand. */
175	typedef struct
176	{
177	union
178	{
179	uint8_t u8;
180	uint16_t u16;
181	uint32_t u32;
182	uint64_t u64;
183	} u;
184	uint8_t cb;
185	} PCIRAWMEMLOC;
186
187	/** Parameters buffer for PCIRAWR0_DO_MMIO_WRITE call. */
188	typedef struct
189	{
190	/* in */
191	RTR0PTR Address;
192	PCIRAWMEMLOC Value;
193	} PCIRAWREQMMIOWRITE;
194
195	/** Parameters buffer for PCIRAWR0_DO_MMIO_READ call. */
196	typedef struct
197	{
198	/* in */
199	RTR0PTR Address;
200	/* inout (Value.cb is in) */
201	PCIRAWMEMLOC Value;
202	} PCIRAWREQMMIOREAD;
203
204	/* Parameters buffer for PCIRAWR0_DO_PCICFG_WRITE call. */
205	typedef struct
206	{
207	/* in */
208	uint32_t iOffset;
209	PCIRAWMEMLOC Value;
210	} PCIRAWREQPCICFGWRITE;
211
212	/** Parameters buffer for PCIRAWR0_DO_PCICFG_READ call. */
213	typedef struct
214	{
215	/* in */
216	uint32_t iOffset;
217	/* inout (Value.cb is in) */
218	PCIRAWMEMLOC Value;
219	} PCIRAWREQPCICFGREAD;
220
221	/** Parameters buffer for PCIRAWR0_DO_GET_IRQ call. */
222	typedef struct PCIRAWREQGETIRQ
223	{
224	/* in */
225	int64_t iTimeout;
226	/* out */
227	int32_t iIrq;
228	} PCIRAWREQGETIRQ;
229
230	/** Parameters buffer for PCIRAWR0_DO_POWER_STATE_CHANGE call. */
231	typedef struct PCIRAWREQPOWERSTATECHANGE
232	{
233	/* in */
234	uint32_t iState;
235	/* in/out */
236	uint64_t u64Param;
237	} PCIRAWREQPOWERSTATECHANGE;
238
239	/**
240	* Request buffer use for communication with the driver.
241	*/
242	typedef struct PCIRAWSENDREQ
243	{
244	/** The request header. */
245	SUPVMMR0REQHDR Hdr;
246	/** Alternative to passing the taking the session from the VM handle.
247	* Either use this member or use the VM handle, don't do both.
248	*/
249	PSUPDRVSESSION pSession;
250	/** Request type. */
251	int32_t iRequest;
252	/** Host device request targetted to. */
253	PCIRAWDEVHANDLE TargetDevice;
254	/** Call parameters. */
255	union
256	{
257	PCIRAWREQOPENDEVICE aOpenDevice;
258	PCIRAWREQCLOSEDEVICE aCloseDevice;
259	PCIRAWREQGETREGIONINFO aGetRegionInfo;
260	PCIRAWREQMAPREGION aMapRegion;
261	PCIRAWREQUNMAPREGION aUnmapRegion;
262	PCIRAWREQPIOWRITE aPioWrite;
263	PCIRAWREQPIOREAD aPioRead;
264	PCIRAWREQMMIOWRITE aMmioWrite;
265	PCIRAWREQMMIOREAD aMmioRead;
266	PCIRAWREQPCICFGWRITE aPciCfgWrite;
267	PCIRAWREQPCICFGREAD aPciCfgRead;
268	PCIRAWREQGETIRQ aGetIrq;
269	PCIRAWREQPOWERSTATECHANGE aPowerStateChange;
270	} u;
271	} PCIRAWSENDREQ;
272	typedef PCIRAWSENDREQ *PPCIRAWSENDREQ;
273
274	/**
275	* Operations performed by the driver.
276	*/
277	typedef enum PCIRAWR0OPERATION
278	{
279	/* Open device. */
280	PCIRAWR0_DO_OPEN_DEVICE,
281	/* Close device. */
282	PCIRAWR0_DO_CLOSE_DEVICE,
283	/* Get PCI region info. */
284	PCIRAWR0_DO_GET_REGION_INFO,
285	/* Map PCI region into VM address space. */
286	PCIRAWR0_DO_MAP_REGION,
287	/* Unmap PCI region from VM address space. */
288	PCIRAWR0_DO_UNMAP_REGION,
289	/* Perform PIO write. */
290	PCIRAWR0_DO_PIO_WRITE,
291	/* Perform PIO read. */
292	PCIRAWR0_DO_PIO_READ,
293	/* Perform MMIO write. */
294	PCIRAWR0_DO_MMIO_WRITE,
295	/* Perform MMIO read. */
296	PCIRAWR0_DO_MMIO_READ,
297	/* Perform PCI config write. */
298	PCIRAWR0_DO_PCICFG_WRITE,
299	/* Perform PCI config read. */
300	PCIRAWR0_DO_PCICFG_READ,
301	/* Get next IRQ for the device. */
302	PCIRAWR0_DO_GET_IRQ,
303	/* Enable getting IRQs for the device. */
304	PCIRAWR0_DO_ENABLE_IRQ,
305	/* Disable getting IRQs for the device. */
306	PCIRAWR0_DO_DISABLE_IRQ,
307	/* Notify driver about guest power state change. */
308	PCIRAWR0_DO_POWER_STATE_CHANGE,
309	/** The usual 32-bit type blow up. */
310	PCIRAWR0_DO_32BIT_HACK = 0x7fffffff
311	} PCIRAWR0OPERATION;
312
313	/**
314	* Power state enumeration.
315	*/
316	typedef enum PCIRAWPOWERSTATE
317	{
318	/* Power on. */
319	PCIRAW_POWER_ON,
320	/* Power off. */
321	PCIRAW_POWER_OFF,
322	/* Suspend. */
323	PCIRAW_POWER_SUSPEND,
324	/* Resume. */
325	PCIRAW_POWER_RESUME,
326	/** The usual 32-bit type blow up. */
327	PCIRAW_POWER_32BIT_HACK = 0x7fffffff
328	} PCIRAWPOWERSTATE;
329
330
331	/** Forward declarations. */
332	typedef struct RAWPCIFACTORY *PRAWPCIFACTORY;
333	typedef struct RAWPCIDEVPORT *PRAWPCIDEVPORT;
334
335	/**
336	* Interrupt service routine callback.
337	*
338	* @param pvContext Opaque user data passed to the handler.
339	* @param iIrq Interrupt number.
340	*/
341	typedef DECLCALLBACK(void) FNRAWPCIISR(void *pvContext, int32_t iIrq);
342	typedef FNRAWPCIISR *PFNRAWPCIISR;
343
344	/**
345	* This is the port on the device interface, i.e. the driver side which the
346	* host device is connected to.
347	*
348	* This is only used for the in-kernel PCI device connections.
349	*/
350	typedef struct RAWPCIDEVPORT
351	{
352	/** Structure version number. (RAWPCIDEVPORT_VERSION) */
353	uint32_t u32Version;
354
355	/**
356	* Init device.
357	*
358	* @param pPort Pointer to this structure.
359	* @param fFlags Initialization flags.
360	*/
361	DECLR0CALLBACKMEMBER(int, pfnInit,(PRAWPCIDEVPORT pPort,
362	uint32_t fFlags));
363
364
365	/**
366	* Deinit device.
367	*
368	* @param pPort Pointer to this structure.
369	* @param fFlags Initialization flags.
370	*/
371	DECLR0CALLBACKMEMBER(int, pfnDeinit,(PRAWPCIDEVPORT pPort,
372	uint32_t fFlags));
373
374
375	/**
376	* Destroy device.
377	*
378	* @param pPort Pointer to this structure.
379	*/
380	DECLR0CALLBACKMEMBER(int, pfnDestroy,(PRAWPCIDEVPORT pPort));
381
382	/**
383	* Get PCI region info.
384	*
385	* @param pPort Pointer to this structure.
386	*/
387	DECLR0CALLBACKMEMBER(int, pfnGetRegionInfo,(PRAWPCIDEVPORT pPort,
388	int32_t iRegion,
389	RTHCPHYS *pRegionStart,
390	uint64_t *pu64RegionSize,
391	bool *pfPresent,
392	uint32_t *pfFlags));
393
394
395	/**
396	* Map PCI region.
397	*
398	* @param pPort Pointer to this structure.
399	*/
400	DECLR0CALLBACKMEMBER(int, pfnMapRegion,(PRAWPCIDEVPORT pPort,
401	int32_t iRegion,
402	RTHCPHYS RegionStart,
403	uint64_t u64RegionSize,
404	int32_t fFlags,
405	RTR0PTR *pRegionBaseR0));
406
407	/**
408	* Unmap PCI region.
409	*
410	* @param pPort Pointer to this structure.
411	*/
412	DECLR0CALLBACKMEMBER(int, pfnUnmapRegion,(PRAWPCIDEVPORT pPort,
413	int32_t iRegion,
414	RTHCPHYS RegionStart,
415	uint64_t u64RegionSize,
416	RTR0PTR RegionBase));
417
418	/**
419	* Read device PCI register.
420	*
421	* @param pPort Pointer to this structure.
422	* @param Register PCI register.
423	* @param pValue Read value (with desired read width).
424	*/
425	DECLR0CALLBACKMEMBER(int, pfnPciCfgRead,(PRAWPCIDEVPORT pPort,
426	uint32_t Register,
427	PCIRAWMEMLOC *pValue));
428
429
430	/**
431	* Write device PCI register.
432	*
433	* @param pPort Pointer to this structure.
434	* @param Register PCI register.
435	* @param pValue Write value (with desired write width).
436	*/
437	DECLR0CALLBACKMEMBER(int, pfnPciCfgWrite,(PRAWPCIDEVPORT pPort,
438	uint32_t Register,
439	PCIRAWMEMLOC *pValue));
440
441	/**
442	* Request to register interrupt handler.
443	*
444	* @param pPort Pointer to this structure.
445	* @param pfnHandler Pointer to the handler.
446	* @param pIrqContext Context passed to the handler.
447	* @param phIsr Handle for the ISR, .
448	*/
449	DECLR0CALLBACKMEMBER(int, pfnRegisterIrqHandler,(PRAWPCIDEVPORT pPort,
450	PFNRAWPCIISR pfnHandler,
451	void* pIrqContext,
452	PCIRAWISRHANDLE *phIsr));
453
454	/**
455	* Request to unregister interrupt handler.
456	*
457	* @param pPort Pointer to this structure.
458	* @param hIsr Handle of ISR to unregister (retured by earlier pfnRegisterIrqHandler).
459	*/
460	DECLR0CALLBACKMEMBER(int, pfnUnregisterIrqHandler,(PRAWPCIDEVPORT pPort,
461	PCIRAWISRHANDLE hIsr));
462
463	/**
464	* Power state change notification.
465	*
466	* @param pPort Pointer to this structure.
467	* @param aState New power state.
468	* @param pu64Param State-specific in/out parameter.
469	*/
470	DECLR0CALLBACKMEMBER(int, pfnPowerStateChange,(PRAWPCIDEVPORT pPort,
471	PCIRAWPOWERSTATE aState,
472	uint64_t *pu64Param));
473
474	/** Structure version number. (RAWPCIDEVPORT_VERSION) */
475	uint32_t u32VersionEnd;
476	} RAWPCIDEVPORT;
477	/** Version number for the RAWPCIDEVPORT::u32Version and RAWPCIIFPORT::u32VersionEnd fields. */
478	#define RAWPCIDEVPORT_VERSION UINT32_C(0xAFBDCC02)
479
480	/**
481	* The component factory interface for create a raw PCI interfaces.
482	*/
483	typedef struct RAWPCIFACTORY
484	{
485	/**
486	* Release this factory.
487	*
488	* SUPR0ComponentQueryFactory (SUPDRVFACTORY::pfnQueryFactoryInterface to be precise)
489	* will retain a reference to the factory and the caller has to call this method to
490	* release it once the pfnCreateAndConnect call(s) has been done.
491	*
492	* @param pIfFactory Pointer to this structure.
493	*/
494	DECLR0CALLBACKMEMBER(void, pfnRelease,(PRAWPCIFACTORY pFactory));
495
496	/**
497	* Create an instance for the specfied host PCI card and connects it
498	* to the driver.
499	*
500	*
501	* @returns VBox status code.
502	*
503	* @param pIfFactory Pointer to this structure.
504	* @param u32HostAddress Address of PCI device on the host.
505	* @param fFlags Creation flags.
506	* @param pVmCtx Context of VM where device is created.
507	* @param ppDevPort Where to store the pointer to the device port
508	* on success.
509	*
510	*/
511	DECLR0CALLBACKMEMBER(int, pfnCreateAndConnect,(PRAWPCIFACTORY pFactory,
512	uint32_t u32HostAddress,
513	uint32_t fFlags,
514	PRAWPCIPERVM pVmCtx,
515	PRAWPCIDEVPORT *ppDevPort,
516	uint32_t *pfDevFlags));
517
518
519	/**
520	* Initialize per-VM data related to PCI passthrough.
521	*
522	* @returns VBox status code.
523	*
524	* @param pIfFactory Pointer to this structure.
525	* @param pVM Pointer to VM structure to initialize.
526	* @param pPciData Pointer to PCI data.
527	*/
528	DECLR0CALLBACKMEMBER(int, pfnInitVm,(PRAWPCIFACTORY pFactory,
529	PVM pVM,
530	PRAWPCIPERVM pPciData));
531
532	/**
533	* Deinitialize per-VM data related to PCI passthrough.
534	*
535	* @returns VBox status code.
536	*
537	* @param pIfFactory Pointer to this structure.
538	* @param pVM Pointer to VM structure to deinitialize.
539	* @param pPciData Pointer to PCI data.
540	*/
541	DECLR0CALLBACKMEMBER(void, pfnDeinitVm,(PRAWPCIFACTORY pFactory,
542	PVM pVM,
543	PRAWPCIPERVM pPciData));
544	} RAWPCIFACTORY;
545
546	#define RAWPCIFACTORY_UUID_STR "ea089839-4171-476f-adfb-9e7ab1cbd0fb"
547
548	/**
549	* Flags passed to pfnPciDeviceConstructStart(), to notify driver
550	* about options to be used to open device.
551	*/
552	typedef enum PCIRAWDRIVERFLAGS
553	{
554	/** If runtime shall try to detach host driver. */
555	PCIRAWDRIVERRFLAG_DETACH_HOST_DRIVER = (1 << 0),
556	/** The usual 32-bit type blow up. */
557	PCIRAWDRIVERRFLAG_32BIT_HACK = 0x7fffffff
558	} PCIRAWDRIVERFLAGS;
559
560	/**
561	* Flags used to describe PCI region, matches to PCIADDRESSSPACE
562	* in pci.h.
563	*/
564	typedef enum PCIRAWADDRESSSPACE
565	{
566	/** Memory. */
567	PCIRAW_ADDRESS_SPACE_MEM = 0x00,
568	/** I/O space. */
569	PCIRAW_ADDRESS_SPACE_IO = 0x01,
570	/** 32-bit BAR. */
571	PCIRAW_ADDRESS_SPACE_BAR32 = 0x00,
572	/** 64-bit BAR. */
573	PCIRAW_ADDRESS_SPACE_BAR64 = 0x04,
574	/** Prefetch memory. */
575	PCIRAW_ADDRESS_SPACE_MEM_PREFETCH = 0x08,
576	/** The usual 32-bit type blow up. */
577	PCIRAW_ADDRESS_SPACE_32BIT_HACK = 0x7fffffff
578	} PCIRAWADDRESSSPACE;
579
580	RT_C_DECLS_END
581
582	#endif

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