vm.h@ 22886

Last change on this file since 22886 was 22886, checked in by vboxsync, 16 years ago
vm.h: 64-bit host realignment.
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1	/** @file
2	* VM - The Virtual Machine, data. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_vm_h
31	#define ___VBox_vm_h
32
33	#include <VBox/cdefs.h>
34	#include <VBox/types.h>
35	#include <VBox/cpum.h>
36	#include <VBox/stam.h>
37	#include <VBox/vmapi.h>
38	#include <VBox/sup.h>
39	#include <VBox/vmm.h>
40
41
42	/** @defgroup grp_vm The Virtual Machine
43	* @{
44	*/
45
46	/**
47	* The state of a Virtual CPU.
48	*
49	* The basic state indicated here is whether the CPU has been started or not. In
50	* addition, there are sub-states when started for assisting scheduling (GVMM
51	* mostly).
52	*
53	* The transision out of the STOPPED state is done by a vmR3PowerOn.
54	* The transision back to the STOPPED state is done by vmR3PowerOff.
55	*
56	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
57	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
58	*/
59	typedef enum VMCPUSTATE
60	{
61	/** The customary invalid zero. */
62	VMCPUSTATE_INVALID = 0,
63
64	/** Virtual CPU has not yet been started. */
65	VMCPUSTATE_STOPPED,
66
67	/** CPU started. */
68	VMCPUSTATE_STARTED,
69	/** Executing guest code and can be poked. */
70	VMCPUSTATE_STARTED_EXEC,
71	/** Executing guest code in the recompiler. */
72	VMCPUSTATE_STARTED_EXEC_REM,
73	/** Halted. */
74	VMCPUSTATE_STARTED_HALTED,
75
76	/** The end of valid virtual CPU states. */
77	VMCPUSTATE_END,
78
79	/** Ensure 32-bit type. */
80	VMCPUSTATE_32BIT_HACK = 0x7fffffff
81	} VMCPUSTATE;
82
83
84	/**
85	* Per virtual CPU data.
86	*/
87	typedef struct VMCPU
88	{
89	/** Per CPU forced action.
90	* See the VMCPU_FF_* \#defines. Updated atomically. */
91	uint32_t volatile fLocalForcedActions;
92	/** The CPU state. */
93	VMCPUSTATE volatile enmState;
94
95	/** Pointer to the ring-3 UVMCPU structure. */
96	PUVMCPU pUVCpu;
97	/** Ring-3 Host Context VM Pointer. */
98	PVMR3 pVMR3;
99	/** Ring-0 Host Context VM Pointer. */
100	PVMR0 pVMR0;
101	/** Raw-mode Context VM Pointer. */
102	PVMRC pVMRC;
103	/** The CPU ID.
104	* This is the index into the VM::aCpu array. */
105	VMCPUID idCpu;
106	/** The native thread handle. */
107	RTNATIVETHREAD hNativeThread;
108	/** Which host CPU ID is this EMT running on.
109	* Only valid when in RC or HWACCMR0 with scheduling disabled. */
110	RTCPUID volatile idHostCpu;
111
112	/** Align the next bit on a 64-byte boundary.
113	*
114	* @remarks The aligments of the members that are larger than 48 bytes should be
115	* 64-byte for cache line reasons. structs containing small amounts of
116	* data could be lumped together at the end with a < 64 byte padding
117	* following it (to grow into and align the struct size).
118	* */
119	uint32_t au32Alignment[HC_ARCH_BITS == 32 ? 7 : 3];
120
121	/** CPUM part. */
122	union
123	{
124	#ifdef ___CPUMInternal_h
125	struct CPUMCPU s;
126	#endif
127	char padding[3456]; /* multiple of 64 */
128	} cpum;
129
130	/** PGM part. */
131	union
132	{
133	#ifdef ___PGMInternal_h
134	struct PGMCPU s;
135	#endif
136	char padding[281024]; / multiple of 64 */
137	} pgm;
138
139	/** HWACCM part. */
140	union
141	{
142	#ifdef ___HWACCMInternal_h
143	struct HWACCMCPU s;
144	#endif
145	char padding[5248]; /* multiple of 64 */
146	} hwaccm;
147
148	/** EM part. */
149	union
150	{
151	#ifdef ___EMInternal_h
152	struct EMCPU s;
153	#endif
154	char padding[1408]; /* multiple of 64 */
155	} em;
156
157	/** TRPM part. */
158	union
159	{
160	#ifdef ___TRPMInternal_h
161	struct TRPMCPU s;
162	#endif
163	char padding[128]; /* multiple of 64 */
164	} trpm;
165
166	/** TM part. */
167	union
168	{
169	#ifdef ___TMInternal_h
170	struct TMCPU s;
171	#endif
172	char padding[64]; /* multiple of 64 */
173	} tm;
174
175	/** VMM part. */
176	union
177	{
178	#ifdef ___VMMInternal_h
179	struct VMMCPU s;
180	#endif
181	char padding[256]; /* multiple of 64 */
182	} vmm;
183
184	/** PDM part. */
185	union
186	{
187	#ifdef ___PDMInternal_h
188	struct PDMCPU s;
189	#endif
190	char padding[128]; /* multiple of 64 */
191	} pdm;
192
193	/** IOM part. */
194	union
195	{
196	#ifdef ___IOMInternal_h
197	struct IOMCPU s;
198	#endif
199	char padding[512]; /* multiple of 64 */
200	} iom;
201
202	/** DBGF part.
203	* @todo Combine this with other tiny structures. */
204	union
205	{
206	#ifdef ___DBGFInternal_h
207	struct DBGFCPU s;
208	#endif
209	uint8_t padding[64]; /* multiple of 64 */
210	} dbgf;
211
212	/** Align at page boundrary. */
213	uint8_t abReserved[HC_ARCH_BITS == 32 ? 448 : 960];
214	} VMCPU;
215
216
217	/** @name Operations on VMCPU::enmState
218	* @{ */
219	/** Gets the VMCPU state. */
220	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
221	/** Sets the VMCPU state. */
222	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
223	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
224	/** Cmpares and sets the VMCPU state. */
225	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
226	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
227	/** Checks the VMCPU state. */
228	#define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
229	do { \
230	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
231	AssertMsg(enmState == (enmExpectedState), \
232	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
233	enmState, enmExpectedState, (pVCpu)->idCpu)); \
234	} while (0)
235	/** Tests if the state means that the CPU is started. */
236	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
237	/** Tests if the state means that the CPU is stopped. */
238	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
239	/** @} */
240
241
242	/** The name of the Guest Context VMM Core module. */
243	#define VMMGC_MAIN_MODULE_NAME "VMMGC.gc"
244	/** The name of the Ring 0 Context VMM Core module. */
245	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
246
247	/** VM Forced Action Flags.
248	*
249	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
250	* action mask of a VM.
251	*
252	* @{
253	*/
254	/** The virtual sync clock has been stopped, go to TM until it has been
255	* restarted... */
256	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
257	/** PDM Queues are pending. */
258	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
259	/** The bit number for VM_FF_PDM_QUEUES. */
260	#define VM_FF_PDM_QUEUES_BIT 3
261	/** PDM DMA transfers are pending. */
262	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
263	/** The bit number for VM_FF_PDM_DMA. */
264	#define VM_FF_PDM_DMA_BIT 4
265	/** This action forces the VM to call DBGF so DBGF can service debugger
266	* requests in the emulation thread.
267	* This action flag stays asserted till DBGF clears it.*/
268	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
269	/** The bit number for VM_FF_DBGF. */
270	#define VM_FF_DBGF_BIT 8
271	/** This action forces the VM to service pending requests from other
272	* thread or requests which must be executed in another context. */
273	#define VM_FF_REQUEST RT_BIT_32(9)
274	/** Terminate the VM immediately. */
275	#define VM_FF_TERMINATE RT_BIT_32(10)
276	/** Reset the VM. (postponed) */
277	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
278	/** The bit number for VM_FF_RESET. */
279	#define VM_FF_RESET_BIT 11
280	/** EMT rendezvous in VMM. */
281	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
282	#define VM_FF_EMT_RENDEZVOUS_BIT 12
283
284	/** PGM needs to allocate handy pages. */
285	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
286	/** PGM is out of memory.
287	* Abandon all loops and code paths which can be resumed and get up to the EM
288	* loops. */
289	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
290	/** REM needs to be informed about handler changes. */
291	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
292	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
293	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
294	/** Suspend the VM - debug only. */
295	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
296
297
298	/** This action forces the VM to check any pending interrups on the APIC. */
299	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
300	/** This action forces the VM to check any pending interrups on the PIC. */
301	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
302	/** This action forces the VM to schedule and run pending timer (TM).
303	* @remarks Don't move - PATM compatability. */
304	#define VMCPU_FF_TIMER RT_BIT_32(2)
305	/** This action forces the VM to check any pending NMIs. */
306	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
307	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
308	/** This action forces the VM to check any pending SMIs. */
309	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
310	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
311	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
312	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
313	/** This action forces the VM to service pending requests from other
314	* thread or requests which must be executed in another context. */
315	#define VMCPU_FF_REQUEST RT_BIT_32(9)
316	/** This action forces the VM to resync the page tables before going
317	* back to execute guest code. (GLOBAL FLUSH) */
318	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
319	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
320	* (NON-GLOBAL FLUSH) */
321	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
322	/** Check for pending TLB shootdown actions. */
323	#define VMCPU_FF_TLB_SHOOTDOWN RT_BIT_32(18)
324	/** Check for pending TLB flush action. */
325	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
326	/** The bit number for VMCPU_FF_TLB_FLUSH. */
327	#define VMCPU_FF_TLB_FLUSH_BIT 19
328	/** Check the interupt and trap gates */
329	#define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
330	/** Check Guest's TSS ring 0 stack */
331	#define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
332	/** Check Guest's GDT table */
333	#define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
334	/** Check Guest's LDT table */
335	#define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
336	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
337	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
338	/** CSAM needs to scan the page that's being executed */
339	#define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
340	/** CSAM needs to do some homework. */
341	#define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
342	/** Force return to Ring-3. */
343	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
344
345	/** Externally VM forced actions. Used to quit the idle/wait loop. */
346	#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS)
347	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
348	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
349
350	/** Externally forced VM actions. Used to quit the idle/wait loop. */
351	#define VM_FF_EXTERNAL_HALTED_MASK (VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
352	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
353	#define VMCPU_FF_EXTERNAL_HALTED_MASK (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_REQUEST \| VMCPU_FF_TIMER)
354
355	/** High priority VM pre-execution actions. */
356	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \| VM_FF_DEBUG_SUSPEND \
357	\| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
358	/** High priority VMCPU pre-execution actions. */
359	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \
360	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
361	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
362
363	/** High priority VM pre raw-mode execution mask. */
364	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
365	/** High priority VMCPU pre raw-mode execution mask. */
366	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
367	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
368
369	/** High priority post-execution actions. */
370	#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
371	/** High priority post-execution actions. */
372	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK (VMCPU_FF_PDM_CRITSECT\|VMCPU_FF_CSAM_PENDING_ACTION)
373
374	/** Normal priority VM post-execution actions. */
375	#define VM_FF_NORMAL_PRIORITY_POST_MASK (VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
376	/** Normal priority VMCPU post-execution actions. */
377	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK (VMCPU_FF_CSAM_SCAN_PAGE)
378
379	/** Normal priority VM actions. */
380	#define VM_FF_NORMAL_PRIORITY_MASK (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
381	/** Normal priority VMCPU actions. */
382	#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST)
383
384	/** Flags to clear before resuming guest execution. */
385	#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
386
387	/** VM Flags that cause the HWACCM loops to go back to ring-3. */
388	#define VM_FF_HWACCM_TO_R3_MASK (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_QUEUES)
389	/** VMCPU Flags that cause the HWACCM loops to go back to ring-3. */
390	#define VMCPU_FF_HWACCM_TO_R3_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER)
391
392	/** All the forced VM flags. */
393	#define VM_FF_ALL_MASK (~0U)
394	/** All the forced VMCPU flags. */
395	#define VMCPU_FF_ALL_MASK (~0U)
396
397	/** All the forced VM flags. */
398	#define VM_FF_ALL_BUT_RAW_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
399	/** All the forced VMCPU flags. */
400	#define VMCPU_FF_ALL_BUT_RAW_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_PDM_CRITSECT))
401
402	/** @} */
403
404	/** @def VM_FF_SET
405	* Sets a force action flag.
406	*
407	* @param pVM VM Handle.
408	* @param fFlag The flag to set.
409	*/
410	#if 1
411	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
412	#else
413	# define VM_FF_SET(pVM, fFlag) \
414	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
415	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
416	} while (0)
417	#endif
418
419	/** @def VMCPU_FF_SET
420	* Sets a force action flag for the given VCPU.
421	*
422	* @param pVCpu VMCPU Handle.
423	* @param fFlag The flag to set.
424	*/
425	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
426
427	/** @def VM_FF_CLEAR
428	* Clears a force action flag.
429	*
430	* @param pVM VM Handle.
431	* @param fFlag The flag to clear.
432	*/
433	#if 1
434	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
435	#else
436	# define VM_FF_CLEAR(pVM, fFlag) \
437	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
438	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
439	} while (0)
440	#endif
441
442	/** @def VMCPU_FF_CLEAR
443	* Clears a force action flag for the given VCPU.
444	*
445	* @param pVCpu VMCPU Handle.
446	* @param fFlag The flag to clear.
447	*/
448	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
449
450	/** @def VM_FF_ISSET
451	* Checks if a force action flag is set.
452	*
453	* @param pVM VM Handle.
454	* @param fFlag The flag to check.
455	*/
456	#define VM_FF_ISSET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
457
458	/** @def VMCPU_FF_ISSET
459	* Checks if a force action flag is set for the given VCPU.
460	*
461	* @param pVCpu VMCPU Handle.
462	* @param fFlag The flag to check.
463	*/
464	#define VMCPU_FF_ISSET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
465
466	/** @def VM_FF_ISPENDING
467	* Checks if one or more force action in the specified set is pending.
468	*
469	* @param pVM VM Handle.
470	* @param fFlags The flags to check for.
471	*/
472	#define VM_FF_ISPENDING(pVM, fFlags) ((pVM)->fGlobalForcedActions & (fFlags))
473
474	/** @def VM_FF_TESTANDCLEAR
475	* Checks if one (!) force action in the specified set is pending and clears it atomically
476	*
477	* @returns true if the bit was set.
478	* @returns false if the bit was clear.
479	* @param pVM VM Handle.
480	* @param iBit Bit position to check and clear
481	*/
482	#define VM_FF_TESTANDCLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
483
484	/** @def VMCPU_FF_TESTANDCLEAR
485	* Checks if one (!) force action in the specified set is pending and clears it atomically
486	*
487	* @returns true if the bit was set.
488	* @returns false if the bit was clear.
489	* @param pVCpu VMCPU Handle.
490	* @param iBit Bit position to check and clear
491	*/
492	#define VMCPU_FF_TESTANDCLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
493
494	/** @def VMCPU_FF_ISPENDING
495	* Checks if one or more force action in the specified set is pending for the given VCPU.
496	*
497	* @param pVCpu VMCPU Handle.
498	* @param fFlags The flags to check for.
499	*/
500	#define VMCPU_FF_ISPENDING(pVCpu, fFlags) ((pVCpu)->fLocalForcedActions & (fFlags))
501
502	/** @def VM_FF_ISPENDING
503	* Checks if one or more force action in the specified set is pending while one
504	* or more other ones are not.
505	*
506	* @param pVM VM Handle.
507	* @param fFlags The flags to check for.
508	* @param fExcpt The flags that should not be set.
509	*/
510	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
511
512	/** @def VMCPU_FF_IS_PENDING_EXCEPT
513	* Checks if one or more force action in the specified set is pending for the given
514	* VCPU while one or more other ones are not.
515	*
516	* @param pVCpu VMCPU Handle.
517	* @param fFlags The flags to check for.
518	* @param fExcpt The flags that should not be set.
519	*/
520	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
521
522	/** @def VM_IS_EMT
523	* Checks if the current thread is the emulation thread (EMT).
524	*
525	* @remark The ring-0 variation will need attention if we expand the ring-0
526	* code to let threads other than EMT mess around with the VM.
527	*/
528	#ifdef IN_RC
529	# define VM_IS_EMT(pVM) true
530	#else
531	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
532	#endif
533
534	/** @def VMCPU_IS_EMT
535	* Checks if the current thread is the emulation thread (EMT) for the specified
536	* virtual CPU.
537	*/
538	#ifdef IN_RC
539	# define VMCPU_IS_EMT(pVCpu) true
540	#else
541	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
542	#endif
543
544	/** @def VM_ASSERT_EMT
545	* Asserts that the current thread IS the emulation thread (EMT).
546	*/
547	#ifdef IN_RC
548	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
549	#elif defined(IN_RING0)
550	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
551	#else
552	# define VM_ASSERT_EMT(pVM) \
553	AssertMsg(VM_IS_EMT(pVM), \
554	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
555	#endif
556
557	/** @def VMCPU_ASSERT_EMT
558	* Asserts that the current thread IS the emulation thread (EMT) of the
559	* specified virtual CPU.
560	*/
561	#ifdef IN_RC
562	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
563	#elif defined(IN_RING0)
564	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
565	#else
566	# define VMCPU_ASSERT_EMT(pVCpu) \
567	AssertMsg(VMCPU_IS_EMT(pVCpu), \
568	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
569	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
570	#endif
571
572	/** @def VM_ASSERT_EMT_RETURN
573	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
574	*/
575	#ifdef IN_RC
576	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
577	#elif defined(IN_RING0)
578	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
579	#else
580	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
581	AssertMsgReturn(VM_IS_EMT(pVM), \
582	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
583	(rc))
584	#endif
585
586	/** @def VMCPU_ASSERT_EMT_RETURN
587	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
588	*/
589	#ifdef IN_RC
590	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
591	#elif defined(IN_RING0)
592	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
593	#else
594	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
595	AssertMsg(VMCPU_IS_EMT(pVCpu), \
596	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
597	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
598	(rc))
599	#endif
600
601	/** @def VM_ASSERT_EMT0
602	* Asserts that the current thread IS emulation thread \#0 (EMT0).
603	*/
604	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
605
606	/** @def VM_ASSERT_EMT0_RETURN
607	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
608	* it isn't.
609	*/
610	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
611
612
613	/**
614	* Asserts that the current thread is NOT the emulation thread.
615	*/
616	#define VM_ASSERT_OTHER_THREAD(pVM) \
617	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
618
619
620	/** @def VM_ASSERT_STATE_RETURN
621	* Asserts a certain VM state.
622	*/
623	#define VM_ASSERT_STATE(pVM, _enmState) \
624	AssertMsg((pVM)->enmVMState == (_enmState), \
625	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
626
627	/** @def VM_ASSERT_STATE_RETURN
628	* Asserts a certain VM state and returns if it doesn't match.
629	*/
630	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
631	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
632	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
633	(rc))
634
635	/** @def VM_ASSERT_VALID_EXT_RETURN
636	* Asserts a the VM handle is valid for external access, i.e. not being
637	* destroy or terminated.
638	*/
639	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
640	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
641	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
642	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
643	&& VM_IS_EMT(pVM))), \
644	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
645	? VMGetStateName(pVM->enmVMState) : ""), \
646	(rc))
647
648	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
649	* Asserts a the VMCPU handle is valid for external access, i.e. not being
650	* destroy or terminated.
651	*/
652	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
653	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
654	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
655	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
656	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
657	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
658	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
659	(rc))
660
661
662	/** This is the VM structure.
663	*
664	* It contains (nearly?) all the VM data which have to be available in all
665	* contexts. Even if it contains all the data the idea is to use APIs not
666	* to modify all the members all around the place. Therefore we make use of
667	* unions to hide everything which isn't local to the current source module.
668	* This means we'll have to pay a little bit of attention when adding new
669	* members to structures in the unions and make sure to keep the padding sizes
670	* up to date.
671	*
672	* Run tstVMStructSize after update!
673	*/
674	typedef struct VM
675	{
676	/** The state of the VM.
677	* This field is read only to everyone except the VM and EM. */
678	VMSTATE enmVMState;
679	/** Forced action flags.
680	* See the VM_FF_* \#defines. Updated atomically.
681	*/
682	volatile uint32_t fGlobalForcedActions;
683	/** Pointer to the array of page descriptors for the VM structure allocation. */
684	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
685	/** Session handle. For use when calling SUPR0 APIs. */
686	PSUPDRVSESSION pSession;
687	/** Pointer to the ring-3 VM structure. */
688	PUVM pUVM;
689	/** Ring-3 Host Context VM Pointer. */
690	R3PTRTYPE(struct VM *) pVMR3;
691	/** Ring-0 Host Context VM Pointer. */
692	R0PTRTYPE(struct VM *) pVMR0;
693	/** Raw-mode Context VM Pointer. */
694	RCPTRTYPE(struct VM *) pVMRC;
695
696	/** The GVM VM handle. Only the GVM should modify this field. */
697	uint32_t hSelf;
698	/** Number of virtual CPUs. */
699	uint32_t cCPUs;
700
701	/** Size of the VM structure including the VMCPU array. */
702	uint32_t cbSelf;
703
704	/** Offset to the VMCPU array starting from beginning of this structure. */
705	uint32_t offVMCPU;
706
707	/** Reserved; alignment. */
708	uint32_t u32Reserved[6];
709
710	/** @name Public VMM Switcher APIs
711	* @{ */
712	/**
713	* Assembly switch entry point for returning to host context.
714	* This function will clean up the stack frame.
715	*
716	* @param eax The return code, register.
717	* @param Ctx The guest core context.
718	* @remark Assume interrupts disabled.
719	*/
720	RTRCPTR pfnVMMGCGuestToHostAsmGuestCtx/(int32_t eax, CPUMCTXCORE Ctx)/;
721
722	/**
723	* Assembly switch entry point for returning to host context.
724	*
725	* This is an alternative entry point which we'll be using when the we have the
726	* hypervisor context and need to save that before going to the host.
727	*
728	* This is typically useful when abandoning the hypervisor because of a trap
729	* and want the trap state to be saved.
730	*
731	* @param eax The return code, register.
732	* @param ecx Pointer to the hypervisor core context, register.
733	* @remark Assume interrupts disabled.
734	*/
735	RTRCPTR pfnVMMGCGuestToHostAsmHyperCtx/(int32_t eax, PCPUMCTXCORE ecx)/;
736
737	/**
738	* Assembly switch entry point for returning to host context.
739	*
740	* This is an alternative to the two *Ctx APIs and implies that the context has already
741	* been saved, or that it's just a brief return to HC and that the caller intends to resume
742	* whatever it is doing upon 'return' from this call.
743	*
744	* @param eax The return code, register.
745	* @remark Assume interrupts disabled.
746	*/
747	RTRCPTR pfnVMMGCGuestToHostAsm/(int32_t eax)/;
748	/** @} */
749
750
751	/** @name Various VM data owned by VM.
752	* @{ */
753	RTTHREAD uPadding1;
754	/** The native handle of ThreadEMT. Getting the native handle
755	* is generally faster than getting the IPRT one (except on OS/2 :-). */
756	RTNATIVETHREAD uPadding2;
757	/** @} */
758
759
760	/** @name Various items that are frequently accessed.
761	* @{ */
762	/** Raw ring-3 indicator. */
763	bool fRawR3Enabled;
764	/** Raw ring-0 indicator. */
765	bool fRawR0Enabled;
766	/** PATM enabled flag.
767	* This is placed here for performance reasons. */
768	bool fPATMEnabled;
769	/** CSAM enabled flag.
770	* This is placed here for performance reasons. */
771	bool fCSAMEnabled;
772	/** Hardware VM support is available and enabled.
773	* This is placed here for performance reasons. */
774	bool fHWACCMEnabled;
775	/** Hardware VM support is required and non-optional.
776	* This is initialized together with the rest of the VM structure. */
777	bool fHwVirtExtForced;
778	/** PARAV enabled flag. */
779	bool fPARAVEnabled;
780	/** @} */
781
782
783	/* padding to make gnuc put the StatQemuToGC where msc does. */
784	#if HC_ARCH_BITS == 32
785	uint32_t padding0;
786	#endif
787
788	/** Profiling the total time from Qemu to GC. */
789	STAMPROFILEADV StatTotalQemuToGC;
790	/** Profiling the total time from GC to Qemu. */
791	STAMPROFILEADV StatTotalGCToQemu;
792	/** Profiling the total time spent in GC. */
793	STAMPROFILEADV StatTotalInGC;
794	/** Profiling the total time spent not in Qemu. */
795	STAMPROFILEADV StatTotalInQemu;
796	/** Profiling the VMMSwitcher code for going to GC. */
797	STAMPROFILEADV StatSwitcherToGC;
798	/** Profiling the VMMSwitcher code for going to HC. */
799	STAMPROFILEADV StatSwitcherToHC;
800	STAMPROFILEADV StatSwitcherSaveRegs;
801	STAMPROFILEADV StatSwitcherSysEnter;
802	STAMPROFILEADV StatSwitcherDebug;
803	STAMPROFILEADV StatSwitcherCR0;
804	STAMPROFILEADV StatSwitcherCR4;
805	STAMPROFILEADV StatSwitcherJmpCR3;
806	STAMPROFILEADV StatSwitcherRstrRegs;
807	STAMPROFILEADV StatSwitcherLgdt;
808	STAMPROFILEADV StatSwitcherLidt;
809	STAMPROFILEADV StatSwitcherLldt;
810	STAMPROFILEADV StatSwitcherTSS;
811
812	/** @todo Realign everything on 64 byte boundaries to better match the
813	* cache-line size. */
814	/* padding - the unions must be aligned on 32 bytes boundraries. */
815	uint32_t padding[HC_ARCH_BITS == 32 ? 4+8 : 6];
816
817	/** CPUM part. */
818	union
819	{
820	#ifdef ___CPUMInternal_h
821	struct CPUM s;
822	#endif
823	uint8_t padding[1472]; /* multiple of 64 */
824	} cpum;
825
826	/** VMM part. */
827	union
828	{
829	#ifdef ___VMMInternal_h
830	struct VMM s;
831	#endif
832	uint8_t padding[1536]; /* multiple of 64 */
833	} vmm;
834
835	/** PGM part. */
836	union
837	{
838	#ifdef ___PGMInternal_h
839	struct PGM s;
840	#endif
841	uint8_t padding[6080]; /* multiple of 64 */
842	} pgm;
843
844	/** HWACCM part. */
845	union
846	{
847	#ifdef ___HWACCMInternal_h
848	struct HWACCM s;
849	#endif
850	uint8_t padding[5376]; /* multiple of 64 */
851	} hwaccm;
852
853	/** TRPM part. */
854	union
855	{
856	#ifdef ___TRPMInternal_h
857	struct TRPM s;
858	#endif
859	uint8_t padding[5184]; /* multiple of 64 */
860	} trpm;
861
862	/** SELM part. */
863	union
864	{
865	#ifdef ___SELMInternal_h
866	struct SELM s;
867	#endif
868	uint8_t padding[576]; /* multiple of 64 */
869	} selm;
870
871	/** MM part. */
872	union
873	{
874	#ifdef ___MMInternal_h
875	struct MM s;
876	#endif
877	uint8_t padding[192]; /* multiple of 64 */
878	} mm;
879
880	/** PDM part. */
881	union
882	{
883	#ifdef ___PDMInternal_h
884	struct PDM s;
885	#endif
886	uint8_t padding[1536]; /* multiple of 64 */
887	} pdm;
888
889	/** IOM part. */
890	union
891	{
892	#ifdef ___IOMInternal_h
893	struct IOM s;
894	#endif
895	uint8_t padding[832]; /* multiple of 64 */
896	} iom;
897
898	/** PATM part. */
899	union
900	{
901	#ifdef ___PATMInternal_h
902	struct PATM s;
903	#endif
904	uint8_t padding[768]; /* multiple of 64 */
905	} patm;
906
907	/** CSAM part. */
908	union
909	{
910	#ifdef ___CSAMInternal_h
911	struct CSAM s;
912	#endif
913	uint8_t padding[1088]; /* multiple of 64 */
914	} csam;
915
916	/** EM part. */
917	union
918	{
919	#ifdef ___EMInternal_h
920	struct EM s;
921	#endif
922	uint8_t padding[256]; /* multiple of 64 */
923	} em;
924
925	/** TM part. */
926	union
927	{
928	#ifdef ___TMInternal_h
929	struct TM s;
930	#endif
931	uint8_t padding[2112]; /* multiple of 64 */
932	} tm;
933
934	/** DBGF part. */
935	union
936	{
937	#ifdef ___DBGFInternal_h
938	struct DBGF s;
939	#endif
940	uint8_t padding[2368]; /* multiple of 64 */
941	} dbgf;
942
943	/** SSM part. */
944	union
945	{
946	#ifdef ___SSMInternal_h
947	struct SSM s;
948	#endif
949	uint8_t padding[128]; /* multiple of 64 */
950	} ssm;
951
952	/** REM part. */
953	union
954	{
955	#ifdef ___REMInternal_h
956	struct REM s;
957	#endif
958
959	/** @def VM_REM_SIZE
960	* Must be multiple of 32 and coherent with REM_ENV_SIZE from REMInternal.h. */
961	# define VM_REM_SIZE 0x11100
962	uint8_t padding[VM_REM_SIZE]; /* multiple of 32 */
963	} rem;
964
965	/* ---- begin small stuff ---- */
966
967	/** VM part. */
968	union
969	{
970	#ifdef ___VMInternal_h
971	struct VMINT s;
972	#endif
973	uint8_t padding[24]; /* multiple of 8 */
974	} vm;
975
976	/** PARAV part. */
977	union
978	{
979	#ifdef ___PARAVInternal_h
980	struct PARAV s;
981	#endif
982	uint8_t padding[24]; /* multiple of 8 */
983	} parav;
984
985	/** CFGM part. */
986	union
987	{
988	#ifdef ___CFGMInternal_h
989	struct CFGM s;
990	#endif
991	uint8_t padding[8]; /* multiple of 8 */
992	} cfgm;
993
994	/** Padding for aligning the cpu array on a 64 byte boundrary. */
995	uint8_t abReserved2[8 + (HC_ARCH_BITS == 32 ? 3712 : 2112)];
996
997	/* ---- end small stuff ---- */
998
999	/** VMCPU array for the configured number of virtual CPUs.
1000	* Must be aligned on a page boundrary for TLB hit reasons as well as
1001	* alignment of VMCPU members. */
1002	VMCPU aCpus[1];
1003	} VM;
1004
1005
1006	#ifdef IN_RC
1007	RT_C_DECLS_BEGIN
1008
1009	/** The VM structure.
1010	* This is imported from the VMMGCBuiltin module, i.e. it's a one
1011	* of those magic globals which we should avoid using.
1012	*/
1013	extern DECLIMPORT(VM) g_VM;
1014
1015	RT_C_DECLS_END
1016	#endif
1017
1018	/** @} */
1019
1020	#endif

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