| 1 | /** @file
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| 2 | * APIC - Advanced Programmable Interrupt Controller.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2006-2017 Oracle Corporation
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| 7 | *
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| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 9 | * available from http://www.virtualbox.org. This file is free software;
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| 10 | * you can redistribute it and/or modify it under the terms of the GNU
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| 11 | * General Public License (GPL) as published by the Free Software
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| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 15 | *
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| 16 | * The contents of this file may alternatively be used under the terms
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| 17 | * of the Common Development and Distribution License Version 1.0
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| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 19 | * VirtualBox OSE distribution, in which case the provisions of the
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| 20 | * CDDL are applicable instead of those of the GPL.
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| 21 | *
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| 22 | * You may elect to license modified versions of this file under the
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| 23 | * terms and conditions of either the GPL or the CDDL or both.
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| 24 | */
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| 25 |
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| 26 | #ifndef ___VBox_vmm_apic_h
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| 27 | #define ___VBox_vmm_apic_h
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| 28 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 29 | # pragma once
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| 30 | #endif
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| 31 |
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| 32 | #include <VBox/types.h>
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| 33 | struct PDMDEVREGCB;
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| 34 |
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| 35 | /** @defgroup grp_apic The local APIC VMM API
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| 36 | * @ingroup grp_vmm
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| 37 | * @{
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| 38 | */
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| 39 |
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| 40 | /** Offset of APIC ID Register. */
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| 41 | #define XAPIC_OFF_ID 0x020
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| 42 | /** Offset of APIC Version Register. */
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| 43 | #define XAPIC_OFF_VERSION 0x030
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| 44 | /** Offset of Task Priority Register. */
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| 45 | #define XAPIC_OFF_TPR 0x080
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| 46 | /** Offset of Arbitrartion Priority register. */
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| 47 | #define XAPIC_OFF_APR 0x090
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| 48 | /** Offset of Processor Priority register. */
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| 49 | #define XAPIC_OFF_PPR 0x0A0
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| 50 | /** Offset of End Of Interrupt register. */
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| 51 | #define XAPIC_OFF_EOI 0x0B0
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| 52 | /** Offset of Remote Read Register. */
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| 53 | #define XAPIC_OFF_RRD 0x0C0
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| 54 | /** Offset of Logical Destination Register. */
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| 55 | #define XAPIC_OFF_LDR 0x0D0
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| 56 | /** Offset of Destination Format Register. */
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| 57 | #define XAPIC_OFF_DFR 0x0E0
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| 58 | /** Offset of Spurious Interrupt Vector Register. */
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| 59 | #define XAPIC_OFF_SVR 0x0F0
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| 60 | /** Offset of In-service Register (bits 31:0). */
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| 61 | #define XAPIC_OFF_ISR0 0x100
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| 62 | /** Offset of In-service Register (bits 63:32). */
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| 63 | #define XAPIC_OFF_ISR1 0x110
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| 64 | /** Offset of In-service Register (bits 95:64). */
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| 65 | #define XAPIC_OFF_ISR2 0x120
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| 66 | /** Offset of In-service Register (bits 127:96). */
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| 67 | #define XAPIC_OFF_ISR3 0x130
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| 68 | /** Offset of In-service Register (bits 159:128). */
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| 69 | #define XAPIC_OFF_ISR4 0x140
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| 70 | /** Offset of In-service Register (bits 191:160). */
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| 71 | #define XAPIC_OFF_ISR5 0x150
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| 72 | /** Offset of In-service Register (bits 223:192). */
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| 73 | #define XAPIC_OFF_ISR6 0x160
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| 74 | /** Offset of In-service Register (bits 255:224). */
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| 75 | #define XAPIC_OFF_ISR7 0x170
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| 76 | /** Offset of Trigger Mode Register (bits 31:0). */
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| 77 | #define XAPIC_OFF_TMR0 0x180
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| 78 | /** Offset of Trigger Mode Register (bits 63:32). */
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| 79 | #define XAPIC_OFF_TMR1 0x190
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| 80 | /** Offset of Trigger Mode Register (bits 95:64). */
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| 81 | #define XAPIC_OFF_TMR2 0x1A0
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| 82 | /** Offset of Trigger Mode Register (bits 127:96). */
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| 83 | #define XAPIC_OFF_TMR3 0x1B0
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| 84 | /** Offset of Trigger Mode Register (bits 159:128). */
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| 85 | #define XAPIC_OFF_TMR4 0x1C0
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| 86 | /** Offset of Trigger Mode Register (bits 191:160). */
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| 87 | #define XAPIC_OFF_TMR5 0x1D0
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| 88 | /** Offset of Trigger Mode Register (bits 223:192). */
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| 89 | #define XAPIC_OFF_TMR6 0x1E0
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| 90 | /** Offset of Trigger Mode Register (bits 255:224). */
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| 91 | #define XAPIC_OFF_TMR7 0x1F0
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| 92 | /** Offset of Interrupt Request Register (bits 31:0). */
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| 93 | #define XAPIC_OFF_IRR0 0x200
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| 94 | /** Offset of Interrupt Request Register (bits 63:32). */
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| 95 | #define XAPIC_OFF_IRR1 0x210
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| 96 | /** Offset of Interrupt Request Register (bits 95:64). */
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| 97 | #define XAPIC_OFF_IRR2 0x220
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| 98 | /** Offset of Interrupt Request Register (bits 127:96). */
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| 99 | #define XAPIC_OFF_IRR3 0x230
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| 100 | /** Offset of Interrupt Request Register (bits 159:128). */
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| 101 | #define XAPIC_OFF_IRR4 0x240
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| 102 | /** Offset of Interrupt Request Register (bits 191:160). */
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| 103 | #define XAPIC_OFF_IRR5 0x250
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| 104 | /** Offset of Interrupt Request Register (bits 223:192). */
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| 105 | #define XAPIC_OFF_IRR6 0x260
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| 106 | /** Offset of Interrupt Request Register (bits 255:224). */
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| 107 | #define XAPIC_OFF_IRR7 0x270
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| 108 | /** Offset of Error Status Register. */
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| 109 | #define XAPIC_OFF_ESR 0x280
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| 110 | /** Offset of LVT CMCI Register. */
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| 111 | #define XAPIC_OFF_LVT_CMCI 0x2F0
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| 112 | /** Offset of Interrupt Command Register - Lo. */
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| 113 | #define XAPIC_OFF_ICR_LO 0x300
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| 114 | /** Offset of Interrupt Command Register - Hi. */
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| 115 | #define XAPIC_OFF_ICR_HI 0x310
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| 116 | /** Offset of LVT Timer Register. */
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| 117 | #define XAPIC_OFF_LVT_TIMER 0x320
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| 118 | /** Offset of LVT Thermal Sensor Register. */
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| 119 | #define XAPIC_OFF_LVT_THERMAL 0x330
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| 120 | /** Offset of LVT Performance Counter Register. */
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| 121 | #define XAPIC_OFF_LVT_PERF 0x340
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| 122 | /** Offset of LVT LINT0 Register. */
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| 123 | #define XAPIC_OFF_LVT_LINT0 0x350
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| 124 | /** Offset of LVT LINT1 Register. */
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| 125 | #define XAPIC_OFF_LVT_LINT1 0x360
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| 126 | /** Offset of LVT Error Register . */
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| 127 | #define XAPIC_OFF_LVT_ERROR 0x370
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| 128 | /** Offset of Timer Initial Count Register. */
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| 129 | #define XAPIC_OFF_TIMER_ICR 0x380
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| 130 | /** Offset of Timer Current Count Register. */
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| 131 | #define XAPIC_OFF_TIMER_CCR 0x390
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| 132 | /** Offset of Timer Divide Configuration Register. */
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| 133 | #define XAPIC_OFF_TIMER_DCR 0x3E0
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| 134 | /** Offset of Self-IPI Register (x2APIC only). */
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| 135 | #define X2APIC_OFF_SELF_IPI 0x3F0
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| 136 |
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| 137 | /** Offset of LVT range start. */
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| 138 | #define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
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| 139 | /** Offset of LVT range end (inclusive). */
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| 140 | #define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
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| 141 | /** Offset of LVT extended range start. */
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| 142 | #define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
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| 143 | /** Offset of LVT extended range end (inclusive). */
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| 144 | #define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
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| 145 | /** Offset of the last register (incl. reserved) in the xAPIC/x2APIC range. */
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| 146 | #define XAPIC_OFF_END 0x3F0
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| 147 |
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| 148 | /**
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| 149 | * xAPIC trigger mode.
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| 150 | */
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| 151 | typedef enum XAPICTRIGGERMODE
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| 152 | {
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| 153 | XAPICTRIGGERMODE_EDGE = 0,
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| 154 | XAPICTRIGGERMODE_LEVEL
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| 155 | } XAPICTRIGGERMODE;
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| 156 |
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| 157 | RT_C_DECLS_BEGIN
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| 158 |
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| 159 | #ifdef IN_RING3
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| 160 | /** @defgroup grp_apic_r3 The APIC Host Context Ring-3 API
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| 161 | * @{
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| 162 | */
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| 163 | VMMR3_INT_DECL(int) APICR3RegisterDevice(struct PDMDEVREGCB *pCallbacks);
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| 164 | VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu);
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| 165 | VMMR3_INT_DECL(void) APICR3HvEnable(PVM pVM);
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| 166 | /** @} */
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| 167 | #endif /* IN_RING3 */
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| 168 |
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| 169 | /* These functions are exported as they are called from external modules (recompiler). */
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| 170 | VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu);
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| 171 | VMMDECL(int) APICGetTpr(PVMCPU pVCpu, uint8_t *pu8Tpr, bool *pfPending, uint8_t *pu8PendingIntr);
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| 172 | VMMDECL(int) APICSetTpr(PVMCPU pVCpu, uint8_t u8Tpr);
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| 173 |
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| 174 | /* These functions are VMM internal. */
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| 175 | VMM_INT_DECL(bool) APICIsEnabled(PVMCPU pVCpu);
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| 176 | VMM_INT_DECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr);
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| 177 | VMM_INT_DECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr);
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| 178 | VMM_INT_DECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr);
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| 179 | VMM_INT_DECL(VBOXSTRICTRC) APICReadMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value);
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| 180 | VMM_INT_DECL(VBOXSTRICTRC) APICWriteMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value);
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| 181 | VMM_INT_DECL(int) APICGetTimerFreq(PVM pVM, uint64_t *pu64Value);
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| 182 | VMM_INT_DECL(VBOXSTRICTRC) APICLocalInterrupt(PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ);
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| 183 | VMM_INT_DECL(uint64_t) APICGetBaseMsrNoCheck(PVMCPU pVCpu);
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| 184 | VMM_INT_DECL(VBOXSTRICTRC) APICGetBaseMsr(PVMCPU pVCpu, uint64_t *pu64Value);
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| 185 | VMM_INT_DECL(int) APICSetBaseMsr(PVMCPU pVCpu, uint64_t u64BaseMsr);
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| 186 | VMM_INT_DECL(int) APICGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc);
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| 187 | VMM_INT_DECL(int) APICBusDeliver(PVM pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
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| 188 | uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc);
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| 189 | VMM_INT_DECL(int) APICGetApicPageForCpu(PVMCPU pVCpu, PRTHCPHYS pHCPhys, PRTR0PTR pR0Ptr, PRTR3PTR pR3Ptr,
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| 190 | PRTRCPTR pRCPtr);
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| 191 |
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| 192 | /** @name Hyper-V interface (Ring-3 and all-context API).
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| 193 | * @{ */
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| 194 | #ifdef IN_RING3
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| 195 | VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode);
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| 196 | #endif
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| 197 | VMM_INT_DECL(void) APICHvSendInterrupt(PVMCPU pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode);
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| 198 | VMM_INT_DECL(VBOXSTRICTRC) APICHvSetTpr(PVMCPU pVCpu, uint8_t uTpr);
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| 199 | VMM_INT_DECL(uint8_t) APICHvGetTpr(PVMCPU pVCpu);
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| 200 | VMM_INT_DECL(VBOXSTRICTRC) APICHvSetIcr(PVMCPU pVCpu, uint64_t uIcr);
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| 201 | VMM_INT_DECL(uint64_t) APICHvGetIcr(PVMCPU pVCpu);
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| 202 | VMM_INT_DECL(VBOXSTRICTRC) APICHvSetEoi(PVMCPU pVCpu, uint32_t uEoi);
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| 203 | /** @} */
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| 204 |
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| 205 | RT_C_DECLS_END
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| 206 |
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| 207 | /** @} */
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| 208 |
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| 209 | #endif
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| 210 |
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