apic.h@ 76558

Last change on this file since 76558 was 76558, checked in by vboxsync, 6 years ago
include/VBox: Use VBOX_INCLUDED_ rather than _vbox_ as header guard prefix, letting scm enforce this (thereby avoiding copy&paste errors like NativeEventQueue.h).
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1	/** @file
2	* APIC - Advanced Programmable Interrupt Controller.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_apic_h
27	#define VBOX_INCLUDED_vmm_apic_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	struct PDMDEVREGCB;
34
35	/** @defgroup grp_apic The local APIC VMM API
36	* @ingroup grp_vmm
37	* @{
38	*/
39
40	/** Offset of APIC ID Register. */
41	#define XAPIC_OFF_ID 0x020
42	/** Offset of APIC Version Register. */
43	#define XAPIC_OFF_VERSION 0x030
44	/** Offset of Task Priority Register. */
45	#define XAPIC_OFF_TPR 0x080
46	/** Offset of Arbitrartion Priority register. */
47	#define XAPIC_OFF_APR 0x090
48	/** Offset of Processor Priority register. */
49	#define XAPIC_OFF_PPR 0x0A0
50	/** Offset of End Of Interrupt register. */
51	#define XAPIC_OFF_EOI 0x0B0
52	/** Offset of Remote Read Register. */
53	#define XAPIC_OFF_RRD 0x0C0
54	/** Offset of Logical Destination Register. */
55	#define XAPIC_OFF_LDR 0x0D0
56	/** Offset of Destination Format Register. */
57	#define XAPIC_OFF_DFR 0x0E0
58	/** Offset of Spurious Interrupt Vector Register. */
59	#define XAPIC_OFF_SVR 0x0F0
60	/** Offset of In-service Register (bits 31:0). */
61	#define XAPIC_OFF_ISR0 0x100
62	/** Offset of In-service Register (bits 63:32). */
63	#define XAPIC_OFF_ISR1 0x110
64	/** Offset of In-service Register (bits 95:64). */
65	#define XAPIC_OFF_ISR2 0x120
66	/** Offset of In-service Register (bits 127:96). */
67	#define XAPIC_OFF_ISR3 0x130
68	/** Offset of In-service Register (bits 159:128). */
69	#define XAPIC_OFF_ISR4 0x140
70	/** Offset of In-service Register (bits 191:160). */
71	#define XAPIC_OFF_ISR5 0x150
72	/** Offset of In-service Register (bits 223:192). */
73	#define XAPIC_OFF_ISR6 0x160
74	/** Offset of In-service Register (bits 255:224). */
75	#define XAPIC_OFF_ISR7 0x170
76	/** Offset of Trigger Mode Register (bits 31:0). */
77	#define XAPIC_OFF_TMR0 0x180
78	/** Offset of Trigger Mode Register (bits 63:32). */
79	#define XAPIC_OFF_TMR1 0x190
80	/** Offset of Trigger Mode Register (bits 95:64). */
81	#define XAPIC_OFF_TMR2 0x1A0
82	/** Offset of Trigger Mode Register (bits 127:96). */
83	#define XAPIC_OFF_TMR3 0x1B0
84	/** Offset of Trigger Mode Register (bits 159:128). */
85	#define XAPIC_OFF_TMR4 0x1C0
86	/** Offset of Trigger Mode Register (bits 191:160). */
87	#define XAPIC_OFF_TMR5 0x1D0
88	/** Offset of Trigger Mode Register (bits 223:192). */
89	#define XAPIC_OFF_TMR6 0x1E0
90	/** Offset of Trigger Mode Register (bits 255:224). */
91	#define XAPIC_OFF_TMR7 0x1F0
92	/** Offset of Interrupt Request Register (bits 31:0). */
93	#define XAPIC_OFF_IRR0 0x200
94	/** Offset of Interrupt Request Register (bits 63:32). */
95	#define XAPIC_OFF_IRR1 0x210
96	/** Offset of Interrupt Request Register (bits 95:64). */
97	#define XAPIC_OFF_IRR2 0x220
98	/** Offset of Interrupt Request Register (bits 127:96). */
99	#define XAPIC_OFF_IRR3 0x230
100	/** Offset of Interrupt Request Register (bits 159:128). */
101	#define XAPIC_OFF_IRR4 0x240
102	/** Offset of Interrupt Request Register (bits 191:160). */
103	#define XAPIC_OFF_IRR5 0x250
104	/** Offset of Interrupt Request Register (bits 223:192). */
105	#define XAPIC_OFF_IRR6 0x260
106	/** Offset of Interrupt Request Register (bits 255:224). */
107	#define XAPIC_OFF_IRR7 0x270
108	/** Offset of Error Status Register. */
109	#define XAPIC_OFF_ESR 0x280
110	/** Offset of LVT CMCI Register. */
111	#define XAPIC_OFF_LVT_CMCI 0x2F0
112	/** Offset of Interrupt Command Register - Lo. */
113	#define XAPIC_OFF_ICR_LO 0x300
114	/** Offset of Interrupt Command Register - Hi. */
115	#define XAPIC_OFF_ICR_HI 0x310
116	/** Offset of LVT Timer Register. */
117	#define XAPIC_OFF_LVT_TIMER 0x320
118	/** Offset of LVT Thermal Sensor Register. */
119	#define XAPIC_OFF_LVT_THERMAL 0x330
120	/** Offset of LVT Performance Counter Register. */
121	#define XAPIC_OFF_LVT_PERF 0x340
122	/** Offset of LVT LINT0 Register. */
123	#define XAPIC_OFF_LVT_LINT0 0x350
124	/** Offset of LVT LINT1 Register. */
125	#define XAPIC_OFF_LVT_LINT1 0x360
126	/** Offset of LVT Error Register . */
127	#define XAPIC_OFF_LVT_ERROR 0x370
128	/** Offset of Timer Initial Count Register. */
129	#define XAPIC_OFF_TIMER_ICR 0x380
130	/** Offset of Timer Current Count Register. */
131	#define XAPIC_OFF_TIMER_CCR 0x390
132	/** Offset of Timer Divide Configuration Register. */
133	#define XAPIC_OFF_TIMER_DCR 0x3E0
134	/** Offset of Self-IPI Register (x2APIC only). */
135	#define X2APIC_OFF_SELF_IPI 0x3F0
136
137	/** Offset of LVT range start. */
138	#define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
139	/** Offset of LVT range end (inclusive). */
140	#define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
141	/** Offset of LVT extended range start. */
142	#define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
143	/** Offset of LVT extended range end (inclusive). */
144	#define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
145	/** Offset of the last register (incl. reserved) in the xAPIC/x2APIC range. */
146	#define XAPIC_OFF_END 0x3F0
147
148	/**
149	* xAPIC trigger mode.
150	*/
151	typedef enum XAPICTRIGGERMODE
152	{
153	XAPICTRIGGERMODE_EDGE = 0,
154	XAPICTRIGGERMODE_LEVEL
155	} XAPICTRIGGERMODE;
156
157	RT_C_DECLS_BEGIN
158
159	#ifdef IN_RING3
160	/** @defgroup grp_apic_r3 The APIC Host Context Ring-3 API
161	* @{
162	*/
163	VMMR3_INT_DECL(int) APICR3RegisterDevice(struct PDMDEVREGCB *pCallbacks);
164	VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu);
165	VMMR3_INT_DECL(void) APICR3HvEnable(PVM pVM);
166	/** @} */
167	#endif /* IN_RING3 */
168
169	/* These functions are exported as they are called from external modules (recompiler). */
170	VMMDECL(void) APICUpdatePendingInterrupts(PVMCPU pVCpu);
171	VMMDECL(int) APICGetTpr(PVMCPU pVCpu, uint8_t pu8Tpr, bool pfPending, uint8_t *pu8PendingIntr);
172	VMMDECL(int) APICSetTpr(PVMCPU pVCpu, uint8_t u8Tpr);
173
174	/* These functions are VMM internal. */
175	VMM_INT_DECL(bool) APICIsEnabled(PVMCPU pVCpu);
176	VMM_INT_DECL(bool) APICGetHighestPendingInterrupt(PVMCPU pVCpu, uint8_t *pu8PendingIntr);
177	VMM_INT_DECL(bool) APICQueueInterruptToService(PVMCPU pVCpu, uint8_t u8PendingIntr);
178	VMM_INT_DECL(void) APICDequeueInterruptFromService(PVMCPU pVCpu, uint8_t u8PendingIntr);
179	VMM_INT_DECL(VBOXSTRICTRC) APICReadMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value);
180	VMM_INT_DECL(VBOXSTRICTRC) APICWriteMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value);
181	VMM_INT_DECL(int) APICGetTimerFreq(PVM pVM, uint64_t *pu64Value);
182	VMM_INT_DECL(VBOXSTRICTRC) APICLocalInterrupt(PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ);
183	VMM_INT_DECL(uint64_t) APICGetBaseMsrNoCheck(PVMCPU pVCpu);
184	VMM_INT_DECL(VBOXSTRICTRC) APICGetBaseMsr(PVMCPU pVCpu, uint64_t *pu64Value);
185	VMM_INT_DECL(int) APICSetBaseMsr(PVMCPU pVCpu, uint64_t u64BaseMsr);
186	VMM_INT_DECL(int) APICGetInterrupt(PVMCPU pVCpu, uint8_t pu8Vector, uint32_t pu32TagSrc);
187	VMM_INT_DECL(int) APICBusDeliver(PVM pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
188	uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc);
189	VMM_INT_DECL(int) APICGetApicPageForCpu(PVMCPU pVCpu, PRTHCPHYS pHCPhys, PRTR0PTR pR0Ptr, PRTR3PTR pR3Ptr,
190	PRTRCPTR pRCPtr);
191
192	/** @name Hyper-V interface (Ring-3 and all-context API).
193	* @{ */
194	#ifdef IN_RING3
195	VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode);
196	#endif
197	VMM_INT_DECL(void) APICHvSendInterrupt(PVMCPU pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode);
198	VMM_INT_DECL(VBOXSTRICTRC) APICHvSetTpr(PVMCPU pVCpu, uint8_t uTpr);
199	VMM_INT_DECL(uint8_t) APICHvGetTpr(PVMCPU pVCpu);
200	VMM_INT_DECL(VBOXSTRICTRC) APICHvSetIcr(PVMCPU pVCpu, uint64_t uIcr);
201	VMM_INT_DECL(uint64_t) APICHvGetIcr(PVMCPU pVCpu);
202	VMM_INT_DECL(VBOXSTRICTRC) APICHvSetEoi(PVMCPU pVCpu, uint32_t uEoi);
203	/** @} */
204
205	RT_C_DECLS_END
206
207	/** @} */
208
209	#endif
210

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source: vbox/trunk/include/VBox/vmm/apic.h@ 76558

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