cpum-armv8.h@ 101121

Last change on this file since 101121 was 101121, checked in by vboxsync, 16 months ago
VMM/CPUM: Log host and guest features, bugref:10525
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_armv8_h
37	#define VBOX_INCLUDED_vmm_cpum_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <iprt/armv8.h>
44
45
46	RT_C_DECLS_BEGIN
47
48	/** @defgroup grp_cpum_armv8 The CPU Monitor / Manager API
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53
54	/**
55	* System register read functions.
56	*/
57	typedef enum CPUMSYSREGRDFN
58	{
59	/** Invalid zero value. */
60	kCpumSysRegRdFn_Invalid = 0,
61	/** Return the CPUMMSRRANGE::uValue. */
62	kCpumSysRegRdFn_FixedValue,
63	/** Alias to the system register range starting at the system register given by
64	* CPUMSYSREGRANGE::uValue. Must be used in pair with
65	* kCpumSysRegWrFn_Alias. */
66	kCpumSysRegRdFn_Alias,
67	/** Write only register, all read attempts cause an exception. */
68	kCpumSysRegRdFn_WriteOnly,
69
70	/** Read from a GICv3 PE ICC system register. */
71	kCpumSysRegRdFn_GicV3Icc,
72	/** Read from the OSLSR_EL1 syste register. */
73	kCpumSysRegRdFn_OslsrEl1,
74
75	/** End of valid system register read function indexes. */
76	kCpumSysRegRdFn_End
77	} CPUMSYSREGRDFN;
78
79
80	/**
81	* System register write functions.
82	*/
83	typedef enum CPUMSYSREGWRFN
84	{
85	/** Invalid zero value. */
86	kCpumSysRegWrFn_Invalid = 0,
87	/** Writes are ignored. */
88	kCpumSysRegWrFn_IgnoreWrite,
89	/** Writes cause an exception. */
90	kCpumSysRegWrFn_ReadOnly,
91	/** Alias to the system register range starting at the system register given by
92	* CPUMSYSREGRANGE::uValue. Must be used in pair with
93	* kCpumSysRegRdFn_Alias. */
94	kCpumSysRegWrFn_Alias,
95
96	/** Write to a GICv3 PE ICC system register. */
97	kCpumSysRegWrFn_GicV3Icc,
98	/** Write to the OSLAR_EL1 syste register. */
99	kCpumSysRegWrFn_OslarEl1,
100
101	/** End of valid system register write function indexes. */
102	kCpumSysRegWrFn_End
103	} CPUMSYSREGWRFN;
104
105
106	/**
107	* System register range.
108	*
109	* @note This is very similar to how x86/amd64 MSRs are handled.
110	*/
111	typedef struct CPUMSYSREGRANGE
112	{
113	/** The first system register. [0] */
114	uint16_t uFirst;
115	/** The last system register. [2] */
116	uint16_t uLast;
117	/** The read function (CPUMMSRRDFN). [4] */
118	uint16_t enmRdFn;
119	/** The write function (CPUMMSRWRFN). [6] */
120	uint16_t enmWrFn;
121	/** The offset of the 64-bit system register value relative to the start of CPUMCPU.
122	* UINT16_MAX if not used by the read and write functions. [8] */
123	uint32_t offCpumCpu : 24;
124	/** Reserved for future hacks. [11] */
125	uint32_t fReserved : 8;
126	/** Padding/Reserved. [12] */
127	uint32_t u32Padding;
128	/** The init/read value. [16]
129	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
130	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
131	* offset into CPUM. */
132	uint64_t uValue;
133	/** The bits to ignore when writing. [24] */
134	uint64_t fWrIgnMask;
135	/** The bits that will cause an exception when writing. [32]
136	* This is always checked prior to calling the write function. Using
137	* UINT64_MAX effectively marks the MSR as read-only. */
138	uint64_t fWrExcpMask;
139	/** The register name, if applicable. [32] */
140	char szName[56];
141
142	/** The number of reads. */
143	STAMCOUNTER cReads;
144	/** The number of writes. */
145	STAMCOUNTER cWrites;
146	/** The number of times ignored bits were written. */
147	STAMCOUNTER cIgnoredBits;
148	/** The number of exceptions generated. */
149	STAMCOUNTER cExcp;
150	} CPUMSYSREGRANGE;
151	#ifndef VBOX_FOR_DTRACE_LIB
152	AssertCompileSize(CPUMSYSREGRANGE, 128);
153	#endif
154	/** Pointer to an system register range. */
155	typedef CPUMSYSREGRANGE *PCPUMSYSREGRANGE;
156	/** Pointer to a const system register range. */
157	typedef CPUMSYSREGRANGE const *PCCPUMSYSREGRANGE;
158
159
160	/**
161	* CPU features and quirks.
162	* This is mostly exploded CPUID info.
163	*/
164	typedef struct CPUMFEATURES
165	{
166	/** The CPU vendor (CPUMCPUVENDOR). */
167	uint8_t enmCpuVendor;
168	/** The CPU family. */
169	uint8_t uFamily;
170	/** The CPU model. */
171	uint8_t uModel;
172	/** The CPU stepping. */
173	uint8_t uStepping;
174	/** The microarchitecture. */
175	#ifndef VBOX_FOR_DTRACE_LIB
176	CPUMMICROARCH enmMicroarch;
177	#else
178	uint32_t enmMicroarch;
179	#endif
180	/** The maximum physical address width of the CPU. */
181	uint8_t cMaxPhysAddrWidth;
182	/** The maximum linear address width of the CPU. */
183	uint8_t cMaxLinearAddrWidth;
184
185	/** @name Granule sizes supported.
186	* @{ */
187	/** 4KiB translation granule size supported. */
188	uint32_t fTGran4K : 1;
189	/** 16KiB translation granule size supported. */
190	uint32_t fTGran16K : 1;
191	/** 64KiB translation granule size supported. */
192	uint32_t fTGran64K : 1;
193	/** @} */
194
195	/** @name pre-2020 Architecture Extensions.
196	* @{ */
197	/** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */
198	uint32_t fAdvSimd : 1;
199	/** Supports Advanced SIMD AES instructions (FEAT_AES). */
200	uint32_t fAes : 1;
201	/** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */
202	uint32_t fPmull : 1;
203	/** Supports CP15Disable2 (FEAT_CP15DISABLE2). */
204	uint32_t fCp15Disable2 : 1;
205	/** Supports Cache Speculation Variant 2 (FEAT_CSV2). */
206	uint32_t fCsv2 : 1;
207	/** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */
208	uint32_t fCsv21p1 : 1;
209	/** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */
210	uint32_t fCsv21p2 : 1;
211	/** Supports Cache Speculation Variant 3 (FEAT_CSV3). */
212	uint32_t fCsv3 : 1;
213	/** Supports Data Gahtering Hint (FEAT_DGH). */
214	uint32_t fDgh : 1;
215	/** Supports Double Lock (FEAT_DoubleLock). */
216	uint32_t fDoubleLock : 1;
217	/** Supports Enhanced Translation Synchronization (FEAT_ETS2). */
218	uint32_t fEts2 : 1;
219	/** Supports Floating Point Extensions (FEAT_FP). */
220	uint32_t fFp : 1;
221	/** Supports IVIPT Extensions (FEAT_IVIPT). */
222	uint32_t fIvipt : 1;
223	/** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */
224	uint32_t fPcsrV8 : 1;
225	/** Supports Speculation Restrictions instructions (FEAT_SPECRES). */
226	uint32_t fSpecres : 1;
227	/** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */
228	uint32_t fRas : 1;
229	/** Supports Speculation Barrier (FEAT_SB). */
230	uint32_t fSb : 1;
231	/** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */
232	uint32_t fSha1 : 1;
233	/** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */
234	uint32_t fSha256 : 1;
235	/** Supports Speculation Store Bypass Safe (FEAT_SSBS). */
236	uint32_t fSsbs : 1;
237	/** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */
238	uint32_t fSsbs2 : 1;
239	/** Supports CRC32 instructions (FEAT_CRC32). */
240	uint32_t fCrc32 : 1;
241	/** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */
242	uint32_t fNTlbpa : 1;
243	/** Supports debug with VHE (FEAT_Debugv8p1). */
244	uint32_t fDebugV8p1 : 1;
245	/** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */
246	uint32_t fHpds : 1;
247	/** Supports Limited ordering regions (FEAT_LOR). */
248	uint32_t fLor : 1;
249	/** Supports Lare Systems Extensons (FEAT_LSE). */
250	uint32_t fLse : 1;
251	/** Supports Privileged access never (FEAT_PAN). */
252	uint32_t fPan : 1;
253	/** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */
254	uint32_t fPmuV3p1 : 1;
255	/** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */
256	uint32_t fRdm : 1;
257	/** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */
258	uint32_t fHafdbs : 1;
259	/** Supports Virtualization Host Extensions (FEAT_VHE). */
260	uint32_t fVhe : 1;
261	/** Supports 16-bit VMID (FEAT_VMID16). */
262	uint32_t fVmid16 : 1;
263	/** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */
264	uint32_t fAa32Bf16 : 1;
265	/** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */
266	uint32_t fAa32Hpd : 1;
267	/** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */
268	uint32_t fAa32I8mm : 1;
269	/** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */
270	uint32_t fPan2 : 1;
271	/** Supports AArch64 BFloat16 instructions (FEAT_BF16). */
272	uint32_t fBf16 : 1;
273	/** Supports DC CVADP instruction (FEAT_DPB2). */
274	uint32_t fDpb2 : 1;
275	/** Supports DC VAP instruction (FEAT_DPB). */
276	uint32_t fDpb : 1;
277	/** Supports Debug v8.2 (FEAT_Debugv8p2). */
278	uint32_t fDebugV8p2 : 1;
279	/** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */
280	uint32_t fDotProd : 1;
281	/** Supports Enhanced Virtualization Traps (FEAT_EVT). */
282	uint32_t fEvt : 1;
283	/** Supports Single precision Matrix Multiplication (FEAT_F32MM). */
284	uint32_t fF32mm : 1;
285	/** Supports Double precision Matrix Multiplication (FEAT_F64MM). */
286	uint32_t fF64mm : 1;
287	/** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */
288	uint32_t fFhm : 1;
289	/** Supports Half-precision floating point data processing (FEAT_FP16). */
290	uint32_t fFp16 : 1;
291	/** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */
292	uint32_t fI8mm : 1;
293	/** Supports Implicit Error Synchronization event (FEAT_IESB). */
294	uint32_t fIesb : 1;
295	/** Supports Large PA and IPA support (FEAT_LPA). */
296	uint32_t fLpa : 1;
297	/** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */
298	uint32_t fLsmaoc : 1;
299	/** Supports Large VA support (FEAT_LVA). */
300	uint32_t fLva : 1;
301	/** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */
302	uint32_t fMpam : 1;
303	/** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */
304	uint32_t fPcsrV8p2 : 1;
305	/** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */
306	uint32_t fSha3 : 1;
307	/** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */
308	uint32_t fSha512 : 1;
309	/** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */
310	uint32_t fSm3 : 1;
311	/** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */
312	uint32_t fSm4 : 1;
313	/** Supports Statistical Profiling Extension (FEAT_SPE). */
314	uint32_t fSpe : 1;
315	/** Supports Scalable Vector Extension (FEAT_SVE). */
316	uint32_t fSve : 1;
317	/** Supports Translation Table Common not private translations (FEAT_TTCNP). */
318	uint32_t fTtcnp : 1;
319	/** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */
320	uint32_t fHpds2 : 1;
321	/** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */
322	uint32_t fXnx : 1;
323	/** Supports Unprivileged Access Override control (FEAT_UAO). */
324	uint32_t fUao : 1;
325	/** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */
326	uint32_t fVpipt : 1;
327	/** Supports Extended cache index (FEAT_CCIDX). */
328	uint32_t fCcidx : 1;
329	/** Supports Floating-point complex number instructions (FEAT_FCMA). */
330	uint32_t fFcma : 1;
331	/** Supports Debug over Powerdown (FEAT_DoPD). */
332	uint32_t fDopd : 1;
333	/** Supports Enhanced pointer authentication (FEAT_EPAC). */
334	uint32_t fEpac : 1;
335	/** Supports Faulting on AUT* instructions (FEAT_FPAC). */
336	uint32_t fFpac : 1;
337	/** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */
338	uint32_t fFpacCombine : 1;
339	/** Supports JavaScript conversion instructions (FEAT_JSCVT). */
340	uint32_t fJscvt : 1;
341	/** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */
342	uint32_t fLrcpc : 1;
343	/** Supports Nexted Virtualization (FEAT_NV). */
344	uint32_t fNv : 1;
345	/** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */
346	uint32_t fPacQarma5 : 1;
347	/** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */
348	uint32_t fPacImp : 1;
349	/** Supports Pointer authentication (FEAT_PAuth). */
350	uint32_t fPAuth : 1;
351	/** Supports Enhancements to pointer authentication (FEAT_PAuth2). */
352	uint32_t fPAuth2 : 1;
353	/** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */
354	uint32_t fSpeV1p1 : 1;
355	/** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */
356	uint32_t fAmuV1 : 1;
357	/** Supports Generic Counter Scaling (FEAT_CNTSC). */
358	uint32_t fCntsc : 1;
359	/** Supports Debug v8.4 (FEAT_Debugv8p4). */
360	uint32_t fDebugV8p4 : 1;
361	/** Supports Double Fault Extension (FEAT_DoubleFault). */
362	uint32_t fDoubleFault : 1;
363	/** Supports Data Independent Timing instructions (FEAT_DIT). */
364	uint32_t fDit : 1;
365	/** Supports Condition flag manipulation isntructions (FEAT_FlagM). */
366	uint32_t fFlagM : 1;
367	/** Supports ID space trap handling (FEAT_IDST). */
368	uint32_t fIdst : 1;
369	/** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */
370	uint32_t fLrcpc2 : 1;
371	/** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */
372	uint32_t fLse2 : 1;
373	/** Supports Enhanced nested virtualization support (FEAT_NV2). */
374	uint32_t fNv2 : 1;
375	/** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */
376	uint32_t fPmuV3p4 : 1;
377	/** Supports RAS Extension v1.1 (FEAT_RASv1p1). */
378	uint32_t fRasV1p1 : 1;
379	/** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */
380	uint32_t fRassaV1p1 : 1;
381	/** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */
382	uint32_t fS2Fwb : 1;
383	/** Supports Secure El2 (FEAT_SEL2). */
384	uint32_t fSecEl2 : 1;
385	/** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */
386	uint32_t fTlbios : 1;
387	/** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */
388	uint32_t fTlbirange : 1;
389	/** Supports Self-hosted Trace Extensions (FEAT_TRF). */
390	uint32_t fTrf : 1;
391	/** Supports Translation Table Level (FEAT_TTL). */
392	uint32_t fTtl : 1;
393	/** Supports Translation table break-before-make levels (FEAT_BBM). */
394	uint32_t fBbm : 1;
395	/** Supports Small translation tables (FEAT_TTST). */
396	uint32_t fTtst : 1;
397	/** Supports Branch Target Identification (FEAT_BTI). */
398	uint32_t fBti : 1;
399	/** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */
400	uint32_t fFlagM2 : 1;
401	/** Supports Context synchronization and exception handling (FEAT_ExS). */
402	uint32_t fExs : 1;
403	/** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */
404	uint32_t fE0Pd : 1;
405	/** Supports Floating-point to integer instructions (FEAT_FRINTTS). */
406	uint32_t fFrintts : 1;
407	/** Supports Guest translation granule size (FEAT_GTG). */
408	uint32_t fGtg : 1;
409	/** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */
410	uint32_t fMte : 1;
411	/** Supports memory Tagging Extension version 2 (FEAT_MTE2). */
412	uint32_t fMte2 : 1;
413	/** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */
414	uint32_t fPmuV3p5 : 1;
415	/** Supports Random number generator (FEAT_RNG). */
416	uint32_t fRng : 1;
417	/** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */
418	uint32_t fAmuV1p1 : 1;
419	/** Supports Enhanced Counter Virtualization (FEAT_ECV). */
420	uint32_t fEcv : 1;
421	/** Supports Fine Grain Traps (FEAT_FGT). */
422	uint32_t fFgt : 1;
423	/** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */
424	uint32_t fMpamV0p1 : 1;
425	/** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */
426	uint32_t fMpamV1p1 : 1;
427	/** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */
428	uint32_t fMtPmu : 1;
429	/** Supports Delayed Trapping of WFE (FEAT_TWED). */
430	uint32_t fTwed : 1;
431	/** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */
432	uint32_t fEtmV4 : 1;
433	/** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */
434	uint32_t fEtmV4p1 : 1;
435	/** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */
436	uint32_t fEtmV4p2 : 1;
437	/** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */
438	uint32_t fEtmV4p3 : 1;
439	/** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */
440	uint32_t fEtmV4p4 : 1;
441	/** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */
442	uint32_t fEtmV4p5 : 1;
443	/** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */
444	uint32_t fEtmV4p6 : 1;
445	/** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */
446	uint32_t fGicV3 : 1;
447	/** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */
448	uint32_t fGicV3p1 : 1;
449	/** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */
450	uint32_t fGicV3Tdir : 1;
451	/** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */
452	uint32_t fGicV4 : 1;
453	/** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */
454	uint32_t fGicV4p1 : 1;
455	/** Supports PMU extension, version 3 (FEAT_PMUv3). */
456	uint32_t fPmuV3 : 1;
457	/** Supports Embedded Trace Extension (FEAT_ETE). */
458	uint32_t fEte : 1;
459	/** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */
460	uint32_t fEteV1p1 : 1;
461	/** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */
462	uint32_t fEteV1p2 : 1;
463	/** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */
464	uint32_t fSve2 : 1;
465	/** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */
466	uint32_t fSveAes : 1;
467	/** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */
468	uint32_t fSvePmull128 : 1;
469	/** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */
470	uint32_t fSveBitPerm : 1;
471	/** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */
472	uint32_t fSveSha3 : 1;
473	/** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */
474	uint32_t fSveSm4 : 1;
475	/** Supports Transactional Memory Extension (FEAT_TME). */
476	uint32_t fTme : 1;
477	/** Supports Trace Buffer Extension (FEAT_TRBE). */
478	uint32_t fTrbe : 1;
479	/** Supports Scalable Matrix Extension (FEAT_SME). */
480	uint32_t fSme : 1;
481	/** @} */
482
483	/** @name 2020 Architecture Extensions.
484	* @{ */
485	/** Supports Alternate floating-point behavior (FEAT_AFP). */
486	uint32_t fAfp : 1;
487	/** Supports HCRX_EL2 register (FEAT_HCX). */
488	uint32_t fHcx : 1;
489	/** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */
490	uint32_t fLpa2 : 1;
491	/** Supports 64 byte loads and stores without return (FEAT_LS64). */
492	uint32_t fLs64 : 1;
493	/** Supports 64 byte stores with return (FEAT_LS64_V). */
494	uint32_t fLs64V : 1;
495	/** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */
496	uint32_t fLs64Accdata : 1;
497	/** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */
498	uint32_t fMte3 : 1;
499	/** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */
500	uint32_t fPan3 : 1;
501	/** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */
502	uint32_t fPmuV3p7 : 1;
503	/** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */
504	uint32_t fRpres : 1;
505	/** Supports Realm Management Extension (FEAT_RME). */
506	uint32_t fRme : 1;
507	/** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */
508	uint32_t fSmeFA64 : 1;
509	/** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */
510	uint32_t fSmeF64F64 : 1;
511	/** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */
512	uint32_t fSmeI16I64 : 1;
513	/** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */
514	uint32_t fSpeV1p2 : 1;
515	/** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */
516	uint32_t fEbf16 : 1;
517	/** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */
518	uint32_t fWfxt : 1;
519	/** Supports XS attribute (FEAT_XS). */
520	uint32_t fXs : 1;
521	/** Supports branch Record Buffer Extension (FEAT_BRBE). */
522	uint32_t fBrbe : 1;
523	/** @} */
524
525	/** @name 2021 Architecture Extensions.
526	* @{ */
527	/** Supports Control for cache maintenance permission (FEAT_CMOW). */
528	uint32_t fCmow : 1;
529	/** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */
530	uint32_t fConstPacField : 1;
531	/** Supports Debug v8.8 (FEAT_Debugv8p8). */
532	uint32_t fDebugV8p8 : 1;
533	/** Supports Hinted conditional branches (FEAT_HBC). */
534	uint32_t fHbc : 1;
535	/** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */
536	uint32_t fHpmn0 : 1;
537	/** Supports Non-Maskable Interrupts (FEAT_NMI). */
538	uint32_t fNmi : 1;
539	/** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */
540	uint32_t fGicV3Nmi : 1;
541	/** Supports Standardization of memory operations (FEAT_MOPS). */
542	uint32_t fMops : 1;
543	/** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */
544	uint32_t fPacQarma3 : 1;
545	/** Supports Event counting threshold (FEAT_PMUv3_TH). */
546	uint32_t fPmuV3Th : 1;
547	/** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */
548	uint32_t fPmuV3p8 : 1;
549	/** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */
550	uint32_t fPmuV3Ext64 : 1;
551	/** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */
552	uint32_t fPmuV3Ext32 : 1;
553	/** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */
554	uint32_t fPmuV3Ext : 1;
555	/** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */
556	uint32_t fRngTrap : 1;
557	/** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */
558	uint32_t fSpeV1p3 : 1;
559	/** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */
560	uint32_t fTidcp1 : 1;
561	/** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */
562	uint32_t fBrbeV1p1 : 1;
563	/** @} */
564
565	/** @name 2022 Architecture Extensions.
566	* @{ */
567	/** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */
568	uint32_t fAble : 1;
569	/** Supports Asynchronous Device error exceptions (FEAT_ADERR). */
570	uint32_t fAderr : 1;
571	/** Supports Memory Attribute Index Enhancement (FEAT_AIE). */
572	uint32_t fAie : 1;
573	/** Supports Asynchronous Normal error exception (FEAT_ANERR). */
574	uint32_t fAnerr : 1;
575	/** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */
576	uint32_t fBwe : 1;
577	/** Supports Clear Branch History instruction (FEAT_CLRBHB). */
578	uint32_t fClrBhb : 1;
579	/** Supports Check Feature Status (FEAT_CHK). */
580	uint32_t fChk : 1;
581	/** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */
582	uint32_t fCssc : 1;
583	/** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */
584	uint32_t fCsv2v3 : 1;
585	/** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */
586	uint32_t fD128 : 1;
587	/** Supports Debug v8.9 (FEAT_Debugv8p9). */
588	uint32_t fDebugV8p9 : 1;
589	/** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */
590	uint32_t fDoubleFault2 : 1;
591	/** Supports Exception based Event Profiling (FEAT_EBEP). */
592	uint32_t fEbep : 1;
593	/** Supports Exploitative control using branch history information (FEAT_ECBHB). */
594	uint32_t fEcBhb : 1;
595	/** Supports for EDHSR (FEAT_EDHSR). */
596	uint32_t fEdhsr : 1;
597	/** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */
598	uint32_t fEteV1p3 : 1;
599	/** Supports Fine-grained traps 2 (FEAT_FGT2). */
600	uint32_t fFgt2 : 1;
601	/** Supports Guarded Control Stack Extension (FEAT_GCS). */
602	uint32_t fGcs : 1;
603	/** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */
604	uint32_t fHaft : 1;
605	/** Supports Instrumentation Extension (FEAT_ITE). */
606	uint32_t fIte : 1;
607	/** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */
608	uint32_t fLrcpc3 : 1;
609	/** Supports 128-bit atomics (FEAT_LSE128). */
610	uint32_t fLse128 : 1;
611	/** Supports 56-bit VA (FEAT_LVA3). */
612	uint32_t fLva3 : 1;
613	/** Supports Memory Encryption Contexts (FEAT_MEC). */
614	uint32_t fMec : 1;
615	/** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */
616	uint32_t fMte4 : 1;
617	/** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */
618	uint32_t fMteCanonicalTags : 1;
619	/** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */
620	uint32_t fMteTaggedFar : 1;
621	/** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */
622	uint32_t fMteStoreOnly : 1;
623	/** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */
624	uint32_t fMteNoAddressTags : 1;
625	/** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */
626	uint32_t fMteAsymFault : 1;
627	/** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */
628	uint32_t fMteAsync : 1;
629	/** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */
630	uint32_t fMtePermS1 : 1;
631	/** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */
632	uint32_t fPcsrV8p9 : 1;
633	/** Supports Permission model enhancements (FEAT_S1PIE). */
634	uint32_t fS1Pie : 1;
635	/** Supports Permission model enhancements (FEAT_S2PIE). */
636	uint32_t fS2Pie : 1;
637	/** Supports Permission model enhancements (FEAT_S1POE). */
638	uint32_t fS1Poe : 1;
639	/** Supports Permission model enhancements (FEAT_S2POE). */
640	uint32_t fS2Poe : 1;
641	/** Supports Physical Fault Address Registers (FEAT_PFAR). */
642	uint32_t fPfar : 1;
643	/** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */
644	uint32_t fPmuV3p9 : 1;
645	/** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */
646	uint32_t fPmuV3Edge : 1;
647	/** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */
648	uint32_t fPmuV3Icntr : 1;
649	/** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */
650	uint32_t fPmuV3Ss : 1;
651	/** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */
652	uint32_t fPrfmSlc : 1;
653	/** Supports RAS version 2 (FEAT_RASv2). */
654	uint32_t fRasV2 : 1;
655	/** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */
656	uint32_t fRasSaV2 : 1;
657	/** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */
658	uint32_t fRprfm : 1;
659	/** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */
660	uint32_t fSctlr2 : 1;
661	/** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */
662	uint32_t fSebep : 1;
663	/** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */
664	uint32_t fSmeF16F16 : 1;
665	/** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */
666	uint32_t fSme2 : 1;
667	/** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */
668	uint32_t fSme2p1 : 1;
669	/** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */
670	uint32_t fSpecres2 : 1;
671	/** Supports System Performance Monitors Extension (FEAT_SPMU). */
672	uint32_t fSpmu : 1;
673	/** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */
674	uint32_t fSpeV1p4 : 1;
675	/** Supports Call Return Branch Records (FEAT_SPE_CRR). */
676	uint32_t fSpeCrr : 1;
677	/** Supports Data Source Filtering (FEAT_SPE_FDS). */
678	uint32_t fSpeFds : 1;
679	/** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */
680	uint32_t fSve2p1 : 1;
681	/** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */
682	uint32_t fSveB16B16 : 1;
683	/** Supports 128-bit System instructions (FEAT_SYSINSTR128). */
684	uint32_t fSysInstr128 : 1;
685	/** Supports 128-bit System registers (FEAT_SYSREG128). */
686	uint32_t fSysReg128 : 1;
687	/** Supports Extension to TCR_ELx (FEAT_TCR2). */
688	uint32_t fTcr2 : 1;
689	/** Supports Translation Hardening Extension (FEAT_THE). */
690	uint32_t fThe : 1;
691	/** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */
692	uint32_t fTrbeExt : 1;
693	/** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */
694	uint32_t fTrbeMpam : 1;
695	/** @} */
696
697	/** Padding to the required size to match CPUMFEATURES for x86/amd64. */
698	uint8_t abPadding[6];
699	} CPUMFEATURES;
700	#ifndef VBOX_FOR_DTRACE_LIB
701	AssertCompileSize(CPUMFEATURES, 48);
702	#endif
703	/** Pointer to a CPU feature structure. */
704	typedef CPUMFEATURES *PCPUMFEATURES;
705	/** Pointer to a const CPU feature structure. */
706	typedef CPUMFEATURES const *PCCPUMFEATURES;
707
708	/**
709	* Chameleon wrapper structure for the host CPU features.
710	*
711	* This is used for the globally readable g_CpumHostFeatures variable, which is
712	* initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
713	* ring-3. To reflect this immutability after load/init, we use this wrapper
714	* structure to switch it between const and non-const depending on the context.
715	* Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
716	*/
717	typedef struct CPUHOSTFEATURES
718	{
719	CPUMFEATURES
720	#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
721	const
722	#endif
723	s;
724	} CPUHOSTFEATURES;
725	/** Pointer to a const host CPU feature structure. */
726	typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
727
728	/** Host CPU features.
729	* @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
730	* module init. */
731	extern CPUHOSTFEATURES g_CpumHostFeatures;
732
733
734	/**
735	* CPU database entry.
736	*/
737	typedef struct CPUMDBENTRY
738	{
739	/** The CPU name. */
740	const char *pszName;
741	/** The full CPU name. */
742	const char *pszFullName;
743	/** The CPU vendor (CPUMCPUVENDOR). */
744	uint8_t enmVendor;
745	/** The CPU family. */
746	uint8_t uFamily;
747	/** The CPU model. */
748	uint8_t uModel;
749	/** The CPU stepping. */
750	uint8_t uStepping;
751	/** The microarchitecture. */
752	CPUMMICROARCH enmMicroarch;
753	/** Scalable bus frequency used for reporting other frequencies. */
754	uint64_t uScalableBusFreq;
755	/** Flags - CPUMDB_F_XXX. */
756	uint32_t fFlags;
757	/** The maximum physical address with of the CPU. This should correspond to
758	* the value in CPUID leaf 0x80000008 when present. */
759	uint8_t cMaxPhysAddrWidth;
760	} CPUMDBENTRY;
761	/** Pointer to a const CPU database entry. */
762	typedef CPUMDBENTRY const *PCCPUMDBENTRY;
763
764
765	/**
766	* CPU ID registers.
767	*/
768	typedef struct CPUMIDREGS
769	{
770	/** Content of the ID_AA64PFR0_EL1 register. */
771	uint64_t u64RegIdAa64Pfr0El1;
772	/** Content of the ID_AA64PFR1_EL1 register. */
773	uint64_t u64RegIdAa64Pfr1El1;
774	/** Content of the ID_AA64DFR0_EL1 register. */
775	uint64_t u64RegIdAa64Dfr0El1;
776	/** Content of the ID_AA64DFR1_EL1 register. */
777	uint64_t u64RegIdAa64Dfr1El1;
778	/** Content of the ID_AA64AFR0_EL1 register. */
779	uint64_t u64RegIdAa64Afr0El1;
780	/** Content of the ID_AA64AFR1_EL1 register. */
781	uint64_t u64RegIdAa64Afr1El1;
782	/** Content of the ID_AA64ISAR0_EL1 register. */
783	uint64_t u64RegIdAa64Isar0El1;
784	/** Content of the ID_AA64ISAR1_EL1 register. */
785	uint64_t u64RegIdAa64Isar1El1;
786	/** Content of the ID_AA64ISAR2_EL1 register. */
787	uint64_t u64RegIdAa64Isar2El1;
788	/** Content of the ID_AA64MMFR0_EL1 register. */
789	uint64_t u64RegIdAa64Mmfr0El1;
790	/** Content of the ID_AA64MMFR1_EL1 register. */
791	uint64_t u64RegIdAa64Mmfr1El1;
792	/** Content of the ID_AA64MMFR2_EL1 register. */
793	uint64_t u64RegIdAa64Mmfr2El1;
794	/** Content of the CLIDR_EL1 register. */
795	uint64_t u64RegClidrEl1;
796	/** Content of the CTR_EL0 register. */
797	uint64_t u64RegCtrEl0;
798	/** Content of the DCZID_EL0 register. */
799	uint64_t u64RegDczidEl0;
800	} CPUMIDREGS;
801	/** Pointer to CPU ID registers. */
802	typedef CPUMIDREGS *PCPUMIDREGS;
803	/** Pointer to a const CPU ID registers structure. */
804	typedef CPUMIDREGS const *PCCPUMIDREGS;
805
806
807	/** @name Changed flags.
808	* These flags are used to keep track of which important register that
809	* have been changed since last they were reset. The only one allowed
810	* to clear them is REM!
811	*
812	* @todo This is obsolete, but remains as it will be refactored for coordinating
813	* IEM and NEM/HM later. Probably.
814	* @{
815	*/
816	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(0)
817	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_GLOBAL_TLB_FLUSH )
818	/** @} */
819
820
821	#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) \|\| defined(DOXYGEN_RUNNING)
822	/** @name Inlined Guest Getters and predicates Functions.
823	* @{ */
824
825	/**
826	* Tests if the guest is running in 64 bits mode or not.
827	*
828	* @returns true if in 64 bits mode, otherwise false.
829	* @param pCtx Current CPU context.
830	*/
831	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
832	{
833	return !RT_BOOL(pCtx->fPState & ARMV8_SPSR_EL2_AARCH64_M4);
834	}
835
836	/** @} */
837	#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS \|\| DOXYGEN_RUNNING */
838
839
840	#ifndef VBOX_FOR_DTRACE_LIB
841
842	#ifdef IN_RING3
843	/** @defgroup grp_cpum_armv8_r3 The CPUM ARMv8 ring-3 API
844	* @{
845	*/
846
847	VMMR3DECL(int) CPUMR3SysRegRangesInsert(PVM pVM, PCCPUMSYSREGRANGE pNewRange);
848	VMMR3DECL(int) CPUMR3PopulateFeaturesByIdRegisters(PVM pVM, PCCPUMIDREGS pIdRegs);
849
850	VMMR3_INT_DECL(int) CPUMR3QueryGuestIdRegs(PVM pVM, PCCPUMIDREGS *ppIdRegs);
851
852	/** @} */
853	#endif /* IN_RING3 */
854
855
856	/** @name Guest Register Getters.
857	* @{ */
858	VMMDECL(bool) CPUMGetGuestIrqMasked(PVMCPUCC pVCpu);
859	VMMDECL(bool) CPUMGetGuestFiqMasked(PVMCPUCC pVCpu);
860	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t *puValue);
861	/** @} */
862
863
864	/** @name Guest Register Setters.
865	* @{ */
866	VMMDECL(VBOXSTRICTRC) CPUMSetGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t uValue);
867	/** @} */
868
869	#endif
870
871	/** @} */
872	RT_C_DECLS_END
873
874
875	#endif /* !VBOX_INCLUDED_vmm_cpum_armv8_h */
876

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source: vbox/trunk/include/VBox/vmm/cpum-armv8.h@ 101121

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