cpum-armv8.h@ 107031

Last change on this file since 107031 was 107031, checked in by vboxsync, 3 months ago
VMM/CPUM-armv8: Allow reading/writing the debug control/value registers through CPUMQueryGuestSysReg/CPUMSetGuestSysReg, bugreef:10393
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File size: 36.8 KB

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_armv8_h
37	#define VBOX_INCLUDED_vmm_cpum_armv8_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <iprt/armv8.h>
44
45
46	RT_C_DECLS_BEGIN
47
48	/** @defgroup grp_cpum_armv8 The CPU Monitor / Manager API
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53
54	/**
55	* System register read functions.
56	*/
57	typedef enum CPUMSYSREGRDFN
58	{
59	/** Invalid zero value. */
60	kCpumSysRegRdFn_Invalid = 0,
61	/** Return the CPUMMSRRANGE::uValue. */
62	kCpumSysRegRdFn_FixedValue,
63	/** Alias to the system register range starting at the system register given by
64	* CPUMSYSREGRANGE::uValue. Must be used in pair with
65	* kCpumSysRegWrFn_Alias. */
66	kCpumSysRegRdFn_Alias,
67	/** Write only register, all read attempts cause an exception. */
68	kCpumSysRegRdFn_WriteOnly,
69	/** Read the value from the given offset from the beginning of CPUMGSTCTX. */
70	kCpumSysRegRdFn_ReadCpumOff,
71
72	/** Read from a GICv3 PE ICC system register. */
73	kCpumSysRegRdFn_GicV3Icc,
74	/** Read from the OSLSR_EL1 syste register. */
75	kCpumSysRegRdFn_OslsrEl1,
76	/** Read from a PMU system register. */
77	kCpumSysRegRdFn_Pmu,
78
79	/** End of valid system register read function indexes. */
80	kCpumSysRegRdFn_End
81	} CPUMSYSREGRDFN;
82
83
84	/**
85	* System register write functions.
86	*/
87	typedef enum CPUMSYSREGWRFN
88	{
89	/** Invalid zero value. */
90	kCpumSysRegWrFn_Invalid = 0,
91	/** Writes are ignored. */
92	kCpumSysRegWrFn_IgnoreWrite,
93	/** Writes cause an exception. */
94	kCpumSysRegWrFn_ReadOnly,
95	/** Alias to the system register range starting at the system register given by
96	* CPUMSYSREGRANGE::uValue. Must be used in pair with
97	* kCpumSysRegRdFn_Alias. */
98	kCpumSysRegWrFn_Alias,
99	/** Write the value to the given offset from the beginning of CPUMGSTCTX. */
100	kCpumSysRegWrFn_WriteCpumOff,
101
102	/** Write to a GICv3 PE ICC system register. */
103	kCpumSysRegWrFn_GicV3Icc,
104	/** Write to the OSLAR_EL1 syste register. */
105	kCpumSysRegWrFn_OslarEl1,
106	/** Write to a PMU system register. */
107	kCpumSysRegWrFn_Pmu,
108
109	/** End of valid system register write function indexes. */
110	kCpumSysRegWrFn_End
111	} CPUMSYSREGWRFN;
112
113
114	/**
115	* System register range.
116	*
117	* @note This is very similar to how x86/amd64 MSRs are handled.
118	*/
119	typedef struct CPUMSYSREGRANGE
120	{
121	/** The first system register. [0] */
122	uint16_t uFirst;
123	/** The last system register. [2] */
124	uint16_t uLast;
125	/** The read function (CPUMMSRRDFN). [4] */
126	uint16_t enmRdFn;
127	/** The write function (CPUMMSRWRFN). [6] */
128	uint16_t enmWrFn;
129	/** The offset of the 64-bit system register value relative to the start of CPUMCPU.
130	* UINT16_MAX if not used by the read and write functions. [8] */
131	uint32_t offCpumCpu : 24;
132	/** Reserved for future hacks. [11] */
133	uint32_t fReserved : 8;
134	/** Padding/Reserved. [12] */
135	uint32_t u32Padding;
136	/** The init/read value. [16]
137	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
138	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
139	* offset into CPUM. */
140	uint64_t uValue;
141	/** The bits to ignore when writing. [24] */
142	uint64_t fWrIgnMask;
143	/** The bits that will cause an exception when writing. [32]
144	* This is always checked prior to calling the write function. Using
145	* UINT64_MAX effectively marks the MSR as read-only. */
146	uint64_t fWrExcpMask;
147	/** The register name, if applicable. [32] */
148	char szName[56];
149
150	/** The number of reads. */
151	STAMCOUNTER cReads;
152	/** The number of writes. */
153	STAMCOUNTER cWrites;
154	/** The number of times ignored bits were written. */
155	STAMCOUNTER cIgnoredBits;
156	/** The number of exceptions generated. */
157	STAMCOUNTER cExcp;
158	} CPUMSYSREGRANGE;
159	#ifndef VBOX_FOR_DTRACE_LIB
160	AssertCompileSize(CPUMSYSREGRANGE, 128);
161	#endif
162	/** Pointer to an system register range. */
163	typedef CPUMSYSREGRANGE *PCPUMSYSREGRANGE;
164	/** Pointer to a const system register range. */
165	typedef CPUMSYSREGRANGE const *PCCPUMSYSREGRANGE;
166
167
168	/**
169	* CPU features and quirks.
170	* This is mostly exploded CPUID info.
171	*/
172	typedef struct CPUMFEATURES
173	{
174	/** The CPU vendor (CPUMCPUVENDOR). */
175	uint8_t enmCpuVendor;
176	/** The CPU family. */
177	uint8_t uFamily;
178	/** The CPU model. */
179	uint8_t uModel;
180	/** The CPU stepping. */
181	uint8_t uStepping;
182	/** The microarchitecture. */
183	#ifndef VBOX_FOR_DTRACE_LIB
184	CPUMMICROARCH enmMicroarch;
185	#else
186	uint32_t enmMicroarch;
187	#endif
188	/** The maximum physical address width of the CPU. */
189	uint8_t cMaxPhysAddrWidth;
190	/** The maximum linear address width of the CPU. */
191	uint8_t cMaxLinearAddrWidth;
192	uint16_t uPadding;
193
194	/** @name Granule sizes supported.
195	* @{ */
196	/** 4KiB translation granule size supported. */
197	uint32_t fTGran4K : 1;
198	/** 16KiB translation granule size supported. */
199	uint32_t fTGran16K : 1;
200	/** 64KiB translation granule size supported. */
201	uint32_t fTGran64K : 1;
202	/** @} */
203
204	/** @name pre-2020 Architecture Extensions.
205	* @{ */
206	/** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */
207	uint32_t fAdvSimd : 1;
208	/** Supports Advanced SIMD AES instructions (FEAT_AES). */
209	uint32_t fAes : 1;
210	/** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */
211	uint32_t fPmull : 1;
212	/** Supports CP15Disable2 (FEAT_CP15DISABLE2). */
213	uint32_t fCp15Disable2 : 1;
214	/** Supports Cache Speculation Variant 2 (FEAT_CSV2). */
215	uint32_t fCsv2 : 1;
216	/** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */
217	uint32_t fCsv21p1 : 1;
218	/** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */
219	uint32_t fCsv21p2 : 1;
220	/** Supports Cache Speculation Variant 3 (FEAT_CSV3). */
221	uint32_t fCsv3 : 1;
222	/** Supports Data Gahtering Hint (FEAT_DGH). */
223	uint32_t fDgh : 1;
224	/** Supports Double Lock (FEAT_DoubleLock). */
225	uint32_t fDoubleLock : 1;
226	/** Supports Enhanced Translation Synchronization (FEAT_ETS2). */
227	uint32_t fEts2 : 1;
228	/** Supports Floating Point Extensions (FEAT_FP). */
229	uint32_t fFp : 1;
230	/** Supports IVIPT Extensions (FEAT_IVIPT). */
231	uint32_t fIvipt : 1;
232	/** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */
233	uint32_t fPcsrV8 : 1;
234	/** Supports Speculation Restrictions instructions (FEAT_SPECRES). */
235	uint32_t fSpecres : 1;
236	/** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */
237	uint32_t fRas : 1;
238	/** Supports Speculation Barrier (FEAT_SB). */
239	uint32_t fSb : 1;
240	/** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */
241	uint32_t fSha1 : 1;
242	/** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */
243	uint32_t fSha256 : 1;
244	/** Supports Speculation Store Bypass Safe (FEAT_SSBS). */
245	uint32_t fSsbs : 1;
246	/** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */
247	uint32_t fSsbs2 : 1;
248	/** Supports CRC32 instructions (FEAT_CRC32). */
249	uint32_t fCrc32 : 1;
250	/** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */
251	uint32_t fNTlbpa : 1;
252	/** Supports debug with VHE (FEAT_Debugv8p1). */
253	uint32_t fDebugV8p1 : 1;
254	/** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */
255	uint32_t fHpds : 1;
256	/** Supports Limited ordering regions (FEAT_LOR). */
257	uint32_t fLor : 1;
258	/** Supports Lare Systems Extensons (FEAT_LSE). */
259	uint32_t fLse : 1;
260	/** Supports Privileged access never (FEAT_PAN). */
261	uint32_t fPan : 1;
262	/** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */
263	uint32_t fPmuV3p1 : 1;
264	/** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */
265	uint32_t fRdm : 1;
266	/** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */
267	uint32_t fHafdbs : 1;
268	/** Supports Virtualization Host Extensions (FEAT_VHE). */
269	uint32_t fVhe : 1;
270	/** Supports 16-bit VMID (FEAT_VMID16). */
271	uint32_t fVmid16 : 1;
272	/** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */
273	uint32_t fAa32Bf16 : 1;
274	/** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */
275	uint32_t fAa32Hpd : 1;
276	/** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */
277	uint32_t fAa32I8mm : 1;
278	/** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */
279	uint32_t fPan2 : 1;
280	/** Supports AArch64 BFloat16 instructions (FEAT_BF16). */
281	uint32_t fBf16 : 1;
282	/** Supports DC CVADP instruction (FEAT_DPB2). */
283	uint32_t fDpb2 : 1;
284	/** Supports DC VAP instruction (FEAT_DPB). */
285	uint32_t fDpb : 1;
286	/** Supports Debug v8.2 (FEAT_Debugv8p2). */
287	uint32_t fDebugV8p2 : 1;
288	/** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */
289	uint32_t fDotProd : 1;
290	/** Supports Enhanced Virtualization Traps (FEAT_EVT). */
291	uint32_t fEvt : 1;
292	/** Supports Single precision Matrix Multiplication (FEAT_F32MM). */
293	uint32_t fF32mm : 1;
294	/** Supports Double precision Matrix Multiplication (FEAT_F64MM). */
295	uint32_t fF64mm : 1;
296	/** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */
297	uint32_t fFhm : 1;
298	/** Supports Half-precision floating point data processing (FEAT_FP16). */
299	uint32_t fFp16 : 1;
300	/** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */
301	uint32_t fI8mm : 1;
302	/** Supports Implicit Error Synchronization event (FEAT_IESB). */
303	uint32_t fIesb : 1;
304	/** Supports Large PA and IPA support (FEAT_LPA). */
305	uint32_t fLpa : 1;
306	/** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */
307	uint32_t fLsmaoc : 1;
308	/** Supports Large VA support (FEAT_LVA). */
309	uint32_t fLva : 1;
310	/** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */
311	uint32_t fMpam : 1;
312	/** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */
313	uint32_t fPcsrV8p2 : 1;
314	/** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */
315	uint32_t fSha3 : 1;
316	/** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */
317	uint32_t fSha512 : 1;
318	/** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */
319	uint32_t fSm3 : 1;
320	/** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */
321	uint32_t fSm4 : 1;
322	/** Supports Statistical Profiling Extension (FEAT_SPE). */
323	uint32_t fSpe : 1;
324	/** Supports Scalable Vector Extension (FEAT_SVE). */
325	uint32_t fSve : 1;
326	/** Supports Translation Table Common not private translations (FEAT_TTCNP). */
327	uint32_t fTtcnp : 1;
328	/** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */
329	uint32_t fHpds2 : 1;
330	/** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */
331	uint32_t fXnx : 1;
332	/** Supports Unprivileged Access Override control (FEAT_UAO). */
333	uint32_t fUao : 1;
334	/** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */
335	uint32_t fVpipt : 1;
336	/** Supports Extended cache index (FEAT_CCIDX). */
337	uint32_t fCcidx : 1;
338	/** Supports Floating-point complex number instructions (FEAT_FCMA). */
339	uint32_t fFcma : 1;
340	/** Supports Debug over Powerdown (FEAT_DoPD). */
341	uint32_t fDopd : 1;
342	/** Supports Enhanced pointer authentication (FEAT_EPAC). */
343	uint32_t fEpac : 1;
344	/** Supports Faulting on AUT* instructions (FEAT_FPAC). */
345	uint32_t fFpac : 1;
346	/** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */
347	uint32_t fFpacCombine : 1;
348	/** Supports JavaScript conversion instructions (FEAT_JSCVT). */
349	uint32_t fJscvt : 1;
350	/** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */
351	uint32_t fLrcpc : 1;
352	/** Supports Nexted Virtualization (FEAT_NV). */
353	uint32_t fNv : 1;
354	/** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */
355	uint32_t fPacQarma5 : 1;
356	/** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */
357	uint32_t fPacImp : 1;
358	/** Supports Pointer authentication (FEAT_PAuth). */
359	uint32_t fPAuth : 1;
360	/** Supports Enhancements to pointer authentication (FEAT_PAuth2). */
361	uint32_t fPAuth2 : 1;
362	/** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */
363	uint32_t fSpeV1p1 : 1;
364	/** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */
365	uint32_t fAmuV1 : 1;
366	/** Supports Generic Counter Scaling (FEAT_CNTSC). */
367	uint32_t fCntsc : 1;
368	/** Supports Debug v8.4 (FEAT_Debugv8p4). */
369	uint32_t fDebugV8p4 : 1;
370	/** Supports Double Fault Extension (FEAT_DoubleFault). */
371	uint32_t fDoubleFault : 1;
372	/** Supports Data Independent Timing instructions (FEAT_DIT). */
373	uint32_t fDit : 1;
374	/** Supports Condition flag manipulation isntructions (FEAT_FlagM). */
375	uint32_t fFlagM : 1;
376	/** Supports ID space trap handling (FEAT_IDST). */
377	uint32_t fIdst : 1;
378	/** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */
379	uint32_t fLrcpc2 : 1;
380	/** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */
381	uint32_t fLse2 : 1;
382	/** Supports Enhanced nested virtualization support (FEAT_NV2). */
383	uint32_t fNv2 : 1;
384	/** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */
385	uint32_t fPmuV3p4 : 1;
386	/** Supports RAS Extension v1.1 (FEAT_RASv1p1). */
387	uint32_t fRasV1p1 : 1;
388	/** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */
389	uint32_t fRassaV1p1 : 1;
390	/** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */
391	uint32_t fS2Fwb : 1;
392	/** Supports Secure El2 (FEAT_SEL2). */
393	uint32_t fSecEl2 : 1;
394	/** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */
395	uint32_t fTlbios : 1;
396	/** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */
397	uint32_t fTlbirange : 1;
398	/** Supports Self-hosted Trace Extensions (FEAT_TRF). */
399	uint32_t fTrf : 1;
400	/** Supports Translation Table Level (FEAT_TTL). */
401	uint32_t fTtl : 1;
402	/** Supports Translation table break-before-make levels (FEAT_BBM). */
403	uint32_t fBbm : 1;
404	/** Supports Small translation tables (FEAT_TTST). */
405	uint32_t fTtst : 1;
406	/** Supports Branch Target Identification (FEAT_BTI). */
407	uint32_t fBti : 1;
408	/** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */
409	uint32_t fFlagM2 : 1;
410	/** Supports Context synchronization and exception handling (FEAT_ExS). */
411	uint32_t fExs : 1;
412	/** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */
413	uint32_t fE0Pd : 1;
414	/** Supports Floating-point to integer instructions (FEAT_FRINTTS). */
415	uint32_t fFrintts : 1;
416	/** Supports Guest translation granule size (FEAT_GTG). */
417	uint32_t fGtg : 1;
418	/** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */
419	uint32_t fMte : 1;
420	/** Supports memory Tagging Extension version 2 (FEAT_MTE2). */
421	uint32_t fMte2 : 1;
422	/** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */
423	uint32_t fPmuV3p5 : 1;
424	/** Supports Random number generator (FEAT_RNG). */
425	uint32_t fRng : 1;
426	/** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */
427	uint32_t fAmuV1p1 : 1;
428	/** Supports Enhanced Counter Virtualization (FEAT_ECV). */
429	uint32_t fEcv : 1;
430	/** Supports Fine Grain Traps (FEAT_FGT). */
431	uint32_t fFgt : 1;
432	/** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */
433	uint32_t fMpamV0p1 : 1;
434	/** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */
435	uint32_t fMpamV1p1 : 1;
436	/** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */
437	uint32_t fMtPmu : 1;
438	/** Supports Delayed Trapping of WFE (FEAT_TWED). */
439	uint32_t fTwed : 1;
440	/** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */
441	uint32_t fEtmV4 : 1;
442	/** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */
443	uint32_t fEtmV4p1 : 1;
444	/** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */
445	uint32_t fEtmV4p2 : 1;
446	/** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */
447	uint32_t fEtmV4p3 : 1;
448	/** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */
449	uint32_t fEtmV4p4 : 1;
450	/** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */
451	uint32_t fEtmV4p5 : 1;
452	/** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */
453	uint32_t fEtmV4p6 : 1;
454	/** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */
455	uint32_t fGicV3 : 1;
456	/** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */
457	uint32_t fGicV3p1 : 1;
458	/** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */
459	uint32_t fGicV3Tdir : 1;
460	/** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */
461	uint32_t fGicV4 : 1;
462	/** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */
463	uint32_t fGicV4p1 : 1;
464	/** Supports PMU extension, version 3 (FEAT_PMUv3). */
465	uint32_t fPmuV3 : 1;
466	/** Supports Embedded Trace Extension (FEAT_ETE). */
467	uint32_t fEte : 1;
468	/** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */
469	uint32_t fEteV1p1 : 1;
470	/** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */
471	uint32_t fEteV1p2 : 1;
472	/** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */
473	uint32_t fSve2 : 1;
474	/** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */
475	uint32_t fSveAes : 1;
476	/** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */
477	uint32_t fSvePmull128 : 1;
478	/** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */
479	uint32_t fSveBitPerm : 1;
480	/** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */
481	uint32_t fSveSha3 : 1;
482	/** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */
483	uint32_t fSveSm4 : 1;
484	/** Supports Transactional Memory Extension (FEAT_TME). */
485	uint32_t fTme : 1;
486	/** Supports Trace Buffer Extension (FEAT_TRBE). */
487	uint32_t fTrbe : 1;
488	/** Supports Scalable Matrix Extension (FEAT_SME). */
489	uint32_t fSme : 1;
490	/** @} */
491
492	/** @name 2020 Architecture Extensions.
493	* @{ */
494	/** Supports Alternate floating-point behavior (FEAT_AFP). */
495	uint32_t fAfp : 1;
496	/** Supports HCRX_EL2 register (FEAT_HCX). */
497	uint32_t fHcx : 1;
498	/** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */
499	uint32_t fLpa2 : 1;
500	/** Supports 64 byte loads and stores without return (FEAT_LS64). */
501	uint32_t fLs64 : 1;
502	/** Supports 64 byte stores with return (FEAT_LS64_V). */
503	uint32_t fLs64V : 1;
504	/** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */
505	uint32_t fLs64Accdata : 1;
506	/** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */
507	uint32_t fMte3 : 1;
508	/** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */
509	uint32_t fPan3 : 1;
510	/** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */
511	uint32_t fPmuV3p7 : 1;
512	/** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */
513	uint32_t fRpres : 1;
514	/** Supports Realm Management Extension (FEAT_RME). */
515	uint32_t fRme : 1;
516	/** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */
517	uint32_t fSmeFA64 : 1;
518	/** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */
519	uint32_t fSmeF64F64 : 1;
520	/** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */
521	uint32_t fSmeI16I64 : 1;
522	/** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */
523	uint32_t fSpeV1p2 : 1;
524	/** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */
525	uint32_t fEbf16 : 1;
526	/** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */
527	uint32_t fWfxt : 1;
528	/** Supports XS attribute (FEAT_XS). */
529	uint32_t fXs : 1;
530	/** Supports branch Record Buffer Extension (FEAT_BRBE). */
531	uint32_t fBrbe : 1;
532	/** @} */
533
534	/** @name 2021 Architecture Extensions.
535	* @{ */
536	/** Supports Control for cache maintenance permission (FEAT_CMOW). */
537	uint32_t fCmow : 1;
538	/** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */
539	uint32_t fConstPacField : 1;
540	/** Supports Debug v8.8 (FEAT_Debugv8p8). */
541	uint32_t fDebugV8p8 : 1;
542	/** Supports Hinted conditional branches (FEAT_HBC). */
543	uint32_t fHbc : 1;
544	/** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */
545	uint32_t fHpmn0 : 1;
546	/** Supports Non-Maskable Interrupts (FEAT_NMI). */
547	uint32_t fNmi : 1;
548	/** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */
549	uint32_t fGicV3Nmi : 1;
550	/** Supports Standardization of memory operations (FEAT_MOPS). */
551	uint32_t fMops : 1;
552	/** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */
553	uint32_t fPacQarma3 : 1;
554	/** Supports Event counting threshold (FEAT_PMUv3_TH). */
555	uint32_t fPmuV3Th : 1;
556	/** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */
557	uint32_t fPmuV3p8 : 1;
558	/** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */
559	uint32_t fPmuV3Ext64 : 1;
560	/** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */
561	uint32_t fPmuV3Ext32 : 1;
562	/** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */
563	uint32_t fPmuV3Ext : 1;
564	/** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */
565	uint32_t fRngTrap : 1;
566	/** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */
567	uint32_t fSpeV1p3 : 1;
568	/** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */
569	uint32_t fTidcp1 : 1;
570	/** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */
571	uint32_t fBrbeV1p1 : 1;
572	/** @} */
573
574	/** @name 2022 Architecture Extensions.
575	* @{ */
576	/** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */
577	uint32_t fAble : 1;
578	/** Supports Asynchronous Device error exceptions (FEAT_ADERR). */
579	uint32_t fAderr : 1;
580	/** Supports Memory Attribute Index Enhancement (FEAT_AIE). */
581	uint32_t fAie : 1;
582	/** Supports Asynchronous Normal error exception (FEAT_ANERR). */
583	uint32_t fAnerr : 1;
584	/** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */
585	uint32_t fBwe : 1;
586	/** Supports Clear Branch History instruction (FEAT_CLRBHB). */
587	uint32_t fClrBhb : 1;
588	/** Supports Check Feature Status (FEAT_CHK). */
589	uint32_t fChk : 1;
590	/** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */
591	uint32_t fCssc : 1;
592	/** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */
593	uint32_t fCsv2v3 : 1;
594	/** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */
595	uint32_t fD128 : 1;
596	/** Supports Debug v8.9 (FEAT_Debugv8p9). */
597	uint32_t fDebugV8p9 : 1;
598	/** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */
599	uint32_t fDoubleFault2 : 1;
600	/** Supports Exception based Event Profiling (FEAT_EBEP). */
601	uint32_t fEbep : 1;
602	/** Supports Exploitative control using branch history information (FEAT_ECBHB). */
603	uint32_t fEcBhb : 1;
604	/** Supports for EDHSR (FEAT_EDHSR). */
605	uint32_t fEdhsr : 1;
606	/** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */
607	uint32_t fEteV1p3 : 1;
608	/** Supports Fine-grained traps 2 (FEAT_FGT2). */
609	uint32_t fFgt2 : 1;
610	/** Supports Guarded Control Stack Extension (FEAT_GCS). */
611	uint32_t fGcs : 1;
612	/** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */
613	uint32_t fHaft : 1;
614	/** Supports Instrumentation Extension (FEAT_ITE). */
615	uint32_t fIte : 1;
616	/** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */
617	uint32_t fLrcpc3 : 1;
618	/** Supports 128-bit atomics (FEAT_LSE128). */
619	uint32_t fLse128 : 1;
620	/** Supports 56-bit VA (FEAT_LVA3). */
621	uint32_t fLva3 : 1;
622	/** Supports Memory Encryption Contexts (FEAT_MEC). */
623	uint32_t fMec : 1;
624	/** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */
625	uint32_t fMte4 : 1;
626	/** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */
627	uint32_t fMteCanonicalTags : 1;
628	/** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */
629	uint32_t fMteTaggedFar : 1;
630	/** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */
631	uint32_t fMteStoreOnly : 1;
632	/** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */
633	uint32_t fMteNoAddressTags : 1;
634	/** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */
635	uint32_t fMteAsymFault : 1;
636	/** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */
637	uint32_t fMteAsync : 1;
638	/** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */
639	uint32_t fMtePermS1 : 1;
640	/** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */
641	uint32_t fPcsrV8p9 : 1;
642	/** Supports Permission model enhancements (FEAT_S1PIE). */
643	uint32_t fS1Pie : 1;
644	/** Supports Permission model enhancements (FEAT_S2PIE). */
645	uint32_t fS2Pie : 1;
646	/** Supports Permission model enhancements (FEAT_S1POE). */
647	uint32_t fS1Poe : 1;
648	/** Supports Permission model enhancements (FEAT_S2POE). */
649	uint32_t fS2Poe : 1;
650	/** Supports Physical Fault Address Registers (FEAT_PFAR). */
651	uint32_t fPfar : 1;
652	/** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */
653	uint32_t fPmuV3p9 : 1;
654	/** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */
655	uint32_t fPmuV3Edge : 1;
656	/** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */
657	uint32_t fPmuV3Icntr : 1;
658	/** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */
659	uint32_t fPmuV3Ss : 1;
660	/** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */
661	uint32_t fPrfmSlc : 1;
662	/** Supports RAS version 2 (FEAT_RASv2). */
663	uint32_t fRasV2 : 1;
664	/** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */
665	uint32_t fRasSaV2 : 1;
666	/** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */
667	uint32_t fRprfm : 1;
668	/** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */
669	uint32_t fSctlr2 : 1;
670	/** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */
671	uint32_t fSebep : 1;
672	/** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */
673	uint32_t fSmeF16F16 : 1;
674	/** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */
675	uint32_t fSme2 : 1;
676	/** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */
677	uint32_t fSme2p1 : 1;
678	/** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */
679	uint32_t fSpecres2 : 1;
680	/** Supports System Performance Monitors Extension (FEAT_SPMU). */
681	uint32_t fSpmu : 1;
682	/** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */
683	uint32_t fSpeV1p4 : 1;
684	/** Supports Call Return Branch Records (FEAT_SPE_CRR). */
685	uint32_t fSpeCrr : 1;
686	/** Supports Data Source Filtering (FEAT_SPE_FDS). */
687	uint32_t fSpeFds : 1;
688	/** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */
689	uint32_t fSve2p1 : 1;
690	/** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */
691	uint32_t fSveB16B16 : 1;
692	/** Supports 128-bit System instructions (FEAT_SYSINSTR128). */
693	uint32_t fSysInstr128 : 1;
694	/** Supports 128-bit System registers (FEAT_SYSREG128). */
695	uint32_t fSysReg128 : 1;
696	/** Supports Extension to TCR_ELx (FEAT_TCR2). */
697	uint32_t fTcr2 : 1;
698	/** Supports Translation Hardening Extension (FEAT_THE). */
699	uint32_t fThe : 1;
700	/** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */
701	uint32_t fTrbeExt : 1;
702	/** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */
703	uint32_t fTrbeMpam : 1;
704	/** @} */
705
706	/** Padding to the required size to match CPUMFEATURES for x86/amd64. */
707	uint8_t abPadding[4];
708	} CPUMFEATURES;
709	#ifndef VBOX_FOR_DTRACE_LIB
710	AssertCompileSize(CPUMFEATURES, 48);
711	#endif
712	/** Pointer to a CPU feature structure. */
713	typedef CPUMFEATURES *PCPUMFEATURES;
714	/** Pointer to a const CPU feature structure. */
715	typedef CPUMFEATURES const *PCCPUMFEATURES;
716
717	/**
718	* Chameleon wrapper structure for the host CPU features.
719	*
720	* This is used for the globally readable g_CpumHostFeatures variable, which is
721	* initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
722	* ring-3. To reflect this immutability after load/init, we use this wrapper
723	* structure to switch it between const and non-const depending on the context.
724	* Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
725	*/
726	typedef struct CPUHOSTFEATURES
727	{
728	CPUMFEATURES
729	#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
730	const
731	#endif
732	s;
733	} CPUHOSTFEATURES;
734	/** Pointer to a const host CPU feature structure. */
735	typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
736
737	/** Host CPU features.
738	* @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
739	* module init. */
740	extern CPUHOSTFEATURES g_CpumHostFeatures;
741
742
743	/**
744	* CPU database entry.
745	*/
746	typedef struct CPUMDBENTRY
747	{
748	/** The CPU name. */
749	const char *pszName;
750	/** The full CPU name. */
751	const char *pszFullName;
752	/** The CPU vendor (CPUMCPUVENDOR). */
753	uint8_t enmVendor;
754	/** The CPU family. */
755	uint8_t uFamily;
756	/** The CPU model. */
757	uint8_t uModel;
758	/** The CPU stepping. */
759	uint8_t uStepping;
760	/** The microarchitecture. */
761	CPUMMICROARCH enmMicroarch;
762	/** Scalable bus frequency used for reporting other frequencies. */
763	uint64_t uScalableBusFreq;
764	/** Flags - CPUMDB_F_XXX. */
765	uint32_t fFlags;
766	/** The maximum physical address with of the CPU. This should correspond to
767	* the value in CPUID leaf 0x80000008 when present. */
768	uint8_t cMaxPhysAddrWidth;
769	} CPUMDBENTRY;
770	/** Pointer to a const CPU database entry. */
771	typedef CPUMDBENTRY const *PCCPUMDBENTRY;
772
773
774	/**
775	* CPU ID registers.
776	*/
777	typedef struct CPUMIDREGS
778	{
779	/** Content of the ID_AA64PFR0_EL1 register. */
780	uint64_t u64RegIdAa64Pfr0El1;
781	/** Content of the ID_AA64PFR1_EL1 register. */
782	uint64_t u64RegIdAa64Pfr1El1;
783	/** Content of the ID_AA64DFR0_EL1 register. */
784	uint64_t u64RegIdAa64Dfr0El1;
785	/** Content of the ID_AA64DFR1_EL1 register. */
786	uint64_t u64RegIdAa64Dfr1El1;
787	/** Content of the ID_AA64AFR0_EL1 register. */
788	uint64_t u64RegIdAa64Afr0El1;
789	/** Content of the ID_AA64AFR1_EL1 register. */
790	uint64_t u64RegIdAa64Afr1El1;
791	/** Content of the ID_AA64ISAR0_EL1 register. */
792	uint64_t u64RegIdAa64Isar0El1;
793	/** Content of the ID_AA64ISAR1_EL1 register. */
794	uint64_t u64RegIdAa64Isar1El1;
795	/** Content of the ID_AA64ISAR2_EL1 register. */
796	uint64_t u64RegIdAa64Isar2El1;
797	/** Content of the ID_AA64MMFR0_EL1 register. */
798	uint64_t u64RegIdAa64Mmfr0El1;
799	/** Content of the ID_AA64MMFR1_EL1 register. */
800	uint64_t u64RegIdAa64Mmfr1El1;
801	/** Content of the ID_AA64MMFR2_EL1 register. */
802	uint64_t u64RegIdAa64Mmfr2El1;
803	/** Content of the CLIDR_EL1 register. */
804	uint64_t u64RegClidrEl1;
805	/** Content of the CTR_EL0 register. */
806	uint64_t u64RegCtrEl0;
807	/** Content of the DCZID_EL0 register. */
808	uint64_t u64RegDczidEl0;
809	} CPUMIDREGS;
810	/** Pointer to CPU ID registers. */
811	typedef CPUMIDREGS *PCPUMIDREGS;
812	/** Pointer to a const CPU ID registers structure. */
813	typedef CPUMIDREGS const *PCCPUMIDREGS;
814
815
816	/** @name Changed flags.
817	* These flags are used to keep track of which important register that
818	* have been changed since last they were reset. The only one allowed
819	* to clear them is REM!
820	*
821	* @todo This is obsolete, but remains as it will be refactored for coordinating
822	* IEM and NEM/HM later. Probably.
823	* @{
824	*/
825	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(0)
826	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_GLOBAL_TLB_FLUSH )
827	/** @} */
828
829
830	#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) \|\| defined(DOXYGEN_RUNNING)
831	/** @name Inlined Guest Getters and predicates Functions.
832	* @{ */
833
834	/**
835	* Tests if the guest is running in 64 bits mode or not.
836	*
837	* @returns true if in 64 bits mode, otherwise false.
838	* @param pCtx Current CPU context.
839	*/
840	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
841	{
842	return !RT_BOOL(pCtx->fPState & ARMV8_SPSR_EL2_AARCH64_M4);
843	}
844
845	/** @} */
846	#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS \|\| DOXYGEN_RUNNING */
847
848
849	#ifndef VBOX_FOR_DTRACE_LIB
850
851	#ifdef IN_RING3
852	/** @defgroup grp_cpum_armv8_r3 The CPUM ARMv8 ring-3 API
853	* @{
854	*/
855
856	VMMR3DECL(int) CPUMR3SysRegRangesInsert(PVM pVM, PCCPUMSYSREGRANGE pNewRange);
857	VMMR3DECL(int) CPUMR3PopulateFeaturesByIdRegisters(PVM pVM, PCCPUMIDREGS pIdRegs);
858
859	VMMR3_INT_DECL(int) CPUMR3QueryGuestIdRegs(PVM pVM, PCCPUMIDREGS *ppIdRegs);
860
861	/** @} */
862	#endif /* IN_RING3 */
863
864
865	/** @name Guest Register Getters.
866	* @{ */
867	VMMDECL(bool) CPUMGetGuestIrqMasked(PVMCPUCC pVCpu);
868	VMMDECL(bool) CPUMGetGuestFiqMasked(PVMCPUCC pVCpu);
869	VMM_INT_DECL(uint8_t) CPUMGetGuestEL(PVMCPUCC pVCpu);
870	VMM_INT_DECL(bool) CPUMGetGuestMmuEnabled(PVMCPUCC pVCpu);
871	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t *puValue);
872	VMM_INT_DECL(RTGCPHYS) CPUMGetEffectiveTtbr(PVMCPUCC pVCpu, RTGCPTR GCPtr);
873	VMM_INT_DECL(uint64_t) CPUMGetTcrEl1(PVMCPUCC pVCpu);
874	VMM_INT_DECL(RTGCPTR) CPUMGetGCPtrPacStripped(PVMCPUCC pVCpu, RTGCPTR GCPtr);
875	/** @} */
876
877
878	/** @name Guest Register Setters.
879	* @{ */
880	VMMDECL(VBOXSTRICTRC) CPUMSetGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t uValue);
881	/** @} */
882
883	#endif
884
885	/** @} */
886	RT_C_DECLS_END
887
888
889	#endif /* !VBOX_INCLUDED_vmm_cpum_armv8_h */
890

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source: vbox/trunk/include/VBox/vmm/cpum-armv8.h@ 107031

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