cpum.h@ 55254

Last change on this file since 55254 was 55229, checked in by vboxsync, 10 years ago
CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), making IEM use it. Early XSAVE/AVX guest support preps.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 60.9 KB

Line
1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpum_h
27	#define ___VBox_vmm_cpum_h
28
29	#include <iprt/x86.h>
30	#include <VBox/types.h>
31	#include <VBox/vmm/cpumctx.h>
32	#include <VBox/vmm/stam.h>
33
34	RT_C_DECLS_BEGIN
35
36	/** @defgroup grp_cpum The CPU Monitor / Manager API
37	* @{
38	*/
39
40	/**
41	* CPUID feature to set or clear.
42	*/
43	typedef enum CPUMCPUIDFEATURE
44	{
45	CPUMCPUIDFEATURE_INVALID = 0,
46	/** The APIC feature bit. (Std+Ext) */
47	CPUMCPUIDFEATURE_APIC,
48	/** The sysenter/sysexit feature bit. (Std) */
49	CPUMCPUIDFEATURE_SEP,
50	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
51	CPUMCPUIDFEATURE_SYSCALL,
52	/** The PAE feature bit. (Std+Ext) */
53	CPUMCPUIDFEATURE_PAE,
54	/** The NX feature bit. (Ext) */
55	CPUMCPUIDFEATURE_NX,
56	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
57	CPUMCPUIDFEATURE_LAHF,
58	/** The LONG MODE feature bit. (Ext) */
59	CPUMCPUIDFEATURE_LONG_MODE,
60	/** The PAT feature bit. (Std+Ext) */
61	CPUMCPUIDFEATURE_PAT,
62	/** The x2APIC feature bit. (Std) */
63	CPUMCPUIDFEATURE_X2APIC,
64	/** The RDTSCP feature bit. (Ext) */
65	CPUMCPUIDFEATURE_RDTSCP,
66	/** The Hypervisor Present bit. (Std) */
67	CPUMCPUIDFEATURE_HVP,
68	/** The MWait Extensions bits (Std) */
69	CPUMCPUIDFEATURE_MWAIT_EXTS,
70	/** The CR4.OSXSAVE bit CPUID mirroring, only use from CPUMSetGuestCR4. */
71	CPUMCPUIDFEATURE_OSXSAVE,
72	/** 32bit hackishness. */
73	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
74	} CPUMCPUIDFEATURE;
75
76	/**
77	* CPU Vendor.
78	*/
79	typedef enum CPUMCPUVENDOR
80	{
81	CPUMCPUVENDOR_INVALID = 0,
82	CPUMCPUVENDOR_INTEL,
83	CPUMCPUVENDOR_AMD,
84	CPUMCPUVENDOR_VIA,
85	CPUMCPUVENDOR_CYRIX,
86	CPUMCPUVENDOR_UNKNOWN,
87	/** 32bit hackishness. */
88	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
89	} CPUMCPUVENDOR;
90
91
92	/**
93	* X86 and AMD64 CPU microarchitectures and in processor generations.
94	*
95	* @remarks The separation here is sometimes a little bit too finely grained,
96	* and the differences is more like processor generation than micro
97	* arch. This can be useful, so we'll provide functions for getting at
98	* more coarse grained info.
99	*/
100	typedef enum CPUMMICROARCH
101	{
102	kCpumMicroarch_Invalid = 0,
103
104	kCpumMicroarch_Intel_First,
105
106	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
107	kCpumMicroarch_Intel_80186,
108	kCpumMicroarch_Intel_80286,
109	kCpumMicroarch_Intel_80386,
110	kCpumMicroarch_Intel_80486,
111	kCpumMicroarch_Intel_P5,
112
113	kCpumMicroarch_Intel_P6_Core_Atom_First,
114	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
115	kCpumMicroarch_Intel_P6_II,
116	kCpumMicroarch_Intel_P6_III,
117
118	kCpumMicroarch_Intel_P6_M_Banias,
119	kCpumMicroarch_Intel_P6_M_Dothan,
120	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
121
122	kCpumMicroarch_Intel_Core2_First,
123	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
124	kCpumMicroarch_Intel_Core2_Penryn,
125
126	kCpumMicroarch_Intel_Core7_First,
127	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
128	kCpumMicroarch_Intel_Core7_Westmere,
129	kCpumMicroarch_Intel_Core7_SandyBridge,
130	kCpumMicroarch_Intel_Core7_IvyBridge,
131	kCpumMicroarch_Intel_Core7_Haswell,
132	kCpumMicroarch_Intel_Core7_Broadwell,
133	kCpumMicroarch_Intel_Core7_Skylake,
134	kCpumMicroarch_Intel_Core7_Cannonlake,
135	kCpumMicroarch_Intel_Core7_End,
136
137	kCpumMicroarch_Intel_Atom_First,
138	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
139	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
140	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
141	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
142	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
143	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
144	kCpumMicroarch_Intel_Atom_Unknown,
145	kCpumMicroarch_Intel_Atom_End,
146
147	kCpumMicroarch_Intel_P6_Core_Atom_End,
148
149	kCpumMicroarch_Intel_NB_First,
150	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
151	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
152	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
153	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
154	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
155	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
156	kCpumMicroarch_Intel_NB_Unknown,
157	kCpumMicroarch_Intel_NB_End,
158
159	kCpumMicroarch_Intel_Unknown,
160	kCpumMicroarch_Intel_End,
161
162	kCpumMicroarch_AMD_First,
163	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
164	kCpumMicroarch_AMD_Am386,
165	kCpumMicroarch_AMD_Am486,
166	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
167	kCpumMicroarch_AMD_K5,
168	kCpumMicroarch_AMD_K6,
169
170	kCpumMicroarch_AMD_K7_First,
171	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
172	kCpumMicroarch_AMD_K7_Spitfire,
173	kCpumMicroarch_AMD_K7_Thunderbird,
174	kCpumMicroarch_AMD_K7_Morgan,
175	kCpumMicroarch_AMD_K7_Thoroughbred,
176	kCpumMicroarch_AMD_K7_Barton,
177	kCpumMicroarch_AMD_K7_Unknown,
178	kCpumMicroarch_AMD_K7_End,
179
180	kCpumMicroarch_AMD_K8_First,
181	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
182	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
183	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
184	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
185	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
186	kCpumMicroarch_AMD_K8_End,
187
188	kCpumMicroarch_AMD_K10,
189	kCpumMicroarch_AMD_K10_Lion,
190	kCpumMicroarch_AMD_K10_Llano,
191	kCpumMicroarch_AMD_Bobcat,
192	kCpumMicroarch_AMD_Jaguar,
193
194	kCpumMicroarch_AMD_15h_First,
195	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
196	kCpumMicroarch_AMD_15h_Piledriver,
197	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
198	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
199	kCpumMicroarch_AMD_15h_Unknown,
200	kCpumMicroarch_AMD_15h_End,
201
202	kCpumMicroarch_AMD_16h_First,
203	kCpumMicroarch_AMD_16h_End,
204
205	kCpumMicroarch_AMD_Unknown,
206	kCpumMicroarch_AMD_End,
207
208	kCpumMicroarch_VIA_First,
209	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
210	kCpumMicroarch_Centaur_C2,
211	kCpumMicroarch_Centaur_C3,
212	kCpumMicroarch_VIA_C3_M2,
213	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
214	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
215	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
216	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
217	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
218	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
219	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
220	kCpumMicroarch_VIA_Isaiah,
221	kCpumMicroarch_VIA_Unknown,
222	kCpumMicroarch_VIA_End,
223
224	kCpumMicroarch_Cyrix_First,
225	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
226	kCpumMicroarch_Cyrix_M1,
227	kCpumMicroarch_Cyrix_MediaGX,
228	kCpumMicroarch_Cyrix_MediaGXm,
229	kCpumMicroarch_Cyrix_M2,
230	kCpumMicroarch_Cyrix_Unknown,
231	kCpumMicroarch_Cyrix_End,
232
233	kCpumMicroarch_Unknown,
234
235	kCpumMicroarch_32BitHack = 0x7fffffff
236	} CPUMMICROARCH;
237
238
239	/** Predicate macro for catching netburst CPUs. */
240	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
241	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
242
243	/** Predicate macro for catching Core7 CPUs. */
244	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
245	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
246
247	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
248	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
249	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
250
251	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
252	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
253
254	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
255	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
256
257	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
258	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
259
260	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
261	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
262
263	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
264	* decendants). */
265	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
266	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
267
268	/** Predicate macro for catching AMD Family 16H CPUs. */
269	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
270	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
271
272
273
274	/**
275	* CPUID leaf.
276	*
277	* @remarks This structure is used by the patch manager and is therefore
278	* more or less set in stone.
279	*/
280	typedef struct CPUMCPUIDLEAF
281	{
282	/** The leaf number. */
283	uint32_t uLeaf;
284	/** The sub-leaf number. */
285	uint32_t uSubLeaf;
286	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
287	uint32_t fSubLeafMask;
288
289	/** The EAX value. */
290	uint32_t uEax;
291	/** The EBX value. */
292	uint32_t uEbx;
293	/** The ECX value. */
294	uint32_t uEcx;
295	/** The EDX value. */
296	uint32_t uEdx;
297
298	/** Flags. */
299	uint32_t fFlags;
300	} CPUMCPUIDLEAF;
301	AssertCompileSize(CPUMCPUIDLEAF, 32);
302	/** Pointer to a CPUID leaf. */
303	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
304	/** Pointer to a const CPUID leaf. */
305	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
306
307	/** @name CPUMCPUIDLEAF::fFlags
308	* @{ */
309	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
310	* and EDX containing the extended APIC ID. */
311	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
312	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
313	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
314	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
315	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
316	/** Mask of the valid flags. */
317	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0x7)
318	/** @} */
319
320	/**
321	* Method used to deal with unknown CPUID leaves.
322	* @remarks Used in patch code.
323	*/
324	typedef enum CPUMUNKNOWNCPUID
325	{
326	/** Invalid zero value. */
327	CPUMUNKNOWNCPUID_INVALID = 0,
328	/** Use given default values (DefCpuId). */
329	CPUMUNKNOWNCPUID_DEFAULTS,
330	/** Return the last standard leaf.
331	* Intel Sandy Bridge has been observed doing this. */
332	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
333	/** Return the last standard leaf, with ecx observed.
334	* Intel Sandy Bridge has been observed doing this. */
335	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
336	/** The register values are passed thru unmodified. */
337	CPUMUNKNOWNCPUID_PASSTHRU,
338	/** End of valid value. */
339	CPUMUNKNOWNCPUID_END,
340	/** Ensure 32-bit type. */
341	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
342	} CPUMUNKNOWNCPUID;
343	/** Pointer to unknown CPUID leaf method. */
344	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
345
346
347	/**
348	* MSR read functions.
349	*/
350	typedef enum CPUMMSRRDFN
351	{
352	/** Invalid zero value. */
353	kCpumMsrRdFn_Invalid = 0,
354	/** Return the CPUMMSRRANGE::uValue. */
355	kCpumMsrRdFn_FixedValue,
356	/** Alias to the MSR range starting at the MSR given by
357	* CPUMMSRRANGE::uValue. Must be used in pair with
358	* kCpumMsrWrFn_MsrAlias. */
359	kCpumMsrRdFn_MsrAlias,
360	/** Write only register, GP all read attempts. */
361	kCpumMsrRdFn_WriteOnly,
362
363	kCpumMsrRdFn_Ia32P5McAddr,
364	kCpumMsrRdFn_Ia32P5McType,
365	kCpumMsrRdFn_Ia32TimestampCounter,
366	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
367	kCpumMsrRdFn_Ia32ApicBase,
368	kCpumMsrRdFn_Ia32FeatureControl,
369	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
370	kCpumMsrRdFn_Ia32SmmMonitorCtl,
371	kCpumMsrRdFn_Ia32PmcN,
372	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
373	kCpumMsrRdFn_Ia32MPerf,
374	kCpumMsrRdFn_Ia32APerf,
375	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
376	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
377	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
378	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
379	kCpumMsrRdFn_Ia32MtrrDefType,
380	kCpumMsrRdFn_Ia32Pat,
381	kCpumMsrRdFn_Ia32SysEnterCs,
382	kCpumMsrRdFn_Ia32SysEnterEsp,
383	kCpumMsrRdFn_Ia32SysEnterEip,
384	kCpumMsrRdFn_Ia32McgCap,
385	kCpumMsrRdFn_Ia32McgStatus,
386	kCpumMsrRdFn_Ia32McgCtl,
387	kCpumMsrRdFn_Ia32DebugCtl,
388	kCpumMsrRdFn_Ia32SmrrPhysBase,
389	kCpumMsrRdFn_Ia32SmrrPhysMask,
390	kCpumMsrRdFn_Ia32PlatformDcaCap,
391	kCpumMsrRdFn_Ia32CpuDcaCap,
392	kCpumMsrRdFn_Ia32Dca0Cap,
393	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
394	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
395	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
396	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
397	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
398	kCpumMsrRdFn_Ia32FixedCtrCtrl,
399	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
400	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
401	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
402	kCpumMsrRdFn_Ia32PebsEnable,
403	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
404	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
405	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
406	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
407	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
408	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
409	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
410	kCpumMsrRdFn_Ia32DsArea,
411	kCpumMsrRdFn_Ia32TscDeadline,
412	kCpumMsrRdFn_Ia32X2ApicN,
413	kCpumMsrRdFn_Ia32DebugInterface,
414	kCpumMsrRdFn_Ia32VmxBase, /*< Takes real value as reference. /
415	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
416	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
417	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
418	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
419	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
420	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
421	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
422	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
423	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
424	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
425	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
426	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
427	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
428	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
429	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
430	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
431
432	kCpumMsrRdFn_Amd64Efer,
433	kCpumMsrRdFn_Amd64SyscallTarget,
434	kCpumMsrRdFn_Amd64LongSyscallTarget,
435	kCpumMsrRdFn_Amd64CompSyscallTarget,
436	kCpumMsrRdFn_Amd64SyscallFlagMask,
437	kCpumMsrRdFn_Amd64FsBase,
438	kCpumMsrRdFn_Amd64GsBase,
439	kCpumMsrRdFn_Amd64KernelGsBase,
440	kCpumMsrRdFn_Amd64TscAux,
441
442	kCpumMsrRdFn_IntelEblCrPowerOn,
443	kCpumMsrRdFn_IntelI7CoreThreadCount,
444	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
445	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
446	kCpumMsrRdFn_IntelP4EbcFrequencyId,
447	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
448	kCpumMsrRdFn_IntelPlatformInfo,
449	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
450	kCpumMsrRdFn_IntelPkgCStConfigControl,
451	kCpumMsrRdFn_IntelPmgIoCaptureBase,
452	kCpumMsrRdFn_IntelLastBranchFromToN,
453	kCpumMsrRdFn_IntelLastBranchFromN,
454	kCpumMsrRdFn_IntelLastBranchToN,
455	kCpumMsrRdFn_IntelLastBranchTos,
456	kCpumMsrRdFn_IntelBblCrCtl,
457	kCpumMsrRdFn_IntelBblCrCtl3,
458	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
459	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
460	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
461	kCpumMsrRdFn_IntelP6CrN,
462	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
463	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
464	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
465	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
466	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
467	kCpumMsrRdFn_IntelI7LbrSelect,
468	kCpumMsrRdFn_IntelI7SandyErrorControl,
469	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
470	kCpumMsrRdFn_IntelI7PowerCtl,
471	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
472	kCpumMsrRdFn_IntelI7PebsLdLat,
473	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
474	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
475	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
476	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
477	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
478	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
479	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
480	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
481	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
482	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
483	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
484	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
485	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
486	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
487	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
488	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
489	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
490	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
491	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
492	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
493	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
494	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
495	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
496	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
497	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
498	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
499	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
500	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
501	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
502	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
503	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
504	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
505	kCpumMsrRdFn_IntelI7UncCBoxConfig,
506	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
507	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
508	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
509	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
510	kCpumMsrRdFn_IntelCore1ExtConfig,
511	kCpumMsrRdFn_IntelCore1DtsCalControl,
512	kCpumMsrRdFn_IntelCore2PeciControl,
513
514	kCpumMsrRdFn_P6LastBranchFromIp,
515	kCpumMsrRdFn_P6LastBranchToIp,
516	kCpumMsrRdFn_P6LastIntFromIp,
517	kCpumMsrRdFn_P6LastIntToIp,
518
519	kCpumMsrRdFn_AmdFam15hTscRate,
520	kCpumMsrRdFn_AmdFam15hLwpCfg,
521	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
522	kCpumMsrRdFn_AmdFam10hMc4MiscN,
523	kCpumMsrRdFn_AmdK8PerfCtlN,
524	kCpumMsrRdFn_AmdK8PerfCtrN,
525	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
526	kCpumMsrRdFn_AmdK8HwCr,
527	kCpumMsrRdFn_AmdK8IorrBaseN,
528	kCpumMsrRdFn_AmdK8IorrMaskN,
529	kCpumMsrRdFn_AmdK8TopOfMemN,
530	kCpumMsrRdFn_AmdK8NbCfg1,
531	kCpumMsrRdFn_AmdK8McXcptRedir,
532	kCpumMsrRdFn_AmdK8CpuNameN,
533	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
534	kCpumMsrRdFn_AmdK8SwThermalCtrl,
535	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
536	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
537	kCpumMsrRdFn_AmdK8McCtlMaskN,
538	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
539	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
540	kCpumMsrRdFn_AmdK8IntPendingMessage,
541	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
542	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
543	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
544	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
545	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
546	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
547	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
548	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
549	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
550	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
551	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
552	kCpumMsrRdFn_AmdK8SmmBase,
553	kCpumMsrRdFn_AmdK8SmmAddr,
554	kCpumMsrRdFn_AmdK8SmmMask,
555	kCpumMsrRdFn_AmdK8VmCr,
556	kCpumMsrRdFn_AmdK8IgnNe,
557	kCpumMsrRdFn_AmdK8SmmCtl,
558	kCpumMsrRdFn_AmdK8VmHSavePa,
559	kCpumMsrRdFn_AmdFam10hVmLockKey,
560	kCpumMsrRdFn_AmdFam10hSmmLockKey,
561	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
562	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
563	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
564	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
565	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
566	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
567	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
568	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
569	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
570	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
571	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
572	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
573	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
574	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
575	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
576	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
577	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
578	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
579	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
580	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
581	kCpumMsrRdFn_AmdK7NodeId,
582	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
583	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
584	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
585	kCpumMsrRdFn_AmdK7LoadStoreCfg,
586	kCpumMsrRdFn_AmdK7InstrCacheCfg,
587	kCpumMsrRdFn_AmdK7DataCacheCfg,
588	kCpumMsrRdFn_AmdK7BusUnitCfg,
589	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
590	kCpumMsrRdFn_AmdFam15hFpuCfg,
591	kCpumMsrRdFn_AmdFam15hDecoderCfg,
592	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
593	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
594	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
595	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
596	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
597	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
598	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
599	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
600	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
601	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
602	kCpumMsrRdFn_AmdFam10hIbsOpRip,
603	kCpumMsrRdFn_AmdFam10hIbsOpData,
604	kCpumMsrRdFn_AmdFam10hIbsOpData2,
605	kCpumMsrRdFn_AmdFam10hIbsOpData3,
606	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
607	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
608	kCpumMsrRdFn_AmdFam10hIbsCtl,
609	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
610
611	kCpumMsrRdFn_Gim,
612
613	/** End of valid MSR read function indexes. */
614	kCpumMsrRdFn_End
615	} CPUMMSRRDFN;
616
617	/**
618	* MSR write functions.
619	*/
620	typedef enum CPUMMSRWRFN
621	{
622	/** Invalid zero value. */
623	kCpumMsrWrFn_Invalid = 0,
624	/** Writes are ignored, the fWrGpMask is observed though. */
625	kCpumMsrWrFn_IgnoreWrite,
626	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
627	kCpumMsrWrFn_ReadOnly,
628	/** Alias to the MSR range starting at the MSR given by
629	* CPUMMSRRANGE::uValue. Must be used in pair with
630	* kCpumMsrRdFn_MsrAlias. */
631	kCpumMsrWrFn_MsrAlias,
632
633	kCpumMsrWrFn_Ia32P5McAddr,
634	kCpumMsrWrFn_Ia32P5McType,
635	kCpumMsrWrFn_Ia32TimestampCounter,
636	kCpumMsrWrFn_Ia32ApicBase,
637	kCpumMsrWrFn_Ia32FeatureControl,
638	kCpumMsrWrFn_Ia32BiosSignId,
639	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
640	kCpumMsrWrFn_Ia32SmmMonitorCtl,
641	kCpumMsrWrFn_Ia32PmcN,
642	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
643	kCpumMsrWrFn_Ia32MPerf,
644	kCpumMsrWrFn_Ia32APerf,
645	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
646	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
647	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
648	kCpumMsrWrFn_Ia32MtrrDefType,
649	kCpumMsrWrFn_Ia32Pat,
650	kCpumMsrWrFn_Ia32SysEnterCs,
651	kCpumMsrWrFn_Ia32SysEnterEsp,
652	kCpumMsrWrFn_Ia32SysEnterEip,
653	kCpumMsrWrFn_Ia32McgStatus,
654	kCpumMsrWrFn_Ia32McgCtl,
655	kCpumMsrWrFn_Ia32DebugCtl,
656	kCpumMsrWrFn_Ia32SmrrPhysBase,
657	kCpumMsrWrFn_Ia32SmrrPhysMask,
658	kCpumMsrWrFn_Ia32PlatformDcaCap,
659	kCpumMsrWrFn_Ia32Dca0Cap,
660	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
661	kCpumMsrWrFn_Ia32PerfStatus,
662	kCpumMsrWrFn_Ia32PerfCtl,
663	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
664	kCpumMsrWrFn_Ia32PerfCapabilities,
665	kCpumMsrWrFn_Ia32FixedCtrCtrl,
666	kCpumMsrWrFn_Ia32PerfGlobalStatus,
667	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
668	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
669	kCpumMsrWrFn_Ia32PebsEnable,
670	kCpumMsrWrFn_Ia32ClockModulation,
671	kCpumMsrWrFn_Ia32ThermInterrupt,
672	kCpumMsrWrFn_Ia32ThermStatus,
673	kCpumMsrWrFn_Ia32Therm2Ctl,
674	kCpumMsrWrFn_Ia32MiscEnable,
675	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
676	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
677	kCpumMsrWrFn_Ia32DsArea,
678	kCpumMsrWrFn_Ia32TscDeadline,
679	kCpumMsrWrFn_Ia32X2ApicN,
680	kCpumMsrWrFn_Ia32DebugInterface,
681
682	kCpumMsrWrFn_Amd64Efer,
683	kCpumMsrWrFn_Amd64SyscallTarget,
684	kCpumMsrWrFn_Amd64LongSyscallTarget,
685	kCpumMsrWrFn_Amd64CompSyscallTarget,
686	kCpumMsrWrFn_Amd64SyscallFlagMask,
687	kCpumMsrWrFn_Amd64FsBase,
688	kCpumMsrWrFn_Amd64GsBase,
689	kCpumMsrWrFn_Amd64KernelGsBase,
690	kCpumMsrWrFn_Amd64TscAux,
691	kCpumMsrWrFn_IntelEblCrPowerOn,
692	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
693	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
694	kCpumMsrWrFn_IntelP4EbcFrequencyId,
695	kCpumMsrWrFn_IntelFlexRatio,
696	kCpumMsrWrFn_IntelPkgCStConfigControl,
697	kCpumMsrWrFn_IntelPmgIoCaptureBase,
698	kCpumMsrWrFn_IntelLastBranchFromToN,
699	kCpumMsrWrFn_IntelLastBranchFromN,
700	kCpumMsrWrFn_IntelLastBranchToN,
701	kCpumMsrWrFn_IntelLastBranchTos,
702	kCpumMsrWrFn_IntelBblCrCtl,
703	kCpumMsrWrFn_IntelBblCrCtl3,
704	kCpumMsrWrFn_IntelI7TemperatureTarget,
705	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
706	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
707	kCpumMsrWrFn_IntelP6CrN,
708	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
709	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
710	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
711	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
712	kCpumMsrWrFn_IntelI7TurboRatioLimit,
713	kCpumMsrWrFn_IntelI7LbrSelect,
714	kCpumMsrWrFn_IntelI7SandyErrorControl,
715	kCpumMsrWrFn_IntelI7PowerCtl,
716	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
717	kCpumMsrWrFn_IntelI7PebsLdLat,
718	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
719	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
720	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
721	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
722	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
723	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
724	kCpumMsrWrFn_IntelI7RaplPp0Policy,
725	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
726	kCpumMsrWrFn_IntelI7RaplPp1Policy,
727	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
728	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
729	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
730	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
731	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
732	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
733	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
734	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
735	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
736	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
737	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
738	kCpumMsrWrFn_IntelCore1ExtConfig,
739	kCpumMsrWrFn_IntelCore1DtsCalControl,
740	kCpumMsrWrFn_IntelCore2PeciControl,
741
742	kCpumMsrWrFn_P6LastIntFromIp,
743	kCpumMsrWrFn_P6LastIntToIp,
744
745	kCpumMsrWrFn_AmdFam15hTscRate,
746	kCpumMsrWrFn_AmdFam15hLwpCfg,
747	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
748	kCpumMsrWrFn_AmdFam10hMc4MiscN,
749	kCpumMsrWrFn_AmdK8PerfCtlN,
750	kCpumMsrWrFn_AmdK8PerfCtrN,
751	kCpumMsrWrFn_AmdK8SysCfg,
752	kCpumMsrWrFn_AmdK8HwCr,
753	kCpumMsrWrFn_AmdK8IorrBaseN,
754	kCpumMsrWrFn_AmdK8IorrMaskN,
755	kCpumMsrWrFn_AmdK8TopOfMemN,
756	kCpumMsrWrFn_AmdK8NbCfg1,
757	kCpumMsrWrFn_AmdK8McXcptRedir,
758	kCpumMsrWrFn_AmdK8CpuNameN,
759	kCpumMsrWrFn_AmdK8HwThermalCtrl,
760	kCpumMsrWrFn_AmdK8SwThermalCtrl,
761	kCpumMsrWrFn_AmdK8FidVidControl,
762	kCpumMsrWrFn_AmdK8McCtlMaskN,
763	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
764	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
765	kCpumMsrWrFn_AmdK8IntPendingMessage,
766	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
767	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
768	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
769	kCpumMsrWrFn_AmdFam10hPStateControl,
770	kCpumMsrWrFn_AmdFam10hPStateStatus,
771	kCpumMsrWrFn_AmdFam10hPStateN,
772	kCpumMsrWrFn_AmdFam10hCofVidControl,
773	kCpumMsrWrFn_AmdFam10hCofVidStatus,
774	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
775	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
776	kCpumMsrWrFn_AmdK8SmmBase,
777	kCpumMsrWrFn_AmdK8SmmAddr,
778	kCpumMsrWrFn_AmdK8SmmMask,
779	kCpumMsrWrFn_AmdK8VmCr,
780	kCpumMsrWrFn_AmdK8IgnNe,
781	kCpumMsrWrFn_AmdK8SmmCtl,
782	kCpumMsrWrFn_AmdK8VmHSavePa,
783	kCpumMsrWrFn_AmdFam10hVmLockKey,
784	kCpumMsrWrFn_AmdFam10hSmmLockKey,
785	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
786	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
787	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
788	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
789	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
790	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
791	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
792	kCpumMsrWrFn_AmdK7MicrocodeCtl,
793	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
794	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
795	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
796	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
797	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
798	kCpumMsrWrFn_AmdK8PatchLoader,
799	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
800	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
801	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
802	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
803	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
804	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
805	kCpumMsrWrFn_AmdK7NodeId,
806	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
807	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
808	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
809	kCpumMsrWrFn_AmdK7LoadStoreCfg,
810	kCpumMsrWrFn_AmdK7InstrCacheCfg,
811	kCpumMsrWrFn_AmdK7DataCacheCfg,
812	kCpumMsrWrFn_AmdK7BusUnitCfg,
813	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
814	kCpumMsrWrFn_AmdFam15hFpuCfg,
815	kCpumMsrWrFn_AmdFam15hDecoderCfg,
816	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
817	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
818	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
819	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
820	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
821	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
822	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
823	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
824	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
825	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
826	kCpumMsrWrFn_AmdFam10hIbsOpRip,
827	kCpumMsrWrFn_AmdFam10hIbsOpData,
828	kCpumMsrWrFn_AmdFam10hIbsOpData2,
829	kCpumMsrWrFn_AmdFam10hIbsOpData3,
830	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
831	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
832	kCpumMsrWrFn_AmdFam10hIbsCtl,
833	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
834
835	kCpumMsrWrFn_Gim,
836
837	/** End of valid MSR write function indexes. */
838	kCpumMsrWrFn_End
839	} CPUMMSRWRFN;
840
841	/**
842	* MSR range.
843	*/
844	typedef struct CPUMMSRRANGE
845	{
846	/** The first MSR. [0] */
847	uint32_t uFirst;
848	/** The last MSR. [4] */
849	uint32_t uLast;
850	/** The read function (CPUMMSRRDFN). [8] */
851	uint16_t enmRdFn;
852	/** The write function (CPUMMSRWRFN). [10] */
853	uint16_t enmWrFn;
854	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
855	* UINT16_MAX if not used by the read and write functions. [12] */
856	uint16_t offCpumCpu;
857	/** Reserved for future hacks. [14] */
858	uint16_t fReserved;
859	/** The init/read value. [16]
860	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
861	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
862	* offset into CPUM. */
863	uint64_t uValue;
864	/** The bits to ignore when writing. [24] */
865	uint64_t fWrIgnMask;
866	/** The bits that will cause a GP(0) when writing. [32]
867	* This is always checked prior to calling the write function. Using
868	* UINT64_MAX effectively marks the MSR as read-only. */
869	uint64_t fWrGpMask;
870	/** The register name, if applicable. [40] */
871	char szName[56];
872
873	#ifdef VBOX_WITH_STATISTICS
874	/** The number of reads. */
875	STAMCOUNTER cReads;
876	/** The number of writes. */
877	STAMCOUNTER cWrites;
878	/** The number of times ignored bits were written. */
879	STAMCOUNTER cIgnoredBits;
880	/** The number of GPs generated. */
881	STAMCOUNTER cGps;
882	#endif
883	} CPUMMSRRANGE;
884	#ifdef VBOX_WITH_STATISTICS
885	AssertCompileSize(CPUMMSRRANGE, 128);
886	#else
887	AssertCompileSize(CPUMMSRRANGE, 96);
888	#endif
889	/** Pointer to an MSR range. */
890	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
891	/** Pointer to a const MSR range. */
892	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
893
894
895	/**
896	* CPU features and quirks.
897	* This is mostly exploded CPUID info.
898	*/
899	typedef struct CPUMFEATURES
900	{
901	/** The CPU vendor (CPUMCPUVENDOR). */
902	uint8_t enmCpuVendor;
903	/** The CPU family. */
904	uint8_t uFamily;
905	/** The CPU model. */
906	uint8_t uModel;
907	/** The CPU stepping. */
908	uint8_t uStepping;
909	/** The microarchitecture. */
910	#ifndef VBOX_FOR_DTRACE_LIB
911	CPUMMICROARCH enmMicroarch;
912	#else
913	uint32_t enmMicroarch;
914	#endif
915	/** The maximum physical address with of the CPU. */
916	uint8_t cMaxPhysAddrWidth;
917	/** Alignment padding. */
918	uint8_t abPadding[1];
919	/** Max size of the extended state (or FPU state if no XSAVE). */
920	uint16_t cbMaxExtendedState;
921
922	/** Supports MSRs. */
923	uint32_t fMsr : 1;
924	/** Supports the page size extension (4/2 MB pages). */
925	uint32_t fPse : 1;
926	/** Supports 36-bit page size extension (4 MB pages can map memory above
927	* 4GB). */
928	uint32_t fPse36 : 1;
929	/** Supports physical address extension (PAE). */
930	uint32_t fPae : 1;
931	/** Page attribute table (PAT) support (page level cache control). */
932	uint32_t fPat : 1;
933	/** Supports the FXSAVE and FXRSTOR instructions. */
934	uint32_t fFxSaveRstor : 1;
935	/** Supports the XSAVE and XRSTOR instructions. */
936	uint32_t fXSaveRstor : 1;
937	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
938	uint32_t fOpSysXSaveRstor : 1;
939	/** Supports MMX. */
940	uint32_t fMmx : 1;
941	/** Supports AMD extensions to MMX instructions. */
942	uint32_t fAmdMmxExts : 1;
943	/** Supports SSE. */
944	uint32_t fSse : 1;
945	/** Supports SSE2. */
946	uint32_t fSse2 : 1;
947	/** Supports SSE3. */
948	uint32_t fSse3 : 1;
949	/** Supports SSSE3. */
950	uint32_t fSsse3 : 1;
951	/** Supports SSE4.1. */
952	uint32_t fSse41 : 1;
953	/** Supports SSE4.2. */
954	uint32_t fSse42 : 1;
955	/** Supports AVX. */
956	uint32_t fAvx : 1;
957	/** Supports AVX2. */
958	uint32_t fAvx2 : 1;
959	/** Supports AVX512 foundation. */
960	uint32_t fAvx512Foundation : 1;
961	/** Supports RDTSC. */
962	uint32_t fTsc : 1;
963	/** Intel SYSENTER/SYSEXIT support */
964	uint32_t fSysEnter : 1;
965	/** First generation APIC. */
966	uint32_t fApic : 1;
967	/** Second generation APIC. */
968	uint32_t fX2Apic : 1;
969	/** Hypervisor present. */
970	uint32_t fHypervisorPresent : 1;
971	/** MWAIT & MONITOR instructions supported. */
972	uint32_t fMonitorMWait : 1;
973	/** MWAIT Extensions present. */
974	uint32_t fMWaitExtensions : 1;
975
976	/** Supports AMD 3DNow instructions. */
977	uint32_t f3DNow : 1;
978	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
979	uint32_t f3DNowPrefetch : 1;
980
981	/** AMD64: Supports long mode. */
982	uint32_t fLongMode : 1;
983	/** AMD64: SYSCALL/SYSRET support. */
984	uint32_t fSysCall : 1;
985	/** AMD64: No-execute page table bit. */
986	uint32_t fNoExecute : 1;
987	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
988	uint32_t fLahfSahf : 1;
989	/** AMD64: Supports RDTSCP. */
990	uint32_t fRdTscP : 1;
991	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
992	uint32_t fMovCr8In32Bit : 1;
993
994	/** Indicates that FPU instruction and data pointers may leak.
995	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
996	* is only saved and restored if an exception is pending. */
997	uint32_t fLeakyFxSR : 1;
998
999	/** Alignment padding / reserved for future use. */
1000	uint32_t fPadding : 29;
1001	uint32_t auPadding[3];
1002	} CPUMFEATURES;
1003	#ifndef VBOX_FOR_DTRACE_LIB
1004	AssertCompileSize(CPUMFEATURES, 32);
1005	#endif
1006	/** Pointer to a CPU feature structure. */
1007	typedef CPUMFEATURES *PCPUMFEATURES;
1008	/** Pointer to a const CPU feature structure. */
1009	typedef CPUMFEATURES const *PCCPUMFEATURES;
1010
1011
1012
1013	/** @name Guest Register Getters.
1014	* @{ */
1015	VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1016	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1017	VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1018	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1019	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
1020	VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1021	VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1022	VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1023	VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1024	VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1025	VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1026	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1027	VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1028	VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1029	VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1030	VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1031	VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1032	VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1033	VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1034	VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1035	VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1036	VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1037	VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1038	VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1039	VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1040	VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1041	VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1042	VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1043	VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1044	VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1045	VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1046	VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1047	VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1048	VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1049	VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1050	VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1051	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
1052	VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1053	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1054	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1055	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1056	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1057	/** @} */
1058
1059	/** @name Guest Register Setters.
1060	* @{ */
1061	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1062	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1063	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1064	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1065	VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1066	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1067	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1068	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1069	VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1070	VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1071	VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1072	VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1073	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1074	VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1075	VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1076	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1077	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1078	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1079	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1080	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1081	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1082	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1083	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1084	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1085	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1086	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1087	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1088	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1089	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1090	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1091	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1092	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1093	VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1094	VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1095	VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1096	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1097	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1098	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1099	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1100	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
1101	/** @} */
1102
1103
1104	/** @name Misc Guest Predicate Functions.
1105	* @{ */
1106
1107	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1108	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1109	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1110	VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1111	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1112	VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1113	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1114	VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1115	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1116	VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1117	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1118	VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1119	VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1120	VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1121
1122	#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
1123
1124	/**
1125	* Tests if the guest is running in real mode or not.
1126	*
1127	* @returns true if in real mode, otherwise false.
1128	* @param pCtx Current CPU context
1129	*/
1130	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1131	{
1132	return !(pCtx->cr0 & X86_CR0_PE);
1133	}
1134
1135	/**
1136	* Tests if the guest is running in real or virtual 8086 mode.
1137	*
1138	* @returns @c true if it is, @c false if not.
1139	* @param pCtx Current CPU context
1140	*/
1141	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1142	{
1143	return !(pCtx->cr0 & X86_CR0_PE)
1144	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1145	}
1146
1147	/**
1148	* Tests if the guest is running in virtual 8086 mode.
1149	*
1150	* @returns @c true if it is, @c false if not.
1151	* @param pCtx Current CPU context
1152	*/
1153	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1154	{
1155	return (pCtx->eflags.Bits.u1VM == 1);
1156	}
1157
1158	/**
1159	* Tests if the guest is running in paged protected or not.
1160	*
1161	* @returns true if in paged protected mode, otherwise false.
1162	* @param pVM The VM handle.
1163	*/
1164	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1165	{
1166	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1167	}
1168
1169	/**
1170	* Tests if the guest is running in long mode or not.
1171	*
1172	* @returns true if in long mode, otherwise false.
1173	* @param pCtx Current CPU context
1174	*/
1175	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1176	{
1177	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1178	}
1179
1180	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1181
1182	/**
1183	* Tests if the guest is running in 64 bits mode or not.
1184	*
1185	* @returns true if in 64 bits protected mode, otherwise false.
1186	* @param pVCpu The current virtual CPU.
1187	* @param pCtx Current CPU context
1188	*/
1189	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1190	{
1191	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1192	return false;
1193	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1194	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1195	return pCtx->cs.Attr.n.u1Long;
1196	}
1197
1198	/**
1199	* Tests if the guest has paging enabled or not.
1200	*
1201	* @returns true if paging is enabled, otherwise false.
1202	* @param pCtx Current CPU context
1203	*/
1204	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1205	{
1206	return !!(pCtx->cr0 & X86_CR0_PG);
1207	}
1208
1209	/**
1210	* Tests if the guest is running in PAE mode or not.
1211	*
1212	* @returns true if in PAE mode, otherwise false.
1213	* @param pCtx Current CPU context
1214	*/
1215	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1216	{
1217	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1218	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1219	return ( (pCtx->cr4 & X86_CR4_PAE)
1220	&& CPUMIsGuestPagingEnabledEx(pCtx)
1221	&& !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1222	}
1223
1224	#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
1225
1226	/** @} */
1227
1228
1229	/** @name Hypervisor Register Getters.
1230	* @{ */
1231	VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1232	VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1233	VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1234	VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1235	VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1236	VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1237	#if 0 /* these are not correct. */
1238	VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1239	VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1240	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1241	VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1242	#endif
1243	/** This register is only saved on fatal traps. */
1244	VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1245	VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1246	/** This register is only saved on fatal traps. */
1247	VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1248	/** This register is only saved on fatal traps. */
1249	VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1250	VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1251	VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1252	VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1253	VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1254	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1255	VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1256	VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1257	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1258	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1259	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1260	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1261	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1262	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1263	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1264	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1265	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1266	VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1267	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1268	/** @} */
1269
1270	/** @name Hypervisor Register Setters.
1271	* @{ */
1272	VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1273	VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1274	VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1275	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1276	VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1277	VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1278	VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1279	VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1280	VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1281	VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1282	VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1283	VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1284	VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1285	VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1286	VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1287	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1288	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1289	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1290	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1291	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1292	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1293	VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1294	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1295	/** @} */
1296
1297	VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1298	VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1299	VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1300	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1301	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1302	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1303	VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1304	VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1305	VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1306	VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1307
1308	/** @name Changed flags.
1309	* These flags are used to keep track of which important register that
1310	* have been changed since last they were reset. The only one allowed
1311	* to clear them is REM!
1312	* @{
1313	*/
1314	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1315	#define CPUM_CHANGED_CR0 RT_BIT(1)
1316	#define CPUM_CHANGED_CR4 RT_BIT(2)
1317	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1318	#define CPUM_CHANGED_CR3 RT_BIT(4)
1319	#define CPUM_CHANGED_GDTR RT_BIT(5)
1320	#define CPUM_CHANGED_IDTR RT_BIT(6)
1321	#define CPUM_CHANGED_LDTR RT_BIT(7)
1322	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
1323	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1324	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
1325	#define CPUM_CHANGED_CPUID RT_BIT(11)
1326	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1327	\| CPUM_CHANGED_CR0 \
1328	\| CPUM_CHANGED_CR4 \
1329	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1330	\| CPUM_CHANGED_CR3 \
1331	\| CPUM_CHANGED_GDTR \
1332	\| CPUM_CHANGED_IDTR \
1333	\| CPUM_CHANGED_LDTR \
1334	\| CPUM_CHANGED_TR \
1335	\| CPUM_CHANGED_SYSENTER_MSR \
1336	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
1337	\| CPUM_CHANGED_CPUID )
1338	/** @} */
1339
1340	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
1341	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1342	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1343	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
1344	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1345	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1346	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1347	VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
1348	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1349	VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1350	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1351	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1352	VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1353	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1354	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1355	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1356	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1357	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1358
1359	/** @name Typical scalable bus frequency values.
1360	* @{ */
1361	/** Special internal value indicating that we don't know the frequency.
1362	* @internal */
1363	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1364	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1365	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1366	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1367	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1368	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1369	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1370	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1371	/** @} */
1372
1373
1374	#ifdef IN_RING3
1375	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1376	* @{
1377	*/
1378
1379	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1380	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM);
1381	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1382	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1383	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1384	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1385	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1386	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1387	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1388	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1389
1390	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1391	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1392	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1393	uint8_t bModel, uint8_t bStepping);
1394	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1395	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1396	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1397	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1398	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1399	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1400
1401	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1402
1403	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
1404	/** @name APIs for the CPUID raw-mode patch (legacy).
1405	* @{ */
1406	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1407	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1408	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1409	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1410	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1411	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1412	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1413	/** @} */
1414	# endif
1415
1416	/** @} */
1417	#endif /* IN_RING3 */
1418
1419	#ifdef IN_RC
1420	/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1421	* @{
1422	*/
1423
1424	/**
1425	* Calls a guest trap/interrupt handler directly
1426	*
1427	* Assumes a trap stack frame has already been setup on the guest's stack!
1428	* This function does not return!
1429	*
1430	* @param pRegFrame Original trap/interrupt context
1431	* @param selCS Code selector of handler
1432	* @param pHandler GC virtual address of handler
1433	* @param eflags Callee's EFLAGS
1434	* @param selSS Stack selector for handler
1435	* @param pEsp Stack address for handler
1436	*/
1437	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1438	uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1439
1440	/**
1441	* Call guest V86 code directly.
1442	*
1443	* This function does not return!
1444	*
1445	* @param pRegFrame Original trap/interrupt context
1446	*/
1447	DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1448
1449	VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1450	VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1451	#ifdef VBOX_WITH_RAW_RING1
1452	VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1453	#endif
1454
1455	/** @} */
1456	#endif /* IN_RC */
1457
1458	#ifdef IN_RING0
1459	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1460	* @{
1461	*/
1462	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1463	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1464	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1465	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1466	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1467	VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1468	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1469	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1470	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1471
1472	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1473	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1474	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1475	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1476	#endif
1477
1478	/** @} */
1479	#endif /* IN_RING0 */
1480
1481	/** @} */
1482	RT_C_DECLS_END
1483
1484
1485	#endif
1486

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 55254

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