VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 76823

Last change on this file since 76823 was 76678, checked in by vboxsync, 6 years ago

Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_cpum_h
27#define VBOX_INCLUDED_vmm_cpum_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <iprt/x86.h>
33#include <VBox/types.h>
34#include <VBox/vmm/cpumctx.h>
35#include <VBox/vmm/stam.h>
36#include <VBox/vmm/vmapi.h>
37#include <VBox/vmm/hm_svm.h>
38#include <VBox/vmm/hm_vmx.h>
39
40RT_C_DECLS_BEGIN
41
42/** @defgroup grp_cpum The CPU Monitor / Manager API
43 * @ingroup grp_vmm
44 * @{
45 */
46
47/**
48 * CPUID feature to set or clear.
49 */
50typedef enum CPUMCPUIDFEATURE
51{
52 CPUMCPUIDFEATURE_INVALID = 0,
53 /** The APIC feature bit. (Std+Ext)
54 * Note! There is a per-cpu flag for masking this CPUID feature bit when the
55 * APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
56 * at VM construction time like all the others. This didn't used to be
57 * that way, this is new with 5.1. */
58 CPUMCPUIDFEATURE_APIC,
59 /** The sysenter/sysexit feature bit. (Std) */
60 CPUMCPUIDFEATURE_SEP,
61 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
62 CPUMCPUIDFEATURE_SYSCALL,
63 /** The PAE feature bit. (Std+Ext) */
64 CPUMCPUIDFEATURE_PAE,
65 /** The NX feature bit. (Ext) */
66 CPUMCPUIDFEATURE_NX,
67 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
68 CPUMCPUIDFEATURE_LAHF,
69 /** The LONG MODE feature bit. (Ext) */
70 CPUMCPUIDFEATURE_LONG_MODE,
71 /** The PAT feature bit. (Std+Ext) */
72 CPUMCPUIDFEATURE_PAT,
73 /** The x2APIC feature bit. (Std) */
74 CPUMCPUIDFEATURE_X2APIC,
75 /** The RDTSCP feature bit. (Ext) */
76 CPUMCPUIDFEATURE_RDTSCP,
77 /** The Hypervisor Present bit. (Std) */
78 CPUMCPUIDFEATURE_HVP,
79 /** The MWait Extensions bits (Std) */
80 CPUMCPUIDFEATURE_MWAIT_EXTS,
81 /** The speculation control feature bits. (StExt) */
82 CPUMCPUIDFEATURE_SPEC_CTRL,
83 /** 32bit hackishness. */
84 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
85} CPUMCPUIDFEATURE;
86
87/**
88 * CPU Vendor.
89 */
90typedef enum CPUMCPUVENDOR
91{
92 CPUMCPUVENDOR_INVALID = 0,
93 CPUMCPUVENDOR_INTEL,
94 CPUMCPUVENDOR_AMD,
95 CPUMCPUVENDOR_VIA,
96 CPUMCPUVENDOR_CYRIX,
97 CPUMCPUVENDOR_UNKNOWN,
98 /** 32bit hackishness. */
99 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
100} CPUMCPUVENDOR;
101
102
103/**
104 * X86 and AMD64 CPU microarchitectures and in processor generations.
105 *
106 * @remarks The separation here is sometimes a little bit too finely grained,
107 * and the differences is more like processor generation than micro
108 * arch. This can be useful, so we'll provide functions for getting at
109 * more coarse grained info.
110 */
111typedef enum CPUMMICROARCH
112{
113 kCpumMicroarch_Invalid = 0,
114
115 kCpumMicroarch_Intel_First,
116
117 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
118 kCpumMicroarch_Intel_80186,
119 kCpumMicroarch_Intel_80286,
120 kCpumMicroarch_Intel_80386,
121 kCpumMicroarch_Intel_80486,
122 kCpumMicroarch_Intel_P5,
123
124 kCpumMicroarch_Intel_P6_Core_Atom_First,
125 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
126 kCpumMicroarch_Intel_P6_II,
127 kCpumMicroarch_Intel_P6_III,
128
129 kCpumMicroarch_Intel_P6_M_Banias,
130 kCpumMicroarch_Intel_P6_M_Dothan,
131 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
132
133 kCpumMicroarch_Intel_Core2_First,
134 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
135 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
136 kCpumMicroarch_Intel_Core2_End,
137
138 kCpumMicroarch_Intel_Core7_First,
139 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
140 kCpumMicroarch_Intel_Core7_Westmere,
141 kCpumMicroarch_Intel_Core7_SandyBridge,
142 kCpumMicroarch_Intel_Core7_IvyBridge,
143 kCpumMicroarch_Intel_Core7_Haswell,
144 kCpumMicroarch_Intel_Core7_Broadwell,
145 kCpumMicroarch_Intel_Core7_Skylake,
146 kCpumMicroarch_Intel_Core7_KabyLake,
147 kCpumMicroarch_Intel_Core7_CoffeeLake,
148 kCpumMicroarch_Intel_Core7_CannonLake,
149 kCpumMicroarch_Intel_Core7_IceLake,
150 kCpumMicroarch_Intel_Core7_TigerLake,
151 kCpumMicroarch_Intel_Core7_End,
152
153 kCpumMicroarch_Intel_Atom_First,
154 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
155 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
156 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
157 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
158 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
159 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
160 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
161 kCpumMicroarch_Intel_Atom_Unknown,
162 kCpumMicroarch_Intel_Atom_End,
163
164
165 kCpumMicroarch_Intel_Phi_First,
166 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
167 kCpumMicroarch_Intel_Phi_KnightsCorner,
168 kCpumMicroarch_Intel_Phi_KnightsLanding,
169 kCpumMicroarch_Intel_Phi_KnightsHill,
170 kCpumMicroarch_Intel_Phi_KnightsMill,
171 kCpumMicroarch_Intel_Phi_End,
172
173 kCpumMicroarch_Intel_P6_Core_Atom_End,
174
175 kCpumMicroarch_Intel_NB_First,
176 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
177 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
178 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
179 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
180 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
181 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
182 kCpumMicroarch_Intel_NB_Unknown,
183 kCpumMicroarch_Intel_NB_End,
184
185 kCpumMicroarch_Intel_Unknown,
186 kCpumMicroarch_Intel_End,
187
188 kCpumMicroarch_AMD_First,
189 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
190 kCpumMicroarch_AMD_Am386,
191 kCpumMicroarch_AMD_Am486,
192 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
193 kCpumMicroarch_AMD_K5,
194 kCpumMicroarch_AMD_K6,
195
196 kCpumMicroarch_AMD_K7_First,
197 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
198 kCpumMicroarch_AMD_K7_Spitfire,
199 kCpumMicroarch_AMD_K7_Thunderbird,
200 kCpumMicroarch_AMD_K7_Morgan,
201 kCpumMicroarch_AMD_K7_Thoroughbred,
202 kCpumMicroarch_AMD_K7_Barton,
203 kCpumMicroarch_AMD_K7_Unknown,
204 kCpumMicroarch_AMD_K7_End,
205
206 kCpumMicroarch_AMD_K8_First,
207 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
208 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
209 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
210 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
211 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
212 kCpumMicroarch_AMD_K8_End,
213
214 kCpumMicroarch_AMD_K10,
215 kCpumMicroarch_AMD_K10_Lion,
216 kCpumMicroarch_AMD_K10_Llano,
217 kCpumMicroarch_AMD_Bobcat,
218 kCpumMicroarch_AMD_Jaguar,
219
220 kCpumMicroarch_AMD_15h_First,
221 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
222 kCpumMicroarch_AMD_15h_Piledriver,
223 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
224 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
225 kCpumMicroarch_AMD_15h_Unknown,
226 kCpumMicroarch_AMD_15h_End,
227
228 kCpumMicroarch_AMD_16h_First,
229 kCpumMicroarch_AMD_16h_End,
230
231 kCpumMicroarch_AMD_Zen_First,
232 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
233 kCpumMicroarch_AMD_Zen_End,
234
235 kCpumMicroarch_AMD_Unknown,
236 kCpumMicroarch_AMD_End,
237
238 kCpumMicroarch_VIA_First,
239 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
240 kCpumMicroarch_Centaur_C2,
241 kCpumMicroarch_Centaur_C3,
242 kCpumMicroarch_VIA_C3_M2,
243 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
244 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
245 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
246 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
247 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
248 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
249 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
250 kCpumMicroarch_VIA_Isaiah,
251 kCpumMicroarch_VIA_Unknown,
252 kCpumMicroarch_VIA_End,
253
254 kCpumMicroarch_Cyrix_First,
255 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
256 kCpumMicroarch_Cyrix_M1,
257 kCpumMicroarch_Cyrix_MediaGX,
258 kCpumMicroarch_Cyrix_MediaGXm,
259 kCpumMicroarch_Cyrix_M2,
260 kCpumMicroarch_Cyrix_Unknown,
261 kCpumMicroarch_Cyrix_End,
262
263 kCpumMicroarch_NEC_First,
264 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
265 kCpumMicroarch_NEC_V30,
266 kCpumMicroarch_NEC_End,
267
268 kCpumMicroarch_Unknown,
269
270 kCpumMicroarch_32BitHack = 0x7fffffff
271} CPUMMICROARCH;
272
273
274/** Predicate macro for catching netburst CPUs. */
275#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
276 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
277
278/** Predicate macro for catching Core7 CPUs. */
279#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
280 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
281
282/** Predicate macro for catching Core 2 CPUs. */
283#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
284 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
285
286/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
287#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
288 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
289
290/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
291#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
292 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
293
294/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
295#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
296
297/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
298#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
299
300/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
301#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
302
303/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
304#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
305
306/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
307 * decendants). */
308#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
309 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
310
311/** Predicate macro for catching AMD Family 16H CPUs. */
312#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
313 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
314
315
316
317/**
318 * CPUID leaf.
319 *
320 * @remarks This structure is used by the patch manager and is therefore
321 * more or less set in stone.
322 */
323typedef struct CPUMCPUIDLEAF
324{
325 /** The leaf number. */
326 uint32_t uLeaf;
327 /** The sub-leaf number. */
328 uint32_t uSubLeaf;
329 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
330 uint32_t fSubLeafMask;
331
332 /** The EAX value. */
333 uint32_t uEax;
334 /** The EBX value. */
335 uint32_t uEbx;
336 /** The ECX value. */
337 uint32_t uEcx;
338 /** The EDX value. */
339 uint32_t uEdx;
340
341 /** Flags. */
342 uint32_t fFlags;
343} CPUMCPUIDLEAF;
344#ifndef VBOX_FOR_DTRACE_LIB
345AssertCompileSize(CPUMCPUIDLEAF, 32);
346#endif
347/** Pointer to a CPUID leaf. */
348typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
349/** Pointer to a const CPUID leaf. */
350typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
351
352/** @name CPUMCPUIDLEAF::fFlags
353 * @{ */
354/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
355 * and EDX containing the extended APIC ID. */
356#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
357/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
358#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
359/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
360#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
361/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
362#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
363/** Mask of the valid flags. */
364#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
365/** @} */
366
367/**
368 * Method used to deal with unknown CPUID leaves.
369 * @remarks Used in patch code.
370 */
371typedef enum CPUMUNKNOWNCPUID
372{
373 /** Invalid zero value. */
374 CPUMUNKNOWNCPUID_INVALID = 0,
375 /** Use given default values (DefCpuId). */
376 CPUMUNKNOWNCPUID_DEFAULTS,
377 /** Return the last standard leaf.
378 * Intel Sandy Bridge has been observed doing this. */
379 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
380 /** Return the last standard leaf, with ecx observed.
381 * Intel Sandy Bridge has been observed doing this. */
382 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
383 /** The register values are passed thru unmodified. */
384 CPUMUNKNOWNCPUID_PASSTHRU,
385 /** End of valid value. */
386 CPUMUNKNOWNCPUID_END,
387 /** Ensure 32-bit type. */
388 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
389} CPUMUNKNOWNCPUID;
390/** Pointer to unknown CPUID leaf method. */
391typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
392
393
394/**
395 * MSR read functions.
396 */
397typedef enum CPUMMSRRDFN
398{
399 /** Invalid zero value. */
400 kCpumMsrRdFn_Invalid = 0,
401 /** Return the CPUMMSRRANGE::uValue. */
402 kCpumMsrRdFn_FixedValue,
403 /** Alias to the MSR range starting at the MSR given by
404 * CPUMMSRRANGE::uValue. Must be used in pair with
405 * kCpumMsrWrFn_MsrAlias. */
406 kCpumMsrRdFn_MsrAlias,
407 /** Write only register, GP all read attempts. */
408 kCpumMsrRdFn_WriteOnly,
409
410 kCpumMsrRdFn_Ia32P5McAddr,
411 kCpumMsrRdFn_Ia32P5McType,
412 kCpumMsrRdFn_Ia32TimestampCounter,
413 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
414 kCpumMsrRdFn_Ia32ApicBase,
415 kCpumMsrRdFn_Ia32FeatureControl,
416 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
417 kCpumMsrRdFn_Ia32SmmMonitorCtl,
418 kCpumMsrRdFn_Ia32PmcN,
419 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
420 kCpumMsrRdFn_Ia32MPerf,
421 kCpumMsrRdFn_Ia32APerf,
422 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
423 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
424 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
425 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
426 kCpumMsrRdFn_Ia32MtrrDefType,
427 kCpumMsrRdFn_Ia32Pat,
428 kCpumMsrRdFn_Ia32SysEnterCs,
429 kCpumMsrRdFn_Ia32SysEnterEsp,
430 kCpumMsrRdFn_Ia32SysEnterEip,
431 kCpumMsrRdFn_Ia32McgCap,
432 kCpumMsrRdFn_Ia32McgStatus,
433 kCpumMsrRdFn_Ia32McgCtl,
434 kCpumMsrRdFn_Ia32DebugCtl,
435 kCpumMsrRdFn_Ia32SmrrPhysBase,
436 kCpumMsrRdFn_Ia32SmrrPhysMask,
437 kCpumMsrRdFn_Ia32PlatformDcaCap,
438 kCpumMsrRdFn_Ia32CpuDcaCap,
439 kCpumMsrRdFn_Ia32Dca0Cap,
440 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
441 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
442 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
443 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
444 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
445 kCpumMsrRdFn_Ia32FixedCtrCtrl,
446 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
447 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
448 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
449 kCpumMsrRdFn_Ia32PebsEnable,
450 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
451 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
452 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
453 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
454 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
455 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
456 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
457 kCpumMsrRdFn_Ia32DsArea,
458 kCpumMsrRdFn_Ia32TscDeadline,
459 kCpumMsrRdFn_Ia32X2ApicN,
460 kCpumMsrRdFn_Ia32DebugInterface,
461 kCpumMsrRdFn_Ia32VmxBasic, /**< Takes real value as reference. */
462 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
463 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
464 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
465 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
466 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
467 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
468 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
469 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
470 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
471 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
472 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
473 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
474 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
475 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
476 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
477 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
478 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
479 kCpumMsrRdFn_Ia32SpecCtrl,
480 kCpumMsrRdFn_Ia32ArchCapabilities,
481
482 kCpumMsrRdFn_Amd64Efer,
483 kCpumMsrRdFn_Amd64SyscallTarget,
484 kCpumMsrRdFn_Amd64LongSyscallTarget,
485 kCpumMsrRdFn_Amd64CompSyscallTarget,
486 kCpumMsrRdFn_Amd64SyscallFlagMask,
487 kCpumMsrRdFn_Amd64FsBase,
488 kCpumMsrRdFn_Amd64GsBase,
489 kCpumMsrRdFn_Amd64KernelGsBase,
490 kCpumMsrRdFn_Amd64TscAux,
491
492 kCpumMsrRdFn_IntelEblCrPowerOn,
493 kCpumMsrRdFn_IntelI7CoreThreadCount,
494 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
495 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
496 kCpumMsrRdFn_IntelP4EbcFrequencyId,
497 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
498 kCpumMsrRdFn_IntelPlatformInfo,
499 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
500 kCpumMsrRdFn_IntelPkgCStConfigControl,
501 kCpumMsrRdFn_IntelPmgIoCaptureBase,
502 kCpumMsrRdFn_IntelLastBranchFromToN,
503 kCpumMsrRdFn_IntelLastBranchFromN,
504 kCpumMsrRdFn_IntelLastBranchToN,
505 kCpumMsrRdFn_IntelLastBranchTos,
506 kCpumMsrRdFn_IntelBblCrCtl,
507 kCpumMsrRdFn_IntelBblCrCtl3,
508 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
509 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
510 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
511 kCpumMsrRdFn_IntelP6CrN,
512 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
513 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
514 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
515 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
516 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
517 kCpumMsrRdFn_IntelI7LbrSelect,
518 kCpumMsrRdFn_IntelI7SandyErrorControl,
519 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
520 kCpumMsrRdFn_IntelI7PowerCtl,
521 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
522 kCpumMsrRdFn_IntelI7PebsLdLat,
523 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
524 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
525 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
526 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
527 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
528 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
529 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
530 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
531 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
532 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
533 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
534 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
535 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
536 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
537 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
538 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
539 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
540 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
541 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
542 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
543 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
544 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
545 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
546 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
547 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
548 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
549 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
550 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
551 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
552 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
553 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
554 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
555 kCpumMsrRdFn_IntelI7UncCBoxConfig,
556 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
557 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
558 kCpumMsrRdFn_IntelI7SmiCount,
559 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
560 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
561 kCpumMsrRdFn_IntelCore1ExtConfig,
562 kCpumMsrRdFn_IntelCore1DtsCalControl,
563 kCpumMsrRdFn_IntelCore2PeciControl,
564 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
565
566 kCpumMsrRdFn_P6LastBranchFromIp,
567 kCpumMsrRdFn_P6LastBranchToIp,
568 kCpumMsrRdFn_P6LastIntFromIp,
569 kCpumMsrRdFn_P6LastIntToIp,
570
571 kCpumMsrRdFn_AmdFam15hTscRate,
572 kCpumMsrRdFn_AmdFam15hLwpCfg,
573 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
574 kCpumMsrRdFn_AmdFam10hMc4MiscN,
575 kCpumMsrRdFn_AmdK8PerfCtlN,
576 kCpumMsrRdFn_AmdK8PerfCtrN,
577 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
578 kCpumMsrRdFn_AmdK8HwCr,
579 kCpumMsrRdFn_AmdK8IorrBaseN,
580 kCpumMsrRdFn_AmdK8IorrMaskN,
581 kCpumMsrRdFn_AmdK8TopOfMemN,
582 kCpumMsrRdFn_AmdK8NbCfg1,
583 kCpumMsrRdFn_AmdK8McXcptRedir,
584 kCpumMsrRdFn_AmdK8CpuNameN,
585 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
586 kCpumMsrRdFn_AmdK8SwThermalCtrl,
587 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
588 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
589 kCpumMsrRdFn_AmdK8McCtlMaskN,
590 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
591 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
592 kCpumMsrRdFn_AmdK8IntPendingMessage,
593 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
594 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
595 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
596 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
597 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
598 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
599 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
600 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
601 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
602 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
603 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
604 kCpumMsrRdFn_AmdK8SmmBase,
605 kCpumMsrRdFn_AmdK8SmmAddr,
606 kCpumMsrRdFn_AmdK8SmmMask,
607 kCpumMsrRdFn_AmdK8VmCr,
608 kCpumMsrRdFn_AmdK8IgnNe,
609 kCpumMsrRdFn_AmdK8SmmCtl,
610 kCpumMsrRdFn_AmdK8VmHSavePa,
611 kCpumMsrRdFn_AmdFam10hVmLockKey,
612 kCpumMsrRdFn_AmdFam10hSmmLockKey,
613 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
614 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
615 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
616 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
617 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
618 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
619 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
620 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
621 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
622 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
623 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
624 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
625 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
626 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
627 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
628 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
629 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
630 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
631 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
632 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
633 kCpumMsrRdFn_AmdK7NodeId,
634 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
635 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
636 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
637 kCpumMsrRdFn_AmdK7LoadStoreCfg,
638 kCpumMsrRdFn_AmdK7InstrCacheCfg,
639 kCpumMsrRdFn_AmdK7DataCacheCfg,
640 kCpumMsrRdFn_AmdK7BusUnitCfg,
641 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
642 kCpumMsrRdFn_AmdFam15hFpuCfg,
643 kCpumMsrRdFn_AmdFam15hDecoderCfg,
644 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
645 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
646 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
647 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
648 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
649 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
650 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
651 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
652 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
653 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
654 kCpumMsrRdFn_AmdFam10hIbsOpRip,
655 kCpumMsrRdFn_AmdFam10hIbsOpData,
656 kCpumMsrRdFn_AmdFam10hIbsOpData2,
657 kCpumMsrRdFn_AmdFam10hIbsOpData3,
658 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
659 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
660 kCpumMsrRdFn_AmdFam10hIbsCtl,
661 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
662
663 kCpumMsrRdFn_Gim,
664
665 /** End of valid MSR read function indexes. */
666 kCpumMsrRdFn_End
667} CPUMMSRRDFN;
668
669/**
670 * MSR write functions.
671 */
672typedef enum CPUMMSRWRFN
673{
674 /** Invalid zero value. */
675 kCpumMsrWrFn_Invalid = 0,
676 /** Writes are ignored, the fWrGpMask is observed though. */
677 kCpumMsrWrFn_IgnoreWrite,
678 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
679 kCpumMsrWrFn_ReadOnly,
680 /** Alias to the MSR range starting at the MSR given by
681 * CPUMMSRRANGE::uValue. Must be used in pair with
682 * kCpumMsrRdFn_MsrAlias. */
683 kCpumMsrWrFn_MsrAlias,
684
685 kCpumMsrWrFn_Ia32P5McAddr,
686 kCpumMsrWrFn_Ia32P5McType,
687 kCpumMsrWrFn_Ia32TimestampCounter,
688 kCpumMsrWrFn_Ia32ApicBase,
689 kCpumMsrWrFn_Ia32FeatureControl,
690 kCpumMsrWrFn_Ia32BiosSignId,
691 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
692 kCpumMsrWrFn_Ia32SmmMonitorCtl,
693 kCpumMsrWrFn_Ia32PmcN,
694 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
695 kCpumMsrWrFn_Ia32MPerf,
696 kCpumMsrWrFn_Ia32APerf,
697 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
698 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
699 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
700 kCpumMsrWrFn_Ia32MtrrDefType,
701 kCpumMsrWrFn_Ia32Pat,
702 kCpumMsrWrFn_Ia32SysEnterCs,
703 kCpumMsrWrFn_Ia32SysEnterEsp,
704 kCpumMsrWrFn_Ia32SysEnterEip,
705 kCpumMsrWrFn_Ia32McgStatus,
706 kCpumMsrWrFn_Ia32McgCtl,
707 kCpumMsrWrFn_Ia32DebugCtl,
708 kCpumMsrWrFn_Ia32SmrrPhysBase,
709 kCpumMsrWrFn_Ia32SmrrPhysMask,
710 kCpumMsrWrFn_Ia32PlatformDcaCap,
711 kCpumMsrWrFn_Ia32Dca0Cap,
712 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
713 kCpumMsrWrFn_Ia32PerfStatus,
714 kCpumMsrWrFn_Ia32PerfCtl,
715 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
716 kCpumMsrWrFn_Ia32PerfCapabilities,
717 kCpumMsrWrFn_Ia32FixedCtrCtrl,
718 kCpumMsrWrFn_Ia32PerfGlobalStatus,
719 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
720 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
721 kCpumMsrWrFn_Ia32PebsEnable,
722 kCpumMsrWrFn_Ia32ClockModulation,
723 kCpumMsrWrFn_Ia32ThermInterrupt,
724 kCpumMsrWrFn_Ia32ThermStatus,
725 kCpumMsrWrFn_Ia32Therm2Ctl,
726 kCpumMsrWrFn_Ia32MiscEnable,
727 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
728 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
729 kCpumMsrWrFn_Ia32DsArea,
730 kCpumMsrWrFn_Ia32TscDeadline,
731 kCpumMsrWrFn_Ia32X2ApicN,
732 kCpumMsrWrFn_Ia32DebugInterface,
733 kCpumMsrWrFn_Ia32SpecCtrl,
734 kCpumMsrWrFn_Ia32PredCmd,
735 kCpumMsrWrFn_Ia32FlushCmd,
736
737 kCpumMsrWrFn_Amd64Efer,
738 kCpumMsrWrFn_Amd64SyscallTarget,
739 kCpumMsrWrFn_Amd64LongSyscallTarget,
740 kCpumMsrWrFn_Amd64CompSyscallTarget,
741 kCpumMsrWrFn_Amd64SyscallFlagMask,
742 kCpumMsrWrFn_Amd64FsBase,
743 kCpumMsrWrFn_Amd64GsBase,
744 kCpumMsrWrFn_Amd64KernelGsBase,
745 kCpumMsrWrFn_Amd64TscAux,
746 kCpumMsrWrFn_IntelEblCrPowerOn,
747 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
748 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
749 kCpumMsrWrFn_IntelP4EbcFrequencyId,
750 kCpumMsrWrFn_IntelFlexRatio,
751 kCpumMsrWrFn_IntelPkgCStConfigControl,
752 kCpumMsrWrFn_IntelPmgIoCaptureBase,
753 kCpumMsrWrFn_IntelLastBranchFromToN,
754 kCpumMsrWrFn_IntelLastBranchFromN,
755 kCpumMsrWrFn_IntelLastBranchToN,
756 kCpumMsrWrFn_IntelLastBranchTos,
757 kCpumMsrWrFn_IntelBblCrCtl,
758 kCpumMsrWrFn_IntelBblCrCtl3,
759 kCpumMsrWrFn_IntelI7TemperatureTarget,
760 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
761 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
762 kCpumMsrWrFn_IntelP6CrN,
763 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
764 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
765 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
766 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
767 kCpumMsrWrFn_IntelI7TurboRatioLimit,
768 kCpumMsrWrFn_IntelI7LbrSelect,
769 kCpumMsrWrFn_IntelI7SandyErrorControl,
770 kCpumMsrWrFn_IntelI7PowerCtl,
771 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
772 kCpumMsrWrFn_IntelI7PebsLdLat,
773 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
774 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
775 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
776 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
777 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
778 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
779 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
780 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
781 kCpumMsrWrFn_IntelI7RaplPp0Policy,
782 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
783 kCpumMsrWrFn_IntelI7RaplPp1Policy,
784 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
785 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
786 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
787 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
788 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
789 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
790 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
791 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
792 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
793 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
794 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
795 kCpumMsrWrFn_IntelCore1ExtConfig,
796 kCpumMsrWrFn_IntelCore1DtsCalControl,
797 kCpumMsrWrFn_IntelCore2PeciControl,
798
799 kCpumMsrWrFn_P6LastIntFromIp,
800 kCpumMsrWrFn_P6LastIntToIp,
801
802 kCpumMsrWrFn_AmdFam15hTscRate,
803 kCpumMsrWrFn_AmdFam15hLwpCfg,
804 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
805 kCpumMsrWrFn_AmdFam10hMc4MiscN,
806 kCpumMsrWrFn_AmdK8PerfCtlN,
807 kCpumMsrWrFn_AmdK8PerfCtrN,
808 kCpumMsrWrFn_AmdK8SysCfg,
809 kCpumMsrWrFn_AmdK8HwCr,
810 kCpumMsrWrFn_AmdK8IorrBaseN,
811 kCpumMsrWrFn_AmdK8IorrMaskN,
812 kCpumMsrWrFn_AmdK8TopOfMemN,
813 kCpumMsrWrFn_AmdK8NbCfg1,
814 kCpumMsrWrFn_AmdK8McXcptRedir,
815 kCpumMsrWrFn_AmdK8CpuNameN,
816 kCpumMsrWrFn_AmdK8HwThermalCtrl,
817 kCpumMsrWrFn_AmdK8SwThermalCtrl,
818 kCpumMsrWrFn_AmdK8FidVidControl,
819 kCpumMsrWrFn_AmdK8McCtlMaskN,
820 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
821 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
822 kCpumMsrWrFn_AmdK8IntPendingMessage,
823 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
824 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
825 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
826 kCpumMsrWrFn_AmdFam10hPStateControl,
827 kCpumMsrWrFn_AmdFam10hPStateStatus,
828 kCpumMsrWrFn_AmdFam10hPStateN,
829 kCpumMsrWrFn_AmdFam10hCofVidControl,
830 kCpumMsrWrFn_AmdFam10hCofVidStatus,
831 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
832 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
833 kCpumMsrWrFn_AmdK8SmmBase,
834 kCpumMsrWrFn_AmdK8SmmAddr,
835 kCpumMsrWrFn_AmdK8SmmMask,
836 kCpumMsrWrFn_AmdK8VmCr,
837 kCpumMsrWrFn_AmdK8IgnNe,
838 kCpumMsrWrFn_AmdK8SmmCtl,
839 kCpumMsrWrFn_AmdK8VmHSavePa,
840 kCpumMsrWrFn_AmdFam10hVmLockKey,
841 kCpumMsrWrFn_AmdFam10hSmmLockKey,
842 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
843 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
844 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
845 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
846 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
847 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
848 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
849 kCpumMsrWrFn_AmdK7MicrocodeCtl,
850 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
851 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
852 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
853 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
854 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
855 kCpumMsrWrFn_AmdK8PatchLoader,
856 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
857 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
858 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
859 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
860 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
861 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
862 kCpumMsrWrFn_AmdK7NodeId,
863 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
864 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
865 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
866 kCpumMsrWrFn_AmdK7LoadStoreCfg,
867 kCpumMsrWrFn_AmdK7InstrCacheCfg,
868 kCpumMsrWrFn_AmdK7DataCacheCfg,
869 kCpumMsrWrFn_AmdK7BusUnitCfg,
870 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
871 kCpumMsrWrFn_AmdFam15hFpuCfg,
872 kCpumMsrWrFn_AmdFam15hDecoderCfg,
873 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
874 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
875 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
876 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
877 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
878 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
879 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
880 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
881 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
882 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
883 kCpumMsrWrFn_AmdFam10hIbsOpRip,
884 kCpumMsrWrFn_AmdFam10hIbsOpData,
885 kCpumMsrWrFn_AmdFam10hIbsOpData2,
886 kCpumMsrWrFn_AmdFam10hIbsOpData3,
887 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
888 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
889 kCpumMsrWrFn_AmdFam10hIbsCtl,
890 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
891
892 kCpumMsrWrFn_Gim,
893
894 /** End of valid MSR write function indexes. */
895 kCpumMsrWrFn_End
896} CPUMMSRWRFN;
897
898/**
899 * MSR range.
900 */
901typedef struct CPUMMSRRANGE
902{
903 /** The first MSR. [0] */
904 uint32_t uFirst;
905 /** The last MSR. [4] */
906 uint32_t uLast;
907 /** The read function (CPUMMSRRDFN). [8] */
908 uint16_t enmRdFn;
909 /** The write function (CPUMMSRWRFN). [10] */
910 uint16_t enmWrFn;
911 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
912 * UINT16_MAX if not used by the read and write functions. [12] */
913 uint16_t offCpumCpu;
914 /** Reserved for future hacks. [14] */
915 uint16_t fReserved;
916 /** The init/read value. [16]
917 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
918 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
919 * offset into CPUM. */
920 uint64_t uValue;
921 /** The bits to ignore when writing. [24] */
922 uint64_t fWrIgnMask;
923 /** The bits that will cause a GP(0) when writing. [32]
924 * This is always checked prior to calling the write function. Using
925 * UINT64_MAX effectively marks the MSR as read-only. */
926 uint64_t fWrGpMask;
927 /** The register name, if applicable. [40] */
928 char szName[56];
929
930#ifdef VBOX_WITH_STATISTICS
931 /** The number of reads. */
932 STAMCOUNTER cReads;
933 /** The number of writes. */
934 STAMCOUNTER cWrites;
935 /** The number of times ignored bits were written. */
936 STAMCOUNTER cIgnoredBits;
937 /** The number of GPs generated. */
938 STAMCOUNTER cGps;
939#endif
940} CPUMMSRRANGE;
941#ifndef VBOX_FOR_DTRACE_LIB
942# ifdef VBOX_WITH_STATISTICS
943AssertCompileSize(CPUMMSRRANGE, 128);
944# else
945AssertCompileSize(CPUMMSRRANGE, 96);
946# endif
947#endif
948/** Pointer to an MSR range. */
949typedef CPUMMSRRANGE *PCPUMMSRRANGE;
950/** Pointer to a const MSR range. */
951typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
952
953
954/**
955 * MSRs.
956 * MSRs which are required while exploding features.
957 */
958typedef struct CPUMMSRS
959{
960 union
961 {
962 VMXMSRS vmx;
963 SVMMSRS svm;
964 } hwvirt;
965} CPUMMSRS;
966/** Pointer to an CPUMMSRS struct. */
967typedef CPUMMSRS *PCPUMMSRS;
968/** Pointer to a const CPUMMSRS struct. */
969typedef CPUMMSRS const *PCCPUMMSRS;
970
971
972/**
973 * CPU features and quirks.
974 * This is mostly exploded CPUID info.
975 */
976typedef struct CPUMFEATURES
977{
978 /** The CPU vendor (CPUMCPUVENDOR). */
979 uint8_t enmCpuVendor;
980 /** The CPU family. */
981 uint8_t uFamily;
982 /** The CPU model. */
983 uint8_t uModel;
984 /** The CPU stepping. */
985 uint8_t uStepping;
986 /** The microarchitecture. */
987#ifndef VBOX_FOR_DTRACE_LIB
988 CPUMMICROARCH enmMicroarch;
989#else
990 uint32_t enmMicroarch;
991#endif
992 /** The maximum physical address width of the CPU. */
993 uint8_t cMaxPhysAddrWidth;
994 /** The maximum linear address width of the CPU. */
995 uint8_t cMaxLinearAddrWidth;
996 /** Max size of the extended state (or FPU state if no XSAVE). */
997 uint16_t cbMaxExtendedState;
998
999 /** Supports MSRs. */
1000 uint32_t fMsr : 1;
1001 /** Supports the page size extension (4/2 MB pages). */
1002 uint32_t fPse : 1;
1003 /** Supports 36-bit page size extension (4 MB pages can map memory above
1004 * 4GB). */
1005 uint32_t fPse36 : 1;
1006 /** Supports physical address extension (PAE). */
1007 uint32_t fPae : 1;
1008 /** Page attribute table (PAT) support (page level cache control). */
1009 uint32_t fPat : 1;
1010 /** Supports the FXSAVE and FXRSTOR instructions. */
1011 uint32_t fFxSaveRstor : 1;
1012 /** Supports the XSAVE and XRSTOR instructions. */
1013 uint32_t fXSaveRstor : 1;
1014 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
1015 uint32_t fOpSysXSaveRstor : 1;
1016 /** Supports MMX. */
1017 uint32_t fMmx : 1;
1018 /** Supports AMD extensions to MMX instructions. */
1019 uint32_t fAmdMmxExts : 1;
1020 /** Supports SSE. */
1021 uint32_t fSse : 1;
1022 /** Supports SSE2. */
1023 uint32_t fSse2 : 1;
1024 /** Supports SSE3. */
1025 uint32_t fSse3 : 1;
1026 /** Supports SSSE3. */
1027 uint32_t fSsse3 : 1;
1028 /** Supports SSE4.1. */
1029 uint32_t fSse41 : 1;
1030 /** Supports SSE4.2. */
1031 uint32_t fSse42 : 1;
1032 /** Supports AVX. */
1033 uint32_t fAvx : 1;
1034 /** Supports AVX2. */
1035 uint32_t fAvx2 : 1;
1036 /** Supports AVX512 foundation. */
1037 uint32_t fAvx512Foundation : 1;
1038 /** Supports RDTSC. */
1039 uint32_t fTsc : 1;
1040 /** Intel SYSENTER/SYSEXIT support */
1041 uint32_t fSysEnter : 1;
1042 /** First generation APIC. */
1043 uint32_t fApic : 1;
1044 /** Second generation APIC. */
1045 uint32_t fX2Apic : 1;
1046 /** Hypervisor present. */
1047 uint32_t fHypervisorPresent : 1;
1048 /** MWAIT & MONITOR instructions supported. */
1049 uint32_t fMonitorMWait : 1;
1050 /** MWAIT Extensions present. */
1051 uint32_t fMWaitExtensions : 1;
1052 /** Supports CMPXCHG16B in 64-bit mode. */
1053 uint32_t fMovCmpXchg16b : 1;
1054 /** Supports CLFLUSH. */
1055 uint32_t fClFlush : 1;
1056 /** Supports CLFLUSHOPT. */
1057 uint32_t fClFlushOpt : 1;
1058 /** Supports IA32_PRED_CMD.IBPB. */
1059 uint32_t fIbpb : 1;
1060 /** Supports IA32_SPEC_CTRL.IBRS. */
1061 uint32_t fIbrs : 1;
1062 /** Supports IA32_SPEC_CTRL.STIBP. */
1063 uint32_t fStibp : 1;
1064 /** Supports IA32_FLUSH_CMD. */
1065 uint32_t fFlushCmd : 1;
1066 /** Supports IA32_ARCH_CAP. */
1067 uint32_t fArchCap : 1;
1068 /** Supports PCID. */
1069 uint32_t fPcid : 1;
1070 /** Supports INVPCID. */
1071 uint32_t fInvpcid : 1;
1072 /** Supports read/write FSGSBASE instructions. */
1073 uint32_t fFsGsBase : 1;
1074
1075 /** Supports AMD 3DNow instructions. */
1076 uint32_t f3DNow : 1;
1077 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1078 uint32_t f3DNowPrefetch : 1;
1079
1080 /** AMD64: Supports long mode. */
1081 uint32_t fLongMode : 1;
1082 /** AMD64: SYSCALL/SYSRET support. */
1083 uint32_t fSysCall : 1;
1084 /** AMD64: No-execute page table bit. */
1085 uint32_t fNoExecute : 1;
1086 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1087 uint32_t fLahfSahf : 1;
1088 /** AMD64: Supports RDTSCP. */
1089 uint32_t fRdTscP : 1;
1090 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1091 uint32_t fMovCr8In32Bit : 1;
1092 /** AMD64: Supports XOP (similar to VEX3/AVX). */
1093 uint32_t fXop : 1;
1094
1095 /** Indicates that FPU instruction and data pointers may leak.
1096 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1097 * is only saved and restored if an exception is pending. */
1098 uint32_t fLeakyFxSR : 1;
1099
1100 /** AMD64: Supports AMD SVM. */
1101 uint32_t fSvm : 1;
1102
1103 /** Support for Intel VMX. */
1104 uint32_t fVmx : 1;
1105
1106 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
1107 * The details are different for Intel and AMD but both have similar
1108 * functionality. */
1109 uint32_t fSpeculationControl : 1;
1110
1111 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
1112 * @remarks Only safe use after CPUM ring-0 init! */
1113 uint32_t fArchRdclNo : 1;
1114 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
1115 * @remarks Only safe use after CPUM ring-0 init! */
1116 uint32_t fArchIbrsAll : 1;
1117 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
1118 * @remarks Only safe use after CPUM ring-0 init! */
1119 uint32_t fArchRsbOverride : 1;
1120 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
1121 * @remarks Only safe use after CPUM ring-0 init! */
1122 uint32_t fArchVmmNeedNotFlushL1d : 1;
1123
1124 /** Alignment padding / reserved for future use. */
1125 uint32_t fPadding : 10;
1126
1127 /** SVM: Supports Nested-paging. */
1128 uint32_t fSvmNestedPaging : 1;
1129 /** SVM: Support LBR (Last Branch Record) virtualization. */
1130 uint32_t fSvmLbrVirt : 1;
1131 /** SVM: Supports SVM lock. */
1132 uint32_t fSvmSvmLock : 1;
1133 /** SVM: Supports Next RIP save. */
1134 uint32_t fSvmNextRipSave : 1;
1135 /** SVM: Supports TSC rate MSR. */
1136 uint32_t fSvmTscRateMsr : 1;
1137 /** SVM: Supports VMCB clean bits. */
1138 uint32_t fSvmVmcbClean : 1;
1139 /** SVM: Supports Flush-by-ASID. */
1140 uint32_t fSvmFlusbByAsid : 1;
1141 /** SVM: Supports decode assist. */
1142 uint32_t fSvmDecodeAssists : 1;
1143 /** SVM: Supports Pause filter. */
1144 uint32_t fSvmPauseFilter : 1;
1145 /** SVM: Supports Pause filter threshold. */
1146 uint32_t fSvmPauseFilterThreshold : 1;
1147 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1148 uint32_t fSvmAvic : 1;
1149 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1150 uint32_t fSvmVirtVmsaveVmload : 1;
1151 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1152 uint32_t fSvmVGif : 1;
1153 /** SVM: Padding / reserved for future features. */
1154 uint32_t fSvmPadding0 : 19;
1155 /** SVM: Maximum supported ASID. */
1156 uint32_t uSvmMaxAsid;
1157
1158 /** VMX: Maximum physical address width. */
1159 uint8_t cVmxMaxPhysAddrWidth;
1160 /** VMX: Padding / reserved for future. */
1161 uint8_t abVmxPadding[3];
1162 /** VMX: Padding / reserved for future. */
1163 uint32_t fVmxPadding0;
1164
1165 /** @name VMX basic controls.
1166 * @{ */
1167 /** VMX: Supports INS/OUTS VM-exit instruction info. */
1168 uint32_t fVmxInsOutInfo : 1;
1169 /** @} */
1170
1171 /** @name VMX Pin-based controls.
1172 * @{ */
1173 /** VMX: Supports external interrupt VM-exit. */
1174 uint32_t fVmxExtIntExit : 1;
1175 /** VMX: Supports NMI VM-exit. */
1176 uint32_t fVmxNmiExit : 1;
1177 /** VMX: Supports Virtual NMIs. */
1178 uint32_t fVmxVirtNmi : 1;
1179 /** VMX: Supports preemption timer. */
1180 uint32_t fVmxPreemptTimer : 1;
1181 /** VMX: Supports posted interrupts. */
1182 uint32_t fVmxPostedInt : 1;
1183 /** @} */
1184
1185 /** @name VMX Processor-based controls.
1186 * @{ */
1187 /** VMX: Supports Interrupt-window exiting. */
1188 uint32_t fVmxIntWindowExit : 1;
1189 /** VMX: Supports TSC offsetting. */
1190 uint32_t fVmxTscOffsetting : 1;
1191 /** VMX: Supports HLT exiting. */
1192 uint32_t fVmxHltExit : 1;
1193 /** VMX: Supports INVLPG exiting. */
1194 uint32_t fVmxInvlpgExit : 1;
1195 /** VMX: Supports MWAIT exiting. */
1196 uint32_t fVmxMwaitExit : 1;
1197 /** VMX: Supports RDPMC exiting. */
1198 uint32_t fVmxRdpmcExit : 1;
1199 /** VMX: Supports RDTSC exiting. */
1200 uint32_t fVmxRdtscExit : 1;
1201 /** VMX: Supports CR3-load exiting. */
1202 uint32_t fVmxCr3LoadExit : 1;
1203 /** VMX: Supports CR3-store exiting. */
1204 uint32_t fVmxCr3StoreExit : 1;
1205 /** VMX: Supports CR8-load exiting. */
1206 uint32_t fVmxCr8LoadExit : 1;
1207 /** VMX: Supports CR8-store exiting. */
1208 uint32_t fVmxCr8StoreExit : 1;
1209 /** VMX: Supports TPR shadow. */
1210 uint32_t fVmxUseTprShadow : 1;
1211 /** VMX: Supports NMI-window exiting. */
1212 uint32_t fVmxNmiWindowExit : 1;
1213 /** VMX: Supports Mov-DRx exiting. */
1214 uint32_t fVmxMovDRxExit : 1;
1215 /** VMX: Supports Unconditional I/O exiting. */
1216 uint32_t fVmxUncondIoExit : 1;
1217 /** VMX: Supportgs I/O bitmaps. */
1218 uint32_t fVmxUseIoBitmaps : 1;
1219 /** VMX: Supports Monitor Trap Flag. */
1220 uint32_t fVmxMonitorTrapFlag : 1;
1221 /** VMX: Supports MSR bitmap. */
1222 uint32_t fVmxUseMsrBitmaps : 1;
1223 /** VMX: Supports MONITOR exiting. */
1224 uint32_t fVmxMonitorExit : 1;
1225 /** VMX: Supports PAUSE exiting. */
1226 uint32_t fVmxPauseExit : 1;
1227 /** VMX: Supports secondary processor-based VM-execution controls. */
1228 uint32_t fVmxSecondaryExecCtls : 1;
1229 /** @} */
1230
1231 /** @name VMX Secondary processor-based controls.
1232 * @{ */
1233 /** VMX: Supports virtualize-APIC access. */
1234 uint32_t fVmxVirtApicAccess : 1;
1235 /** VMX: Supports EPT (Extended Page Tables). */
1236 uint32_t fVmxEpt : 1;
1237 /** VMX: Supports descriptor-table exiting. */
1238 uint32_t fVmxDescTableExit : 1;
1239 /** VMX: Supports RDTSCP. */
1240 uint32_t fVmxRdtscp : 1;
1241 /** VMX: Supports virtualize-x2APIC mode. */
1242 uint32_t fVmxVirtX2ApicMode : 1;
1243 /** VMX: Supports VPID. */
1244 uint32_t fVmxVpid : 1;
1245 /** VMX: Supports WBIND exiting. */
1246 uint32_t fVmxWbinvdExit : 1;
1247 /** VMX: Supports Unrestricted guest. */
1248 uint32_t fVmxUnrestrictedGuest : 1;
1249 /** VMX: Supports APIC-register virtualization. */
1250 uint32_t fVmxApicRegVirt : 1;
1251 /** VMX: Supports virtual-interrupt delivery. */
1252 uint32_t fVmxVirtIntDelivery : 1;
1253 /** VMX: Supports Pause-loop exiting. */
1254 uint32_t fVmxPauseLoopExit : 1;
1255 /** VMX: Supports RDRAND exiting. */
1256 uint32_t fVmxRdrandExit : 1;
1257 /** VMX: Supports INVPCID. */
1258 uint32_t fVmxInvpcid : 1;
1259 /** VMX: Supports VM functions. */
1260 uint32_t fVmxVmFunc : 1;
1261 /** VMX: Supports VMCS shadowing. */
1262 uint32_t fVmxVmcsShadowing : 1;
1263 /** VMX: Supports RDSEED exiting. */
1264 uint32_t fVmxRdseedExit : 1;
1265 /** VMX: Supports PML. */
1266 uint32_t fVmxPml : 1;
1267 /** VMX: Supports EPT-violations \#VE. */
1268 uint32_t fVmxEptXcptVe : 1;
1269 /** VMX: Supports XSAVES/XRSTORS. */
1270 uint32_t fVmxXsavesXrstors : 1;
1271 /** VMX: Supports TSC scaling. */
1272 uint32_t fVmxUseTscScaling : 1;
1273 /** @} */
1274
1275 /** @name VMX VM-entry controls.
1276 * @{ */
1277 /** VMX: Supports load-debug controls on VM-entry. */
1278 uint32_t fVmxEntryLoadDebugCtls : 1;
1279 /** VMX: Supports IA32e mode guest. */
1280 uint32_t fVmxIa32eModeGuest : 1;
1281 /** VMX: Supports load guest EFER MSR on VM-entry. */
1282 uint32_t fVmxEntryLoadEferMsr : 1;
1283 /** VMX: Supports load guest PAT MSR on VM-entry. */
1284 uint32_t fVmxEntryLoadPatMsr : 1;
1285 /** @} */
1286
1287 /** @name VMX VM-exit controls.
1288 * @{ */
1289 /** VMX: Supports save debug controls on VM-exit. */
1290 uint32_t fVmxExitSaveDebugCtls : 1;
1291 /** VMX: Supports host-address space size. */
1292 uint32_t fVmxHostAddrSpaceSize : 1;
1293 /** VMX: Supports acknowledge external interrupt on VM-exit. */
1294 uint32_t fVmxExitAckExtInt : 1;
1295 /** VMX: Supports save guest PAT MSR on VM-exit. */
1296 uint32_t fVmxExitSavePatMsr : 1;
1297 /** VMX: Supports load hsot PAT MSR on VM-exit. */
1298 uint32_t fVmxExitLoadPatMsr : 1;
1299 /** VMX: Supports save guest EFER MSR on VM-exit. */
1300 uint32_t fVmxExitSaveEferMsr : 1;
1301 /** VMX: Supports load host EFER MSR on VM-exit. */
1302 uint32_t fVmxExitLoadEferMsr : 1;
1303 /** VMX: Supports save VMX preemption timer on VM-exit. */
1304 uint32_t fVmxSavePreemptTimer : 1;
1305 /** @} */
1306
1307 /** @name VMX Miscellaneous data.
1308 * @{ */
1309 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1310 uint32_t fVmxExitSaveEferLma : 1;
1311 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1312 uint32_t fVmxIntelPt : 1;
1313 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1314 * VMWRITE cannot modify read-only VM-exit information fields. */
1315 uint32_t fVmxVmwriteAll : 1;
1316 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1317 * length instructions. */
1318 uint32_t fVmxEntryInjectSoftInt : 1;
1319 /** @} */
1320
1321 /** VMX: Padding / reserved for future features. */
1322 uint32_t fVmxPadding1 : 1;
1323 uint32_t fVmxPadding2;
1324} CPUMFEATURES;
1325#ifndef VBOX_FOR_DTRACE_LIB
1326AssertCompileSize(CPUMFEATURES, 48);
1327#endif
1328/** Pointer to a CPU feature structure. */
1329typedef CPUMFEATURES *PCPUMFEATURES;
1330/** Pointer to a const CPU feature structure. */
1331typedef CPUMFEATURES const *PCCPUMFEATURES;
1332
1333
1334#ifndef VBOX_FOR_DTRACE_LIB
1335
1336/** @name Guest Register Getters.
1337 * @{ */
1338VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1339VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1340VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1341VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1342VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1343VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1344VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1345VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1346VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1347VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1348VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1349VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1350VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1351VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1352VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1353VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1354VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1355VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1356VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1357VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1358VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1359VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1360VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1361VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1362VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1363VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1364VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1365VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1366VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1367VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1368VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1369VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1370VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1371VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1372VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1373VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1374VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1375VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1376 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1377VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1378VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu);
1379VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PVMCPU pVCpu);
1380VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1381VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1382VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1383VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1384/** @} */
1385
1386/** @name Guest Register Setters.
1387 * @{ */
1388VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1389VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1390VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1391VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1392VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1393VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1394VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1395VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1396VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1397VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1398VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1399VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1400VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1401VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1402VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1403VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue);
1404VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1405VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1406VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1407VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1408VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1409VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1410VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1411VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1412VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1413VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1414VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1415VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1416VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1417VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1418VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1419VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1420VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1421VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1422VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1423VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1424VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1425VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1426VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1427VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1428VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1429VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPU pVCpu);
1430VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPU pVCpu, uint64_t uValue);
1431VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPU pVCpu);
1432VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1433/** @} */
1434
1435
1436/** @name Misc Guest Predicate Functions.
1437 * @{ */
1438VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1439VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1440VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1441VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1442VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1443VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1444VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1445VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1446VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1447VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1448VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1449VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1450VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1451VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1452/** @} */
1453
1454/** @name Nested Hardware-Virtualization Helpers.
1455 * @{ */
1456VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1457VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1458VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PVMCPU pVCpu, PCCPUMCTX pCtx);
1459VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PVMCPU pVCpu, PCCPUMCTX pCtx);
1460VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1461VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPU pVCpu, PCPUMCTX pCtx);
1462VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1463VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PVMCPU pVCpu, uint64_t uTicks);
1464VMM_INT_DECL(bool) CPUMIsGuestVmxPhysIntrEnabled(PVMCPU pVCpu, PCCPUMCTX pCtx);
1465VMM_INT_DECL(bool) CPUMIsGuestVmxVirtIntrEnabled(PVMCPU pVCpu, PCCPUMCTX pCtx);
1466/** @} */
1467
1468/** @name Externalized State Helpers.
1469 * @{ */
1470/** @def CPUM_ASSERT_NOT_EXTRN
1471 * Macro for asserting that @a a_fNotExtrn are present.
1472 *
1473 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1474 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1475 *
1476 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1477 */
1478#define CPUM_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
1479 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fNotExtrn)), \
1480 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fNotExtrn)))
1481
1482/** @def CPUM_IMPORT_EXTRN_RET
1483 * Macro for making sure the state specified by @a fExtrnImport is present,
1484 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1485 *
1486 * Will return if CPUMImportGuestStateOnDemand() fails.
1487 *
1488 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1489 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1490 * @thread EMT(a_pVCpu)
1491 *
1492 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1493 */
1494#define CPUM_IMPORT_EXTRN_RET(a_pVCpu, a_fExtrnImport) \
1495 do { \
1496 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1497 { /* already present, consider this likely */ } \
1498 else \
1499 { \
1500 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1501 AssertRCReturn(rcCpumImport, rcCpumImport); \
1502 } \
1503 } while (0)
1504
1505/** @def CPUM_IMPORT_EXTRN_RCSTRICT
1506 * Macro for making sure the state specified by @a fExtrnImport is present,
1507 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1508 *
1509 * Will update a_rcStrict if CPUMImportGuestStateOnDemand() fails.
1510 *
1511 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1512 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1513 * @param a_rcStrict Strict status code variable to update on failure.
1514 * @thread EMT(a_pVCpu)
1515 *
1516 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1517 */
1518#define CPUM_IMPORT_EXTRN_RCSTRICT(a_pVCpu, a_fExtrnImport, a_rcStrict) \
1519 do { \
1520 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1521 { /* already present, consider this likely */ } \
1522 else \
1523 { \
1524 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1525 AssertStmt(RT_SUCCESS(rcCpumImport) || RT_FAILURE_NP(a_rcStrict), a_rcStrict = rcCpumImport); \
1526 } \
1527 } while (0)
1528
1529VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPU pVCpu, uint64_t fExtrnImport);
1530/** @} */
1531
1532#ifndef IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS
1533
1534/**
1535 * Gets valid CR0 bits for the guest.
1536 *
1537 * @returns Valid CR0 bits.
1538 */
1539DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1540{
1541 return ( X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
1542 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
1543 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG);
1544}
1545
1546/**
1547 * Tests if the guest is running in real mode or not.
1548 *
1549 * @returns true if in real mode, otherwise false.
1550 * @param pCtx Current CPU context.
1551 */
1552DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1553{
1554 return !(pCtx->cr0 & X86_CR0_PE);
1555}
1556
1557/**
1558 * Tests if the guest is running in real or virtual 8086 mode.
1559 *
1560 * @returns @c true if it is, @c false if not.
1561 * @param pCtx Current CPU context.
1562 */
1563DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1564{
1565 return !(pCtx->cr0 & X86_CR0_PE)
1566 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1567}
1568
1569/**
1570 * Tests if the guest is running in virtual 8086 mode.
1571 *
1572 * @returns @c true if it is, @c false if not.
1573 * @param pCtx Current CPU context.
1574 */
1575DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1576{
1577 return (pCtx->eflags.Bits.u1VM == 1);
1578}
1579
1580/**
1581 * Tests if the guest is running in paged protected or not.
1582 *
1583 * @returns true if in paged protected mode, otherwise false.
1584 * @param pCtx Current CPU context.
1585 */
1586DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1587{
1588 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1589}
1590
1591/**
1592 * Tests if the guest is running in long mode or not.
1593 *
1594 * @returns true if in long mode, otherwise false.
1595 * @param pCtx Current CPU context.
1596 */
1597DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1598{
1599 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1600}
1601
1602VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1603
1604/**
1605 * Tests if the guest is running in 64 bits mode or not.
1606 *
1607 * @returns true if in 64 bits protected mode, otherwise false.
1608 * @param pCtx Current CPU context.
1609 */
1610DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1611{
1612 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1613 return false;
1614 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1615 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1616 return pCtx->cs.Attr.n.u1Long;
1617}
1618
1619/**
1620 * Tests if the guest has paging enabled or not.
1621 *
1622 * @returns true if paging is enabled, otherwise false.
1623 * @param pCtx Current CPU context.
1624 */
1625DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1626{
1627 return !!(pCtx->cr0 & X86_CR0_PG);
1628}
1629
1630/**
1631 * Tests if the guest is running in PAE mode or not.
1632 *
1633 * @returns true if in PAE mode, otherwise false.
1634 * @param pCtx Current CPU context.
1635 */
1636DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1637{
1638 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1639 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1640 return ( (pCtx->cr4 & X86_CR4_PAE)
1641 && CPUMIsGuestPagingEnabledEx(pCtx)
1642 && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1643}
1644
1645/**
1646 * Tests if the guest has AMD SVM enabled or not.
1647 *
1648 * @returns true if SMV is enabled, otherwise false.
1649 * @param pCtx Current CPU context.
1650 */
1651DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1652{
1653 return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1654}
1655
1656/**
1657 * Tests if the guest has Intel VT-x enabled or not.
1658 *
1659 * @returns true if VMX is enabled, otherwise false.
1660 * @param pCtx Current CPU context.
1661 */
1662DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1663{
1664 return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1665}
1666
1667/**
1668 * Returns the guest's global-interrupt (GIF) flag.
1669 *
1670 * @returns true when global-interrupts are enabled, otherwise false.
1671 * @param pCtx Current CPU context.
1672 */
1673DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1674{
1675 return pCtx->hwvirt.fGif;
1676}
1677
1678/**
1679 * Sets the guest's global-interrupt flag (GIF).
1680 *
1681 * @param pCtx Current CPU context.
1682 * @param fGif The value to set.
1683 */
1684DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1685{
1686 pCtx->hwvirt.fGif = fGif;
1687}
1688
1689/**
1690 * Checks if we are executing inside an SVM nested hardware-virtualized guest.
1691 *
1692 * @returns @c true if in SVM nested-guest mode, @c false otherwise.
1693 * @param pCtx Current CPU context.
1694 */
1695DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1696{
1697 /*
1698 * With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1699 * See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1700 */
1701#ifndef IN_RC
1702 if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
1703 || !(pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
1704 return false;
1705 return true;
1706#else
1707 NOREF(pCtx);
1708 return false;
1709#endif
1710}
1711
1712/**
1713 * Checks if the guest is in VMX non-root operation.
1714 *
1715 * @returns @c true if in VMX non-root operation, @c false otherwise.
1716 * @param pCtx Current CPU context.
1717 */
1718DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
1719{
1720#ifndef IN_RC
1721 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1722 return false;
1723 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
1724 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
1725#else
1726 NOREF(pCtx);
1727 return false;
1728#endif
1729}
1730
1731/**
1732 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
1733 * guest.
1734 *
1735 * @returns @c true if in nested-guest mode, @c false otherwise.
1736 * @param pCtx Current CPU context.
1737 */
1738DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
1739{
1740 return CPUMIsGuestInVmxNonRootMode(pCtx) || CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
1741}
1742
1743/**
1744 * Checks if the guest is in VMX root operation.
1745 *
1746 * @returns @c true if in VMX root operation, @c false otherwise.
1747 * @param pCtx Current CPU context.
1748 */
1749DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
1750{
1751#ifndef IN_RC
1752 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
1753 return false;
1754 return pCtx->hwvirt.vmx.fInVmxRootMode;
1755#else
1756 NOREF(pCtx);
1757 return false;
1758#endif
1759}
1760
1761# ifndef IN_RC
1762
1763/**
1764 * Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
1765 * active.
1766 *
1767 * @returns @c true if in intercept is set, @c false otherwise.
1768 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1769 * @param pCtx Pointer to the context.
1770 * @param fIntercept The SVM control/instruction intercept, see
1771 * SVM_CTRL_INTERCEPT_*.
1772 */
1773DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
1774{
1775 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1776 return false;
1777 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1778 if (HMHasGuestSvmVmcbCached(pVCpu))
1779 return HMIsGuestSvmCtrlInterceptSet(pVCpu, fIntercept);
1780 return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fIntercept);
1781}
1782
1783/**
1784 * Checks if the nested-guest VMCB has the specified CR read intercept active.
1785 *
1786 * @returns @c true if in intercept is set, @c false otherwise.
1787 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1788 * @param pCtx Pointer to the context.
1789 * @param uCr The CR register number (0 to 15).
1790 */
1791DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1792{
1793 Assert(uCr < 16);
1794 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1795 return false;
1796 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1797 if (HMHasGuestSvmVmcbCached(pVCpu))
1798 return HMIsGuestSvmReadCRxInterceptSet(pVCpu, uCr);
1799 return RT_BOOL(pVmcb->ctrl.u16InterceptRdCRx & (UINT16_C(1) << uCr));
1800}
1801
1802/**
1803 * Checks if the nested-guest VMCB has the specified CR write intercept active.
1804 *
1805 * @returns @c true if in intercept is set, @c false otherwise.
1806 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1807 * @param pCtx Pointer to the context.
1808 * @param uCr The CR register number (0 to 15).
1809 */
1810DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1811{
1812 Assert(uCr < 16);
1813 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1814 return false;
1815 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1816 if (HMHasGuestSvmVmcbCached(pVCpu))
1817 return HMIsGuestSvmWriteCRxInterceptSet(pVCpu, uCr);
1818 return RT_BOOL(pVmcb->ctrl.u16InterceptWrCRx & (UINT16_C(1) << uCr));
1819}
1820
1821/**
1822 * Checks if the nested-guest VMCB has the specified DR read intercept active.
1823 *
1824 * @returns @c true if in intercept is set, @c false otherwise.
1825 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1826 * @param pCtx Pointer to the context.
1827 * @param uDr The DR register number (0 to 15).
1828 */
1829DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1830{
1831 Assert(uDr < 16);
1832 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1833 return false;
1834 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1835 if (HMHasGuestSvmVmcbCached(pVCpu))
1836 return HMIsGuestSvmReadDRxInterceptSet(pVCpu, uDr);
1837 return RT_BOOL(pVmcb->ctrl.u16InterceptRdDRx & (UINT16_C(1) << uDr));
1838}
1839
1840/**
1841 * Checks if the nested-guest VMCB has the specified DR write intercept active.
1842 *
1843 * @returns @c true if in intercept is set, @c false otherwise.
1844 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1845 * @param pCtx Pointer to the context.
1846 * @param uDr The DR register number (0 to 15).
1847 */
1848DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1849{
1850 Assert(uDr < 16);
1851 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1852 return false;
1853 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1854 if (HMHasGuestSvmVmcbCached(pVCpu))
1855 return HMIsGuestSvmWriteDRxInterceptSet(pVCpu, uDr);
1856 return RT_BOOL(pVmcb->ctrl.u16InterceptWrDRx & (UINT16_C(1) << uDr));
1857}
1858
1859/**
1860 * Checks if the nested-guest VMCB has the specified exception intercept active.
1861 *
1862 * @returns @c true if in intercept is active, @c false otherwise.
1863 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1864 * @param pCtx Pointer to the context.
1865 * @param uVector The exception / interrupt vector.
1866 */
1867DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1868{
1869 Assert(uVector < 32);
1870 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1871 return false;
1872 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1873 if (HMHasGuestSvmVmcbCached(pVCpu))
1874 return HMIsGuestSvmXcptInterceptSet(pVCpu, uVector);
1875 return RT_BOOL(pVmcb->ctrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
1876}
1877
1878/**
1879 * Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
1880 *
1881 * @returns @c true if virtual-interrupts are masked, @c false otherwise.
1882 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1883 * @param pCtx Pointer to the context.
1884 *
1885 * @remarks Should only be called when SVM feature is exposed to the guest.
1886 */
1887DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu, PCCPUMCTX pCtx)
1888{
1889 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1890 return false;
1891 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1892 if (HMHasGuestSvmVmcbCached(pVCpu))
1893 return HMIsGuestSvmVirtIntrMasking(pVCpu);
1894 return pVmcb->ctrl.IntCtrl.n.u1VIntrMasking;
1895}
1896
1897/**
1898 * Checks if the nested-guest VMCB has nested-paging enabled.
1899 *
1900 * @returns @c true if nested-paging is enabled, @c false otherwise.
1901 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1902 * @param pCtx Pointer to the context.
1903 *
1904 * @remarks Should only be called when SVM feature is exposed to the guest.
1905 */
1906DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu, PCCPUMCTX pCtx)
1907{
1908 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1909 return false;
1910 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1911 if (HMHasGuestSvmVmcbCached(pVCpu))
1912 return HMIsGuestSvmNestedPagingEnabled(pVCpu);
1913 return pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging;
1914}
1915
1916/**
1917 * Gets the nested-guest VMCB pause-filter count.
1918 *
1919 * @returns The pause-filter count.
1920 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1921 * @param pCtx Pointer to the context.
1922 *
1923 * @remarks Should only be called when SVM feature is exposed to the guest.
1924 */
1925DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PVMCPU pVCpu, PCCPUMCTX pCtx)
1926{
1927 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
1928 return false;
1929 PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcb);
1930 if (HMHasGuestSvmVmcbCached(pVCpu))
1931 return HMGetGuestSvmPauseFilterCount(pVCpu);
1932 return pVmcb->ctrl.u16PauseFilterCount;
1933}
1934
1935/**
1936 * Updates the NextRIP (NRIP) field in the nested-guest VMCB.
1937 *
1938 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1939 * @param pCtx Pointer to the context.
1940 * @param cbInstr The length of the current instruction in bytes.
1941 *
1942 * @remarks Should only be called when SVM feature is exposed to the guest.
1943 */
1944DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t cbInstr)
1945{
1946 RT_NOREF(pVCpu);
1947 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1948 PSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1949 Assert(pVmcb);
1950 pVmcb->ctrl.u64NextRIP = pCtx->rip + cbInstr;
1951}
1952
1953/**
1954 * Checks whether one of the given Pin-based VM-execution controls are set when
1955 * executing a nested-guest.
1956 *
1957 * @returns @c true if set, @c false otherwise.
1958 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1959 * @param pCtx Pointer to the context.
1960 * @param uPinCtls The Pin-based VM-execution controls to check.
1961 *
1962 * @remarks This does not check if all given controls are set if more than one
1963 * control is passed in @a uPinCtl.
1964 */
1965DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint32_t uPinCtls)
1966{
1967 RT_NOREF(pVCpu);
1968 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1969 Assert(pCtx->hwvirt.vmx.fInVmxNonRootMode);
1970 Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1971 return RT_BOOL(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32PinCtls & uPinCtls);
1972}
1973
1974/**
1975 * Checks whether one of the given Processor-based VM-execution controls are set
1976 * when executing a nested-guest.
1977 *
1978 * @returns @c true if set, @c false otherwise.
1979 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1980 * @param pCtx Pointer to the context.
1981 * @param uProcCtls The Processor-based VM-execution controls to check.
1982 *
1983 * @remarks This does not check if all given controls are set if more than one
1984 * control is passed in @a uProcCtls.
1985 */
1986DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint32_t uProcCtls)
1987{
1988 RT_NOREF(pVCpu);
1989 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1990 Assert(pCtx->hwvirt.vmx.fInVmxNonRootMode);
1991 Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1992 return RT_BOOL(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32ProcCtls & uProcCtls);
1993}
1994
1995/**
1996 * Checks whether one of the given Secondary Processor-based VM-execution controls
1997 * are set when executing a nested-guest.
1998 *
1999 * @returns @c true if set, @c false otherwise.
2000 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2001 * @param pCtx Pointer to the context.
2002 * @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2003 * check.
2004 *
2005 * @remarks This does not check if all given controls are set if more than one
2006 * control is passed in @a uProcCtls2.
2007 */
2008DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PVMCPU pVCpu, PCCPUMCTX pCtx, uint32_t uProcCtls2)
2009{
2010 RT_NOREF(pVCpu);
2011 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
2012 Assert(pCtx->hwvirt.vmx.fInVmxNonRootMode);
2013 Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2014 return RT_BOOL(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32ProcCtls2 & uProcCtls2);
2015}
2016
2017
2018/**
2019 * Checks whether one of the given VM-exit controls are set when executing a
2020 * nested-guest.
2021 *
2022 * @returns @c true if set, @c false otherwise.
2023 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2024 * @param pCtx Pointer to the context.
2025 * @param uExitCtls The VM-exit controls to check.
2026 *
2027 * @remarks This does not check if all given controls are set if more than one
2028 * control is passed in @a uExitCtls.
2029 */
2030DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint32_t uExitCtls)
2031{
2032 RT_NOREF(pVCpu);
2033 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
2034 Assert(pCtx->hwvirt.vmx.fInVmxNonRootMode);
2035 Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2036 return RT_BOOL(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u32ExitCtls & uExitCtls);
2037}
2038
2039
2040/**
2041 * Returns the guest-physical address of the APIC-access page when executing a
2042 * nested-guest.
2043 *
2044 * @returns The APIC-access page guest-physical address.
2045 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2046 * @param pCtx Pointer to the context.
2047 */
2048DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PVMCPU pVCpu, PCCPUMCTX pCtx)
2049{
2050 RT_NOREF(pVCpu);
2051 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
2052 Assert(pCtx->hwvirt.vmx.fInVmxNonRootMode);
2053 Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2054 return pCtx->hwvirt.vmx.CTX_SUFF(pVmcs)->u64AddrApicAccess.u;
2055}
2056
2057# endif /* !IN_RC */
2058
2059#endif /* IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS */
2060
2061/** @} */
2062
2063
2064/** @name Hypervisor Register Getters.
2065 * @{ */
2066VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
2067VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
2068VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
2069VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
2070VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
2071VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
2072#if 0 /* these are not correct. */
2073VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
2074VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
2075VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2076VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
2077#endif
2078/** This register is only saved on fatal traps. */
2079VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
2080VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
2081/** This register is only saved on fatal traps. */
2082VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
2083/** This register is only saved on fatal traps. */
2084VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
2085VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
2086VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
2087VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
2088VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
2089VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
2090VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
2091VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
2092VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
2093VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
2094VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
2095VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
2096VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
2097VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
2098VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
2099VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
2100VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
2101VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
2102VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
2103/** @} */
2104
2105/** @name Hypervisor Register Setters.
2106 * @{ */
2107VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
2108VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
2109VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
2110VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
2111VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
2112VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
2113VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
2114VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
2115VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
2116VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
2117VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
2118VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
2119VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
2120VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
2121VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
2122VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
2123VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
2124VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
2125VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
2126VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
2127VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
2128VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
2129VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
2130/** @} */
2131
2132VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
2133VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
2134VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
2135VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
2136VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
2137VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
2138VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
2139VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
2140VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
2141VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
2142VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
2143
2144/** @name Changed flags.
2145 * These flags are used to keep track of which important register that
2146 * have been changed since last they were reset. The only one allowed
2147 * to clear them is REM!
2148 * @{
2149 */
2150#define CPUM_CHANGED_FPU_REM RT_BIT(0)
2151#define CPUM_CHANGED_CR0 RT_BIT(1)
2152#define CPUM_CHANGED_CR4 RT_BIT(2)
2153#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
2154#define CPUM_CHANGED_CR3 RT_BIT(4)
2155#define CPUM_CHANGED_GDTR RT_BIT(5)
2156#define CPUM_CHANGED_IDTR RT_BIT(6)
2157#define CPUM_CHANGED_LDTR RT_BIT(7)
2158#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
2159#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
2160#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
2161#define CPUM_CHANGED_CPUID RT_BIT(11)
2162#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
2163 | CPUM_CHANGED_CR0 \
2164 | CPUM_CHANGED_CR4 \
2165 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
2166 | CPUM_CHANGED_CR3 \
2167 | CPUM_CHANGED_GDTR \
2168 | CPUM_CHANGED_IDTR \
2169 | CPUM_CHANGED_LDTR \
2170 | CPUM_CHANGED_TR \
2171 | CPUM_CHANGED_SYSENTER_MSR \
2172 | CPUM_CHANGED_HIDDEN_SEL_REGS \
2173 | CPUM_CHANGED_CPUID )
2174/** @} */
2175
2176VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
2177VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
2178VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
2179VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
2180VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
2181VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
2182VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
2183VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
2184VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
2185VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
2186VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
2187VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
2188VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
2189VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
2190VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
2191VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
2192VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
2193VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
2194VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
2195VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
2196VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
2197VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
2198 uint64_t *puValidEfer);
2199VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
2200VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
2201
2202/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
2203typedef enum CPUMINTERRUPTIBILITY
2204{
2205 CPUMINTERRUPTIBILITY_INVALID = 0,
2206 CPUMINTERRUPTIBILITY_UNRESTRAINED,
2207 CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
2208 CPUMINTERRUPTIBILITY_INT_DISABLED,
2209 CPUMINTERRUPTIBILITY_INT_INHIBITED,
2210 CPUMINTERRUPTIBILITY_NMI_INHIBIT,
2211 CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
2212 CPUMINTERRUPTIBILITY_END,
2213 CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
2214} CPUMINTERRUPTIBILITY;
2215
2216/**
2217 * Calculates the interruptiblity of the guest.
2218 *
2219 * @returns Interruptibility level.
2220 * @param pVCpu The cross context virtual CPU structure.
2221 */
2222VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
2223
2224
2225/** @name Typical scalable bus frequency values.
2226 * @{ */
2227/** Special internal value indicating that we don't know the frequency.
2228 * @internal */
2229#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
2230#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
2231#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
2232#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
2233#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
2234#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
2235#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
2236#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
2237/** @} */
2238
2239
2240#ifdef IN_RING3
2241/** @defgroup grp_cpum_r3 The CPUM ring-3 API
2242 * @{
2243 */
2244
2245VMMR3DECL(int) CPUMR3Init(PVM pVM);
2246VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
2247VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
2248VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
2249VMMR3DECL(int) CPUMR3Term(PVM pVM);
2250VMMR3DECL(void) CPUMR3Reset(PVM pVM);
2251VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
2252VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
2253VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
2254
2255VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
2256VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
2257VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
2258 uint8_t bModel, uint8_t bStepping);
2259VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
2260VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
2261VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
2262VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
2263VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
2264VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
2265VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
2266
2267VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
2268
2269# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
2270/** @name APIs for the CPUID raw-mode patch (legacy).
2271 * @{ */
2272VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
2273VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
2274VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
2275VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
2276VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
2277VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
2278VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
2279/** @} */
2280# endif
2281
2282/** @} */
2283#endif /* IN_RING3 */
2284
2285#ifdef IN_RC
2286/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
2287 * @{
2288 */
2289
2290/**
2291 * Calls a guest trap/interrupt handler directly
2292 *
2293 * Assumes a trap stack frame has already been setup on the guest's stack!
2294 * This function does not return!
2295 *
2296 * @param pRegFrame Original trap/interrupt context
2297 * @param selCS Code selector of handler
2298 * @param pHandler GC virtual address of handler
2299 * @param eflags Callee's EFLAGS
2300 * @param selSS Stack selector for handler
2301 * @param pEsp Stack address for handler
2302 */
2303DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
2304 uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
2305
2306/**
2307 * Call guest V86 code directly.
2308 *
2309 * This function does not return!
2310 *
2311 * @param pRegFrame Original trap/interrupt context
2312 */
2313DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
2314
2315VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
2316VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
2317#ifdef VBOX_WITH_RAW_RING1
2318VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
2319#endif
2320VMMRCDECL(void) CPUMRCProcessForceFlag(PVMCPU pVCpu);
2321
2322/** @} */
2323#endif /* IN_RC */
2324
2325#ifdef IN_RING0
2326/** @defgroup grp_cpum_r0 The CPUM ring-0 API
2327 * @{
2328 */
2329VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
2330VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
2331VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
2332DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPU pVCpu);
2333DECLASM(void) CPUMR0TouchHostFpu(void);
2334VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu);
2335VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu);
2336VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu);
2337VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
2338VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
2339VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
2340
2341VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
2342VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
2343#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
2344VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
2345#endif
2346
2347/** @} */
2348#endif /* IN_RING0 */
2349
2350/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
2351 * @{
2352 */
2353VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPU pVCpu);
2354VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPU pVCpu);
2355VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPU pVCpu);
2356VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPU pVCpu);
2357VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPU pVCpu);
2358/** @} */
2359
2360
2361#endif /* !VBOX_FOR_DTRACE_LIB */
2362/** @} */
2363RT_C_DECLS_END
2364
2365
2366#endif /* !VBOX_INCLUDED_vmm_cpum_h */
2367
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