VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 105224

Last change on this file since 105224 was 100940, checked in by vboxsync, 16 months ago

VMM: Make CPUMIsGuestIn64Bit[Code|CodeEx|Slow] use a const CPUM context parameter.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 16.0 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_cpum_h
37#define VBOX_INCLUDED_vmm_cpum_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/types.h>
43#include <VBox/vmm/cpumctx.h>
44#include <VBox/vmm/stam.h>
45#include <VBox/vmm/vmapi.h>
46#include <VBox/vmm/cpum-common.h>
47
48
49/** @defgroup grp_cpum The CPU Monitor / Manager API
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * CPU Vendor.
56 */
57typedef enum CPUMCPUVENDOR
58{
59 CPUMCPUVENDOR_INVALID = 0,
60 CPUMCPUVENDOR_INTEL,
61 CPUMCPUVENDOR_AMD,
62 CPUMCPUVENDOR_VIA,
63 CPUMCPUVENDOR_CYRIX,
64 CPUMCPUVENDOR_SHANGHAI,
65 CPUMCPUVENDOR_HYGON,
66 CPUMCPUVENDOR_APPLE, /**< ARM */
67 CPUMCPUVENDOR_UNKNOWN,
68 /** 32bit hackishness. */
69 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
70} CPUMCPUVENDOR;
71
72
73/**
74 * CPU architecture.
75 */
76typedef enum CPUMARCH
77{
78 /** Invalid zero value. */
79 kCpumArch_Invalid = 0,
80 /** x86 based architecture (includes 64-bit). */
81 kCpumArch_X86,
82 /** ARM based architecture (includs both AArch32 and AArch64). */
83 kCpumArch_Arm,
84
85 /** @todo RiscV, Mips, ... ;). */
86
87 /*
88 * Unknown.
89 */
90 kCpumArch_Unknown,
91
92 kCpumArch_32BitHack = 0x7fffffff
93} CPUMARCH;
94
95
96/**
97 * CPU microarchitectures and in processor generations.
98 *
99 * @remarks The separation here is sometimes a little bit too finely grained,
100 * and the differences is more like processor generation than micro
101 * arch. This can be useful, so we'll provide functions for getting at
102 * more coarse grained info.
103 */
104typedef enum CPUMMICROARCH
105{
106 kCpumMicroarch_Invalid = 0,
107
108 /*
109 * x86 and AMD64 CPUs.
110 */
111
112 kCpumMicroarch_Intel_First,
113
114 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
115 kCpumMicroarch_Intel_80186,
116 kCpumMicroarch_Intel_80286,
117 kCpumMicroarch_Intel_80386,
118 kCpumMicroarch_Intel_80486,
119 kCpumMicroarch_Intel_P5,
120
121 kCpumMicroarch_Intel_P6_Core_Atom_First,
122 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
123 kCpumMicroarch_Intel_P6_II,
124 kCpumMicroarch_Intel_P6_III,
125
126 kCpumMicroarch_Intel_P6_M_Banias,
127 kCpumMicroarch_Intel_P6_M_Dothan,
128 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
129
130 kCpumMicroarch_Intel_Core2_First,
131 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
132 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
133 kCpumMicroarch_Intel_Core2_End,
134
135 kCpumMicroarch_Intel_Core7_First,
136 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
137 kCpumMicroarch_Intel_Core7_Westmere,
138 kCpumMicroarch_Intel_Core7_SandyBridge,
139 kCpumMicroarch_Intel_Core7_IvyBridge,
140 kCpumMicroarch_Intel_Core7_Haswell,
141 kCpumMicroarch_Intel_Core7_Broadwell,
142 kCpumMicroarch_Intel_Core7_Skylake,
143 kCpumMicroarch_Intel_Core7_KabyLake,
144 kCpumMicroarch_Intel_Core7_CoffeeLake,
145 kCpumMicroarch_Intel_Core7_WhiskeyLake,
146 kCpumMicroarch_Intel_Core7_CascadeLake,
147 kCpumMicroarch_Intel_Core7_CannonLake, /**< Limited 10nm. */
148 kCpumMicroarch_Intel_Core7_CometLake, /**< 10th gen, 14nm desktop + high power mobile. */
149 kCpumMicroarch_Intel_Core7_IceLake, /**< 10th gen, 10nm mobile and some Xeons. Actually 'Sunny Cove' march. */
150 kCpumMicroarch_Intel_Core7_SunnyCove = kCpumMicroarch_Intel_Core7_IceLake,
151 kCpumMicroarch_Intel_Core7_RocketLake, /**< 11th gen, 14nm desktop + high power mobile. Aka 'Cypress Cove', backport of 'Willow Cove' to 14nm. */
152 kCpumMicroarch_Intel_Core7_CypressCove = kCpumMicroarch_Intel_Core7_RocketLake,
153 kCpumMicroarch_Intel_Core7_TigerLake, /**< 11th gen, 10nm mobile. Actually 'Willow Cove' march. */
154 kCpumMicroarch_Intel_Core7_WillowCove = kCpumMicroarch_Intel_Core7_TigerLake,
155 kCpumMicroarch_Intel_Core7_AlderLake, /**< 12th gen, 10nm all platforms(?). */
156 kCpumMicroarch_Intel_Core7_SapphireRapids, /**< 12th? gen, 10nm server? */
157 kCpumMicroarch_Intel_Core7_End,
158
159 kCpumMicroarch_Intel_Atom_First,
160 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
161 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
162 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
163 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
164 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
165 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
166 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
167 kCpumMicroarch_Intel_Atom_Unknown,
168 kCpumMicroarch_Intel_Atom_End,
169
170
171 kCpumMicroarch_Intel_Phi_First,
172 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
173 kCpumMicroarch_Intel_Phi_KnightsCorner,
174 kCpumMicroarch_Intel_Phi_KnightsLanding,
175 kCpumMicroarch_Intel_Phi_KnightsHill,
176 kCpumMicroarch_Intel_Phi_KnightsMill,
177 kCpumMicroarch_Intel_Phi_End,
178
179 kCpumMicroarch_Intel_P6_Core_Atom_End,
180
181 kCpumMicroarch_Intel_NB_First,
182 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
183 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
184 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
185 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
186 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
187 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
188 kCpumMicroarch_Intel_NB_Unknown,
189 kCpumMicroarch_Intel_NB_End,
190
191 kCpumMicroarch_Intel_Unknown,
192 kCpumMicroarch_Intel_End,
193
194 kCpumMicroarch_AMD_First,
195 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
196 kCpumMicroarch_AMD_Am386,
197 kCpumMicroarch_AMD_Am486,
198 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
199 kCpumMicroarch_AMD_K5,
200 kCpumMicroarch_AMD_K6,
201
202 kCpumMicroarch_AMD_K7_First,
203 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
204 kCpumMicroarch_AMD_K7_Spitfire,
205 kCpumMicroarch_AMD_K7_Thunderbird,
206 kCpumMicroarch_AMD_K7_Morgan,
207 kCpumMicroarch_AMD_K7_Thoroughbred,
208 kCpumMicroarch_AMD_K7_Barton,
209 kCpumMicroarch_AMD_K7_Unknown,
210 kCpumMicroarch_AMD_K7_End,
211
212 kCpumMicroarch_AMD_K8_First,
213 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
214 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
215 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
216 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
217 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
218 kCpumMicroarch_AMD_K8_End,
219
220 kCpumMicroarch_AMD_K10,
221 kCpumMicroarch_AMD_K10_Lion,
222 kCpumMicroarch_AMD_K10_Llano,
223 kCpumMicroarch_AMD_Bobcat,
224 kCpumMicroarch_AMD_Jaguar,
225
226 kCpumMicroarch_AMD_15h_First,
227 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
228 kCpumMicroarch_AMD_15h_Piledriver,
229 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
230 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
231 kCpumMicroarch_AMD_15h_Unknown,
232 kCpumMicroarch_AMD_15h_End,
233
234 kCpumMicroarch_AMD_16h_First,
235 kCpumMicroarch_AMD_16h_End,
236
237 kCpumMicroarch_AMD_Zen_First,
238 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
239 kCpumMicroarch_AMD_Zen_End,
240
241 kCpumMicroarch_AMD_Unknown,
242 kCpumMicroarch_AMD_End,
243
244 kCpumMicroarch_Hygon_First,
245 kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
246 kCpumMicroarch_Hygon_Unknown,
247 kCpumMicroarch_Hygon_End,
248
249 kCpumMicroarch_VIA_First,
250 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
251 kCpumMicroarch_Centaur_C2,
252 kCpumMicroarch_Centaur_C3,
253 kCpumMicroarch_VIA_C3_M2,
254 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
255 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
256 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
257 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
258 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
259 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
260 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
261 kCpumMicroarch_VIA_Isaiah,
262 kCpumMicroarch_VIA_Unknown,
263 kCpumMicroarch_VIA_End,
264
265 kCpumMicroarch_Shanghai_First,
266 kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
267 kCpumMicroarch_Shanghai_Unknown,
268 kCpumMicroarch_Shanghai_End,
269
270 kCpumMicroarch_Cyrix_First,
271 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
272 kCpumMicroarch_Cyrix_M1,
273 kCpumMicroarch_Cyrix_MediaGX,
274 kCpumMicroarch_Cyrix_MediaGXm,
275 kCpumMicroarch_Cyrix_M2,
276 kCpumMicroarch_Cyrix_Unknown,
277 kCpumMicroarch_Cyrix_End,
278
279 kCpumMicroarch_NEC_First,
280 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
281 kCpumMicroarch_NEC_V30,
282 kCpumMicroarch_NEC_End,
283
284 /*
285 * ARM CPUs.
286 */
287 kCpumMicroarch_Apple_First,
288 kCpumMicroarch_Apple_M1 = kCpumMicroarch_Apple_First,
289 kCpumMicroarch_Apple_M2,
290 kCpumMicroarch_Apple_End,
291
292 /*
293 * Unknown.
294 */
295 kCpumMicroarch_Unknown,
296
297 kCpumMicroarch_32BitHack = 0x7fffffff
298} CPUMMICROARCH;
299
300
301/** Predicate macro for catching netburst CPUs. */
302#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
303 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
304
305/** Predicate macro for catching Core7 CPUs. */
306#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
307 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
308
309/** Predicate macro for catching Core 2 CPUs. */
310#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
311 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
312
313/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
314#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
315 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
316
317/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
318#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
319 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
320
321/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
322#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
323
324/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
325#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
326
327/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
328#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
329
330/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
331#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
332
333/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
334 * decendants). */
335#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
336 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
337
338/** Predicate macro for catching AMD Family 16H CPUs. */
339#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
340 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
341
342/** Predicate macro for catching AMD Zen Family CPUs. */
343#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
344 ((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
345
346/** Predicate macro for catching Apple (ARM) CPUs. */
347#define CPUMMICROARCH_IS_APPLE(a_enmMicroarch) \
348 ((a_enmMicroarch) >= kCpumMicroarch_Apple_First && (a_enmMicroarch) <= kCpumMicroarch_Apple_End)
349
350
351/*
352 * Include the target specific header.
353 * This uses several of the above types, so it must be postponed till here.
354 */
355#ifndef VBOX_VMM_TARGET_ARMV8
356# include <VBox/vmm/cpum-x86-amd64.h>
357#else
358# include <VBox/vmm/cpum-armv8.h>
359#endif
360
361
362RT_C_DECLS_BEGIN
363
364#ifndef VBOX_FOR_DTRACE_LIB
365
366VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
367VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
368VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
369VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
370VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
371
372/** @name Guest Register Getters.
373 * @{ */
374VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
375VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
376VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
377VMMDECL(CPUMARCH) CPUMGetGuestArch(PCVM pVM);
378VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
379VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth);
380/** @} */
381
382/** @name Misc Guest Predicate Functions.
383 * @{ */
384VMMDECL(bool) CPUMIsGuestIn64BitCode(PCVMCPU pVCpu);
385/** @} */
386
387VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
388VMMDECL(CPUMARCH) CPUMGetHostArch(PCVM pVM);
389VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
390
391#ifdef IN_RING3
392/** @defgroup grp_cpum_r3 The CPUM ring-3 API
393 * @{
394 */
395
396VMMR3DECL(int) CPUMR3Init(PVM pVM);
397VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
398VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
399VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
400VMMR3DECL(int) CPUMR3Term(PVM pVM);
401VMMR3DECL(void) CPUMR3Reset(PVM pVM);
402VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
403VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
404VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
405VMMR3DECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
406
407VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
408/** Pointer to CPUMR3DbGetEntries. */
409typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
410VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
411/** Pointer to CPUMR3DbGetEntryByIndex. */
412typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
413VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
414/** Pointer to CPUMR3DbGetEntryByName. */
415typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
416
417VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
418VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
419/** @} */
420#endif /* IN_RING3 */
421
422#endif /* !VBOX_FOR_DTRACE_LIB */
423/** @} */
424RT_C_DECLS_END
425
426
427#endif /* !VBOX_INCLUDED_vmm_cpum_h */
428
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette