cpum.h@ 107650

Last change on this file since 107650 was 107650, checked in by vboxsync, 3 weeks ago
VMM/CPUM,++: Made the HostFeatures match the host when targeting x86 guests on arm64 hosts. Merged and deduplicated code targeting x86 & amd64. jiraref:VBP-1470
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 65.2 KB

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpum_h
37	#define VBOX_INCLUDED_vmm_cpum_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <VBox/vmm/cpumctx.h>
44	#include <VBox/vmm/stam.h>
45	#include <VBox/vmm/vmapi.h>
46	#include <VBox/vmm/cpum-common.h>
47
48
49	/** @defgroup grp_cpum The CPU Monitor / Manager API
50	* @ingroup grp_vmm
51	* @{
52	*/
53
54	/**
55	* CPU Vendor.
56	*/
57	typedef enum CPUMCPUVENDOR
58	{
59	CPUMCPUVENDOR_INVALID = 0,
60	CPUMCPUVENDOR_INTEL,
61	CPUMCPUVENDOR_AMD,
62	CPUMCPUVENDOR_VIA,
63	CPUMCPUVENDOR_CYRIX,
64	CPUMCPUVENDOR_SHANGHAI,
65	CPUMCPUVENDOR_HYGON,
66	CPUMCPUVENDOR_APPLE, /*< ARM /
67	CPUMCPUVENDOR_UNKNOWN,
68	/** 32bit hackishness. */
69	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
70	} CPUMCPUVENDOR;
71
72
73	/**
74	* CPU architecture.
75	*/
76	typedef enum CPUMARCH
77	{
78	/** Invalid zero value. */
79	kCpumArch_Invalid = 0,
80	/** x86 based architecture (includes 64-bit). */
81	kCpumArch_X86,
82	/** ARM based architecture (includs both AArch32 and AArch64). */
83	kCpumArch_Arm,
84
85	/** @todo RiscV, Mips, ... ;). */
86
87	/*
88	* Unknown.
89	*/
90	kCpumArch_Unknown,
91
92	kCpumArch_32BitHack = 0x7fffffff
93	} CPUMARCH;
94
95
96	/**
97	* CPU microarchitectures and in processor generations.
98	*
99	* @remarks The separation here is sometimes a little bit too finely grained,
100	* and the differences is more like processor generation than micro
101	* arch. This can be useful, so we'll provide functions for getting at
102	* more coarse grained info.
103	*/
104	typedef enum CPUMMICROARCH
105	{
106	kCpumMicroarch_Invalid = 0,
107
108	/*
109	* x86 and AMD64 CPUs.
110	*/
111
112	kCpumMicroarch_Intel_First,
113
114	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
115	kCpumMicroarch_Intel_80186,
116	kCpumMicroarch_Intel_80286,
117	kCpumMicroarch_Intel_80386,
118	kCpumMicroarch_Intel_80486,
119	kCpumMicroarch_Intel_P5,
120
121	kCpumMicroarch_Intel_P6_Core_Atom_First,
122	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
123	kCpumMicroarch_Intel_P6_II,
124	kCpumMicroarch_Intel_P6_III,
125
126	kCpumMicroarch_Intel_P6_M_Banias,
127	kCpumMicroarch_Intel_P6_M_Dothan,
128	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
129
130	kCpumMicroarch_Intel_Core2_First,
131	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /*< 65nm, Merom/Conroe/Kentsfield/Tigerton /
132	kCpumMicroarch_Intel_Core2_Penryn, /*< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown /
133	kCpumMicroarch_Intel_Core2_End,
134
135	kCpumMicroarch_Intel_Core7_First,
136	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
137	kCpumMicroarch_Intel_Core7_Westmere,
138	kCpumMicroarch_Intel_Core7_SandyBridge,
139	kCpumMicroarch_Intel_Core7_IvyBridge,
140	kCpumMicroarch_Intel_Core7_Haswell,
141	kCpumMicroarch_Intel_Core7_Broadwell,
142	kCpumMicroarch_Intel_Core7_Skylake,
143	kCpumMicroarch_Intel_Core7_KabyLake,
144	kCpumMicroarch_Intel_Core7_CoffeeLake,
145	kCpumMicroarch_Intel_Core7_WhiskeyLake,
146	kCpumMicroarch_Intel_Core7_CascadeLake,
147	kCpumMicroarch_Intel_Core7_CannonLake, /*< Limited 10nm. /
148	kCpumMicroarch_Intel_Core7_CometLake, /*< 10th gen, 14nm desktop + high power mobile. /
149	kCpumMicroarch_Intel_Core7_IceLake, /*< 10th gen, 10nm mobile and some Xeons. Actually 'Sunny Cove' march. /
150	kCpumMicroarch_Intel_Core7_SunnyCove = kCpumMicroarch_Intel_Core7_IceLake,
151	kCpumMicroarch_Intel_Core7_RocketLake, /*< 11th gen, 14nm desktop + high power mobile. Aka 'Cypress Cove', backport of 'Willow Cove' to 14nm. /
152	kCpumMicroarch_Intel_Core7_CypressCove = kCpumMicroarch_Intel_Core7_RocketLake,
153	kCpumMicroarch_Intel_Core7_TigerLake, /*< 11th gen, 10nm mobile. Actually 'Willow Cove' march. /
154	kCpumMicroarch_Intel_Core7_WillowCove = kCpumMicroarch_Intel_Core7_TigerLake,
155	kCpumMicroarch_Intel_Core7_AlderLake, /*< 12th gen, 10nm all platforms(?). /
156	kCpumMicroarch_Intel_Core7_SapphireRapids, /*< 12th? gen, 10nm server? /
157	kCpumMicroarch_Intel_Core7_End,
158
159	kCpumMicroarch_Intel_Atom_First,
160	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
161	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
162	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
163	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
164	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
165	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
166	kCpumMicroarch_Intel_Atom_GoldmontPlus, /*< 14nm /
167	kCpumMicroarch_Intel_Atom_Unknown,
168	kCpumMicroarch_Intel_Atom_End,
169
170
171	kCpumMicroarch_Intel_Phi_First,
172	kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
173	kCpumMicroarch_Intel_Phi_KnightsCorner,
174	kCpumMicroarch_Intel_Phi_KnightsLanding,
175	kCpumMicroarch_Intel_Phi_KnightsHill,
176	kCpumMicroarch_Intel_Phi_KnightsMill,
177	kCpumMicroarch_Intel_Phi_End,
178
179	kCpumMicroarch_Intel_P6_Core_Atom_End,
180
181	kCpumMicroarch_Intel_NB_First,
182	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
183	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
184	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
185	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
186	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
187	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
188	kCpumMicroarch_Intel_NB_Unknown,
189	kCpumMicroarch_Intel_NB_End,
190
191	kCpumMicroarch_Intel_Unknown,
192	kCpumMicroarch_Intel_End,
193
194	kCpumMicroarch_AMD_First,
195	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
196	kCpumMicroarch_AMD_Am386,
197	kCpumMicroarch_AMD_Am486,
198	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
199	kCpumMicroarch_AMD_K5,
200	kCpumMicroarch_AMD_K6,
201
202	kCpumMicroarch_AMD_K7_First,
203	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
204	kCpumMicroarch_AMD_K7_Spitfire,
205	kCpumMicroarch_AMD_K7_Thunderbird,
206	kCpumMicroarch_AMD_K7_Morgan,
207	kCpumMicroarch_AMD_K7_Thoroughbred,
208	kCpumMicroarch_AMD_K7_Barton,
209	kCpumMicroarch_AMD_K7_Unknown,
210	kCpumMicroarch_AMD_K7_End,
211
212	kCpumMicroarch_AMD_K8_First,
213	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
214	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
215	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
216	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
217	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
218	kCpumMicroarch_AMD_K8_End,
219
220	kCpumMicroarch_AMD_K10,
221	kCpumMicroarch_AMD_K10_Lion,
222	kCpumMicroarch_AMD_K10_Llano,
223	kCpumMicroarch_AMD_Bobcat,
224	kCpumMicroarch_AMD_Jaguar,
225
226	kCpumMicroarch_AMD_15h_First,
227	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
228	kCpumMicroarch_AMD_15h_Piledriver,
229	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
230	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
231	kCpumMicroarch_AMD_15h_Unknown,
232	kCpumMicroarch_AMD_15h_End,
233
234	kCpumMicroarch_AMD_16h_First,
235	kCpumMicroarch_AMD_16h_End,
236
237	kCpumMicroarch_AMD_Zen_First,
238	kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
239	kCpumMicroarch_AMD_Zen_End,
240
241	kCpumMicroarch_AMD_Unknown,
242	kCpumMicroarch_AMD_End,
243
244	kCpumMicroarch_Hygon_First,
245	kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
246	kCpumMicroarch_Hygon_Unknown,
247	kCpumMicroarch_Hygon_End,
248
249	kCpumMicroarch_VIA_First,
250	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
251	kCpumMicroarch_Centaur_C2,
252	kCpumMicroarch_Centaur_C3,
253	kCpumMicroarch_VIA_C3_M2,
254	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
255	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
256	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
257	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
258	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
259	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
260	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
261	kCpumMicroarch_VIA_Isaiah,
262	kCpumMicroarch_VIA_Unknown,
263	kCpumMicroarch_VIA_End,
264
265	kCpumMicroarch_Shanghai_First,
266	kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
267	kCpumMicroarch_Shanghai_Unknown,
268	kCpumMicroarch_Shanghai_End,
269
270	kCpumMicroarch_Cyrix_First,
271	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
272	kCpumMicroarch_Cyrix_M1,
273	kCpumMicroarch_Cyrix_MediaGX,
274	kCpumMicroarch_Cyrix_MediaGXm,
275	kCpumMicroarch_Cyrix_M2,
276	kCpumMicroarch_Cyrix_Unknown,
277	kCpumMicroarch_Cyrix_End,
278
279	kCpumMicroarch_NEC_First,
280	kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
281	kCpumMicroarch_NEC_V30,
282	kCpumMicroarch_NEC_End,
283
284	/*
285	* ARM CPUs.
286	*/
287	kCpumMicroarch_Apple_First,
288	kCpumMicroarch_Apple_M1 = kCpumMicroarch_Apple_First,
289	kCpumMicroarch_Apple_M2,
290	kCpumMicroarch_Apple_End,
291
292	/*
293	* Unknown.
294	*/
295	kCpumMicroarch_Unknown,
296
297	kCpumMicroarch_32BitHack = 0x7fffffff
298	} CPUMMICROARCH;
299
300
301	/** Predicate macro for catching netburst CPUs. */
302	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
303	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
304
305	/** Predicate macro for catching Core7 CPUs. */
306	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
307	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
308
309	/** Predicate macro for catching Core 2 CPUs. */
310	#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
311	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
312
313	/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
314	#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
315	((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
316
317	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
318	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
319	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
320
321	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
322	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
323
324	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
325	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
326
327	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
328	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
329
330	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
331	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
332
333	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
334	* decendants). */
335	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
336	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
337
338	/** Predicate macro for catching AMD Family 16H CPUs. */
339	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
340	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
341
342	/** Predicate macro for catching AMD Zen Family CPUs. */
343	#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
344	((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
345
346	/** Predicate macro for catching Apple (ARM) CPUs. */
347	#define CPUMMICROARCH_IS_APPLE(a_enmMicroarch) \
348	((a_enmMicroarch) >= kCpumMicroarch_Apple_First && (a_enmMicroarch) <= kCpumMicroarch_Apple_End)
349
350
351	/**
352	* Common portion of the CPU feature structures.
353	*/
354	typedef struct CPUMFEATURESCOMMON
355	{
356	/** The microarchitecture. */
357	#ifndef VBOX_FOR_DTRACE_LIB
358	CPUMMICROARCH enmMicroarch;
359	#else
360	uint32_t enmMicroarch;
361	#endif
362	/** The CPU vendor (CPUMCPUVENDOR). */
363	uint8_t enmCpuVendor;
364	/** The maximum physical address width of the CPU. */
365	uint8_t cMaxPhysAddrWidth;
366	/** The maximum linear address width of the CPU. */
367	uint8_t cMaxLinearAddrWidth;
368	} CPUMFEATURESCOMMON;
369
370	/**
371	* CPU features and quirks for X86.
372	*
373	* This is mostly exploded CPUID info.
374	*/
375	typedef struct CPUMFEATURESX86
376	{
377	/** The microarchitecture. */
378	#ifndef VBOX_FOR_DTRACE_LIB
379	CPUMMICROARCH enmMicroarch;
380	#else
381	uint32_t enmMicroarch;
382	#endif
383	/** The CPU vendor (CPUMCPUVENDOR). */
384	uint8_t enmCpuVendor;
385	/** The maximum physical address width of the CPU. */
386	uint8_t cMaxPhysAddrWidth;
387	/** The maximum linear address width of the CPU. */
388	uint8_t cMaxLinearAddrWidth;
389
390	/** The CPU family. */
391	uint8_t uFamily;
392	/** The CPU model. */
393	uint8_t uModel;
394	/** The CPU stepping. */
395	uint8_t uStepping;
396	/** Max size of the extended state (or FPU state if no XSAVE). */
397	uint16_t cbMaxExtendedState;
398
399	/** Supports MSRs. */
400	uint32_t fMsr : 1;
401	/** Supports the page size extension (4/2 MB pages). */
402	uint32_t fPse : 1;
403	/** Supports 36-bit page size extension (4 MB pages can map memory above
404	* 4GB). */
405	uint32_t fPse36 : 1;
406	/** Supports physical address extension (PAE). */
407	uint32_t fPae : 1;
408	/** Supports page-global extension (PGE). */
409	uint32_t fPge : 1;
410	/** Page attribute table (PAT) support (page level cache control). */
411	uint32_t fPat : 1;
412	/** Supports the FXSAVE and FXRSTOR instructions. */
413	uint32_t fFxSaveRstor : 1;
414	/** Supports the XSAVE and XRSTOR instructions. */
415	uint32_t fXSaveRstor : 1;
416	/** Supports the XSAVEOPT instruction. */
417	uint32_t fXSaveOpt : 1;
418	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
419	uint32_t fOpSysXSaveRstor : 1;
420	/** Supports MMX. */
421	uint32_t fMmx : 1;
422	/** Supports AMD extensions to MMX instructions. */
423	uint32_t fAmdMmxExts : 1;
424	/** Supports SSE. */
425	uint32_t fSse : 1;
426	/** Supports SSE2. */
427	uint32_t fSse2 : 1;
428	/** Supports SSE3. */
429	uint32_t fSse3 : 1;
430	/** Supports SSSE3. */
431	uint32_t fSsse3 : 1;
432	/** Supports SSE4.1. */
433	uint32_t fSse41 : 1;
434	/** Supports SSE4.2. */
435	uint32_t fSse42 : 1;
436	/** Supports AVX. */
437	uint32_t fAvx : 1;
438	/** Supports AVX2. */
439	uint32_t fAvx2 : 1;
440	/** Supports AVX512 foundation. */
441	uint32_t fAvx512Foundation : 1;
442	/** Supports RDTSC. */
443	uint32_t fTsc : 1;
444	/** Intel SYSENTER/SYSEXIT support */
445	uint32_t fSysEnter : 1;
446	/** Supports MTRR. */
447	uint32_t fMtrr : 1;
448	/** First generation APIC. */
449	uint32_t fApic : 1;
450	/** Second generation APIC. */
451	uint32_t fX2Apic : 1;
452	/** Hypervisor present. */
453	uint32_t fHypervisorPresent : 1;
454	/** MWAIT & MONITOR instructions supported. */
455	uint32_t fMonitorMWait : 1;
456	/** MWAIT Extensions present. */
457	uint32_t fMWaitExtensions : 1;
458	/** Supports CMPXCHG8B. */
459	uint32_t fCmpXchg8b : 1;
460	/** Supports CMPXCHG16B in 64-bit mode. */
461	uint32_t fCmpXchg16b : 1;
462	/** Supports CLFLUSH. */
463	uint32_t fClFlush : 1;
464	/** Supports CLFLUSHOPT. */
465	uint32_t fClFlushOpt : 1;
466	/** Supports IA32_PRED_CMD.IBPB. */
467	uint32_t fIbpb : 1;
468	/** Supports IA32_SPEC_CTRL.IBRS. */
469	uint32_t fIbrs : 1;
470	/** Supports IA32_SPEC_CTRL.STIBP. */
471	uint32_t fStibp : 1;
472	/** Supports IA32_FLUSH_CMD. */
473	uint32_t fFlushCmd : 1;
474	/** Supports IA32_ARCH_CAP. */
475	uint32_t fArchCap : 1;
476	/** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
477	uint32_t fMdsClear : 1;
478	/** Supports PCID. */
479	uint32_t fPcid : 1;
480	/** Supports INVPCID. */
481	uint32_t fInvpcid : 1;
482	/** Supports read/write FSGSBASE instructions. */
483	uint32_t fFsGsBase : 1;
484	/** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
485	uint32_t fBmi1 : 1;
486	/** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
487	* and SHLX). */
488	uint32_t fBmi2 : 1;
489	/** Supports POPCNT instruction. */
490	uint32_t fPopCnt : 1;
491	/** Supports RDRAND instruction. */
492	uint32_t fRdRand : 1;
493	/** Supports RDSEED instruction. */
494	uint32_t fRdSeed : 1;
495	/** Supports Hardware Lock Elision (HLE). */
496	uint32_t fHle : 1;
497	/** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
498	uint32_t fRtm : 1;
499	/** Supports PCLMULQDQ instruction. */
500	uint32_t fPclMul : 1;
501	/** Supports AES-NI (six AESxxx instructions). */
502	uint32_t fAesNi : 1;
503	/** Support MOVBE instruction. */
504	uint32_t fMovBe : 1;
505	/** Support SHA instructions. */
506	uint32_t fSha : 1;
507	/** Support ADX instructions. */
508	uint32_t fAdx : 1;
509	/** Supports FMA. */
510	uint32_t fFma : 1;
511	/** Supports F16C. */
512	uint32_t fF16c : 1;
513
514	/** Supports AMD 3DNow instructions. */
515	uint32_t f3DNow : 1;
516	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
517	uint32_t f3DNowPrefetch : 1;
518
519	/** AMD64: Supports long mode. */
520	uint32_t fLongMode : 1;
521	/** AMD64: SYSCALL/SYSRET support. */
522	uint32_t fSysCall : 1;
523	/** AMD64: No-execute page table bit. */
524	uint32_t fNoExecute : 1;
525	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
526	uint32_t fLahfSahf : 1;
527	/** AMD64: Supports RDTSCP. */
528	uint32_t fRdTscP : 1;
529	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
530	uint32_t fMovCr8In32Bit : 1;
531	/** AMD64: Supports XOP (similar to VEX3/AVX). */
532	uint32_t fXop : 1;
533	/** AMD64: Supports ABM, i.e. the LZCNT instruction. */
534	uint32_t fAbm : 1;
535	/** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
536	* BLSFILL, BLSIC, T1MSKC, and TZMSK). */
537	uint32_t fTbm : 1;
538
539	/** Indicates that FPU instruction and data pointers may leak.
540	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
541	* is only saved and restored if an exception is pending. */
542	uint32_t fLeakyFxSR : 1;
543
544	/** Supports VEX instruction encoding (AVX, BMI, etc.). */
545	uint32_t fVex : 1;
546
547	/** AMD64: Supports AMD SVM. */
548	uint32_t fSvm : 1;
549
550	/** Support for Intel VMX. */
551	uint32_t fVmx : 1;
552
553	/** Indicates that speculative execution control CPUID bits and MSRs are exposed.
554	* The details are different for Intel and AMD but both have similar
555	* functionality. */
556	uint32_t fSpeculationControl : 1;
557
558	/** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
559	* @remarks Only safe use after CPUM ring-0 init! */
560	uint32_t fArchRdclNo : 1;
561	/** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
562	* @remarks Only safe use after CPUM ring-0 init! */
563	uint32_t fArchIbrsAll : 1;
564	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
565	* @remarks Only safe use after CPUM ring-0 init! */
566	uint32_t fArchRsbOverride : 1;
567	/** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
568	* @remarks Only safe use after CPUM ring-0 init! */
569	uint32_t fArchVmmNeedNotFlushL1d : 1;
570	/** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
571	* @remarks Only safe use after CPUM ring-0 init! */
572	uint32_t fArchMdsNo : 1;
573
574	/** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
575	* prior to the bit fields -> total of 24 bytes) */
576	uint32_t fPadding0 : 19;
577
578
579	/** @name SVM
580	* @{ */
581	/** SVM: Supports Nested-paging. */
582	uint32_t fSvmNestedPaging : 1;
583	/** SVM: Support LBR (Last Branch Record) virtualization. */
584	uint32_t fSvmLbrVirt : 1;
585	/** SVM: Supports SVM lock. */
586	uint32_t fSvmSvmLock : 1;
587	/** SVM: Supports Next RIP save. */
588	uint32_t fSvmNextRipSave : 1;
589	/** SVM: Supports TSC rate MSR. */
590	uint32_t fSvmTscRateMsr : 1;
591	/** SVM: Supports VMCB clean bits. */
592	uint32_t fSvmVmcbClean : 1;
593	/** SVM: Supports Flush-by-ASID. */
594	uint32_t fSvmFlusbByAsid : 1;
595	/** SVM: Supports decode assist. */
596	uint32_t fSvmDecodeAssists : 1;
597	/** SVM: Supports Pause filter. */
598	uint32_t fSvmPauseFilter : 1;
599	/** SVM: Supports Pause filter threshold. */
600	uint32_t fSvmPauseFilterThreshold : 1;
601	/** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
602	uint32_t fSvmAvic : 1;
603	/** SVM: Supports Virtualized VMSAVE/VMLOAD. */
604	uint32_t fSvmVirtVmsaveVmload : 1;
605	/** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
606	uint32_t fSvmVGif : 1;
607	/** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
608	uint32_t fSvmGmet : 1;
609	/** SVM: Supports AVIC in x2APIC mode. */
610	uint32_t fSvmX2Avic : 1;
611	/** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
612	uint32_t fSvmSSSCheck : 1;
613	/** SVM: Supports SPEC_CTRL virtualization. */
614	uint32_t fSvmSpecCtrl : 1;
615	/** SVM: Supports Read-Only Guest Page Table feature. */
616	uint32_t fSvmRoGpt : 1;
617	/** SVM: Supports HOST_MCE_OVERRIDE. */
618	uint32_t fSvmHostMceOverride : 1;
619	/** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
620	uint32_t fSvmTlbiCtl : 1;
621	/** SVM: Supports NMI virtualization. */
622	uint32_t fSvmVNmi : 1;
623	/** SVM: Supports IBS virtualizaiton. */
624	uint32_t fSvmIbsVirt : 1;
625	/** SVM: Supports Extended LVT AVIC access changes. */
626	uint32_t fSvmExtLvtAvicAccessChg : 1;
627	/** SVM: Supports Guest VMCB address check. */
628	uint32_t fSvmNstVirtVmcbAddrChk : 1;
629	/** SVM: Supports Bus Lock Threshold. */
630	uint32_t fSvmBusLockThreshold : 1;
631	/** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
632	uint32_t fSvmPadding0 : 7;
633	/** SVM: Maximum supported ASID. */
634	uint32_t uSvmMaxAsid;
635	/** @} */
636
637
638	/** VMX: Maximum physical address width. */
639	uint32_t cVmxMaxPhysAddrWidth : 8;
640
641	/** @name VMX basic controls.
642	* @{ */
643	/** VMX: Supports INS/OUTS VM-exit instruction info. */
644	uint32_t fVmxInsOutInfo : 1;
645	/** @} */
646
647	/** @name VMX Pin-based controls.
648	* @{ */
649	/** VMX: Supports external interrupt VM-exit. */
650	uint32_t fVmxExtIntExit : 1;
651	/** VMX: Supports NMI VM-exit. */
652	uint32_t fVmxNmiExit : 1;
653	/** VMX: Supports Virtual NMIs. */
654	uint32_t fVmxVirtNmi : 1;
655	/** VMX: Supports preemption timer. */
656	uint32_t fVmxPreemptTimer : 1;
657	/** VMX: Supports posted interrupts. */
658	uint32_t fVmxPostedInt : 1;
659	/** @} */
660
661	/** @name VMX Processor-based controls.
662	* @{ */
663	/** VMX: Supports Interrupt-window exiting. */
664	uint32_t fVmxIntWindowExit : 1;
665	/** VMX: Supports TSC offsetting. */
666	uint32_t fVmxTscOffsetting : 1;
667	/** VMX: Supports HLT exiting. */
668	uint32_t fVmxHltExit : 1;
669	/** VMX: Supports INVLPG exiting. */
670	uint32_t fVmxInvlpgExit : 1;
671	/** VMX: Supports MWAIT exiting. */
672	uint32_t fVmxMwaitExit : 1;
673	/** VMX: Supports RDPMC exiting. */
674	uint32_t fVmxRdpmcExit : 1;
675	/** VMX: Supports RDTSC exiting. */
676	uint32_t fVmxRdtscExit : 1;
677	/** VMX: Supports CR3-load exiting. */
678	uint32_t fVmxCr3LoadExit : 1;
679	/** VMX: Supports CR3-store exiting. */
680	uint32_t fVmxCr3StoreExit : 1;
681	/** VMX: Supports tertiary processor-based VM-execution controls. */
682	uint32_t fVmxTertiaryExecCtls : 1;
683	/** VMX: Supports CR8-load exiting. */
684	uint32_t fVmxCr8LoadExit : 1;
685	/** VMX: Supports CR8-store exiting. */
686	uint32_t fVmxCr8StoreExit : 1;
687	/** VMX: Supports TPR shadow. */
688	uint32_t fVmxUseTprShadow : 1;
689	/** VMX: Supports NMI-window exiting. */
690	uint32_t fVmxNmiWindowExit : 1;
691	/** VMX: Supports Mov-DRx exiting. */
692	uint32_t fVmxMovDRxExit : 1;
693	/** VMX: Supports Unconditional I/O exiting. */
694	uint32_t fVmxUncondIoExit : 1;
695	/** VMX: Supportgs I/O bitmaps. */
696	uint32_t fVmxUseIoBitmaps : 1;
697	/** VMX: Supports Monitor Trap Flag. */
698	uint32_t fVmxMonitorTrapFlag : 1;
699	/** VMX: Supports MSR bitmap. */
700	uint32_t fVmxUseMsrBitmaps : 1;
701	/** VMX: Supports MONITOR exiting. */
702	uint32_t fVmxMonitorExit : 1;
703	/** VMX: Supports PAUSE exiting. */
704	uint32_t fVmxPauseExit : 1;
705	/** VMX: Supports secondary processor-based VM-execution controls. */
706	uint32_t fVmxSecondaryExecCtls : 1;
707	/** @} */
708
709	/** @name VMX Secondary processor-based controls.
710	* @{ */
711	/** VMX: Supports virtualize-APIC access. */
712	uint32_t fVmxVirtApicAccess : 1;
713	/** VMX: Supports EPT (Extended Page Tables). */
714	uint32_t fVmxEpt : 1;
715	/** VMX: Supports descriptor-table exiting. */
716	uint32_t fVmxDescTableExit : 1;
717	/** VMX: Supports RDTSCP. */
718	uint32_t fVmxRdtscp : 1;
719	/** VMX: Supports virtualize-x2APIC mode. */
720	uint32_t fVmxVirtX2ApicMode : 1;
721	/** VMX: Supports VPID. */
722	uint32_t fVmxVpid : 1;
723	/** VMX: Supports WBIND exiting. */
724	uint32_t fVmxWbinvdExit : 1;
725	/** VMX: Supports Unrestricted guest. */
726	uint32_t fVmxUnrestrictedGuest : 1;
727	/** VMX: Supports APIC-register virtualization. */
728	uint32_t fVmxApicRegVirt : 1;
729	/** VMX: Supports virtual-interrupt delivery. */
730	uint32_t fVmxVirtIntDelivery : 1;
731	/** VMX: Supports Pause-loop exiting. */
732	uint32_t fVmxPauseLoopExit : 1;
733	/** VMX: Supports RDRAND exiting. */
734	uint32_t fVmxRdrandExit : 1;
735	/** VMX: Supports INVPCID. */
736	uint32_t fVmxInvpcid : 1;
737	/** VMX: Supports VM functions. */
738	uint32_t fVmxVmFunc : 1;
739	/** VMX: Supports VMCS shadowing. */
740	uint32_t fVmxVmcsShadowing : 1;
741	/** VMX: Supports RDSEED exiting. */
742	uint32_t fVmxRdseedExit : 1;
743	/** VMX: Supports PML. */
744	uint32_t fVmxPml : 1;
745	/** VMX: Supports EPT-violations \#VE. */
746	uint32_t fVmxEptXcptVe : 1;
747	/** VMX: Supports conceal VMX from PT. */
748	uint32_t fVmxConcealVmxFromPt : 1;
749	/** VMX: Supports XSAVES/XRSTORS. */
750	uint32_t fVmxXsavesXrstors : 1;
751	/** VMX: Supports PASID translation. */
752	uint32_t fVmxPasidTranslate : 1;
753	/** VMX: Supports mode-based execute control for EPT. */
754	uint32_t fVmxModeBasedExecuteEpt : 1;
755	/** VMX: Supports sub-page write permissions for EPT. */
756	uint32_t fVmxSppEpt : 1;
757	/** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
758	uint32_t fVmxPtEpt : 1;
759	/** VMX: Supports TSC scaling. */
760	uint32_t fVmxUseTscScaling : 1;
761	/** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
762	uint32_t fVmxUserWaitPause : 1;
763	/** VMX: Supports PCONFIG. */
764	uint32_t fVmxPconfig : 1;
765	/** VMX: Supports enclave (ENCLV) exiting. */
766	uint32_t fVmxEnclvExit : 1;
767	/** VMX: Supports VMM bus-lock detection. */
768	uint32_t fVmxBusLockDetect : 1;
769	/** VMX: Supports instruction timeout. */
770	uint32_t fVmxInstrTimeout : 1;
771	/** @} */
772
773	/** @name VMX Tertiary processor-based controls.
774	* @{ */
775	/** VMX: Supports LOADIWKEY exiting. */
776	uint32_t fVmxLoadIwKeyExit : 1;
777	/** VMX: Supports hypervisor-managed linear address translation (HLAT). */
778	uint32_t fVmxHlat : 1;
779	/** VMX: Supports EPT paging-write control. */
780	uint32_t fVmxEptPagingWrite : 1;
781	/** VMX: Supports Guest-paging verification. */
782	uint32_t fVmxGstPagingVerify : 1;
783	/** VMX: Supports IPI virtualization. */
784	uint32_t fVmxIpiVirt : 1;
785	/** VMX: Supports virtualize IA32_SPEC_CTRL. */
786	uint32_t fVmxVirtSpecCtrl : 1;
787	/** @} */
788
789	/** @name VMX VM-entry controls.
790	* @{ */
791	/** VMX: Supports load-debug controls on VM-entry. */
792	uint32_t fVmxEntryLoadDebugCtls : 1;
793	/** VMX: Supports IA32e mode guest. */
794	uint32_t fVmxIa32eModeGuest : 1;
795	/** VMX: Supports load guest EFER MSR on VM-entry. */
796	uint32_t fVmxEntryLoadEferMsr : 1;
797	/** VMX: Supports load guest PAT MSR on VM-entry. */
798	uint32_t fVmxEntryLoadPatMsr : 1;
799	/** @} */
800
801	/** @name VMX VM-exit controls.
802	* @{ */
803	/** VMX: Supports save debug controls on VM-exit. */
804	uint32_t fVmxExitSaveDebugCtls : 1;
805	/** VMX: Supports host-address space size. */
806	uint32_t fVmxHostAddrSpaceSize : 1;
807	/** VMX: Supports acknowledge external interrupt on VM-exit. */
808	uint32_t fVmxExitAckExtInt : 1;
809	/** VMX: Supports save guest PAT MSR on VM-exit. */
810	uint32_t fVmxExitSavePatMsr : 1;
811	/** VMX: Supports load hsot PAT MSR on VM-exit. */
812	uint32_t fVmxExitLoadPatMsr : 1;
813	/** VMX: Supports save guest EFER MSR on VM-exit. */
814	uint32_t fVmxExitSaveEferMsr : 1;
815	/** VMX: Supports load host EFER MSR on VM-exit. */
816	uint32_t fVmxExitLoadEferMsr : 1;
817	/** VMX: Supports save VMX preemption timer on VM-exit. */
818	uint32_t fVmxSavePreemptTimer : 1;
819	/** VMX: Supports secondary VM-exit controls. */
820	uint32_t fVmxSecondaryExitCtls : 1;
821	/** @} */
822
823	/** @name VMX Miscellaneous data.
824	* @{ */
825	/** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
826	uint32_t fVmxExitSaveEferLma : 1;
827	/** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
828	uint32_t fVmxPt : 1;
829	/** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
830	* VMWRITE cannot modify read-only VM-exit information fields. */
831	uint32_t fVmxVmwriteAll : 1;
832	/** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
833	* length instructions. */
834	uint32_t fVmxEntryInjectSoftInt : 1;
835	/** @} */
836
837	/** VMX: Padding / reserved for future features. */
838	uint32_t fVmxPadding0 : 7;
839	/** VMX: Padding / reserved for future, making it a total of 128 bits. */
840	uint32_t fVmxPadding1;
841	uint32_t auPadding[4];
842	} CPUMFEATURESX86;
843	#ifndef VBOX_FOR_DTRACE_LIB
844	AssertCompileSize(CPUMFEATURESX86, 64);
845	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESX86, enmCpuVendor);
846	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESX86, enmMicroarch);
847	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESX86, cMaxPhysAddrWidth);
848	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESX86, cMaxLinearAddrWidth);
849	#endif
850
851	/**
852	* CPU features and quirks for ARMv8.
853	*
854	* This is mostly exploded CPU feature register info.
855	*/
856	typedef struct CPUMFEATURESARMV8
857	{
858	/** The microarchitecture. */
859	#ifndef VBOX_FOR_DTRACE_LIB
860	CPUMMICROARCH enmMicroarch;
861	#else
862	uint32_t enmMicroarch;
863	#endif
864	/** The CPU vendor (CPUMCPUVENDOR). */
865	uint8_t enmCpuVendor;
866	/** The maximum physical address width of the CPU. */
867	uint8_t cMaxPhysAddrWidth;
868	/** The maximum linear address width of the CPU. */
869	uint8_t cMaxLinearAddrWidth;
870
871	/** The CPU implementer value (from MIDR_EL1). */
872	uint8_t uImplementeter;
873	/** The CPU part number (from MIDR_EL1). */
874	uint16_t uPartNum;
875	/** The CPU variant (from MIDR_EL1). */
876	uint8_t uVariant;
877	/** The CPU revision (from MIDR_EL1). */
878	uint8_t uRevision;
879
880	/** @name Granule sizes supported.
881	* @{ */
882	/** 4KiB translation granule size supported. */
883	uint32_t fTGran4K : 1;
884	/** 16KiB translation granule size supported. */
885	uint32_t fTGran16K : 1;
886	/** 64KiB translation granule size supported. */
887	uint32_t fTGran64K : 1;
888	/** @} */
889
890	/** @name pre-2020 Architecture Extensions.
891	* @{ */
892	/** Supports Advanced SIMD Extension (FEAT_AdvSIMD). */
893	uint32_t fAdvSimd : 1;
894	/** Supports Advanced SIMD AES instructions (FEAT_AES). */
895	uint32_t fAes : 1;
896	/** Supports Advanced SIMD PMULL instructions (FEAT_PMULL). */
897	uint32_t fPmull : 1;
898	/** Supports CP15Disable2 (FEAT_CP15DISABLE2). */
899	uint32_t fCp15Disable2 : 1;
900	/** Supports Cache Speculation Variant 2 (FEAT_CSV2). */
901	uint32_t fCsv2 : 1;
902	/** Supports Cache Speculation Variant 2, version 1.1 (FEAT_CSV2_1p1). */
903	uint32_t fCsv21p1 : 1;
904	/** Supports Cache Speculation Variant 2, version 1.2 (FEAT_CSV2_1p2). */
905	uint32_t fCsv21p2 : 1;
906	/** Supports Cache Speculation Variant 3 (FEAT_CSV3). */
907	uint32_t fCsv3 : 1;
908	/** Supports Data Gahtering Hint (FEAT_DGH). */
909	uint32_t fDgh : 1;
910	/** Supports Double Lock (FEAT_DoubleLock). */
911	uint32_t fDoubleLock : 1;
912	/** Supports Enhanced Translation Synchronization (FEAT_ETS2). */
913	uint32_t fEts2 : 1;
914	/** Supports Floating Point Extensions (FEAT_FP). */
915	uint32_t fFp : 1;
916	/** Supports IVIPT Extensions (FEAT_IVIPT). */
917	uint32_t fIvipt : 1;
918	/** Supports PC Sample-based Profiling Extension (FEAT_PCSRv8). */
919	uint32_t fPcsrV8 : 1;
920	/** Supports Speculation Restrictions instructions (FEAT_SPECRES). */
921	uint32_t fSpecres : 1;
922	/** Supports Reliability, Availability, and Serviceability (RAS) Extension (FEAT_RAS). */
923	uint32_t fRas : 1;
924	/** Supports Speculation Barrier (FEAT_SB). */
925	uint32_t fSb : 1;
926	/** Supports Advanced SIMD SHA1 instructions (FEAT_SHA1). */
927	uint32_t fSha1 : 1;
928	/** Supports Advanced SIMD SHA256 instructions (FEAT_SHA256). */
929	uint32_t fSha256 : 1;
930	/** Supports Speculation Store Bypass Safe (FEAT_SSBS). */
931	uint32_t fSsbs : 1;
932	/** Supports MRS and MSR instructions for Speculation Store Bypass Safe version 2 (FEAT_SSBS2). */
933	uint32_t fSsbs2 : 1;
934	/** Supports CRC32 instructions (FEAT_CRC32). */
935	uint32_t fCrc32 : 1;
936	/** Supports Intermediate chacing of trnslation table walks (FEAT_nTLBPA). */
937	uint32_t fNTlbpa : 1;
938	/** Supports debug with VHE (FEAT_Debugv8p1). */
939	uint32_t fDebugV8p1 : 1;
940	/** Supports Hierarchical permission disables in translation tables (FEAT_HPDS). */
941	uint32_t fHpds : 1;
942	/** Supports Limited ordering regions (FEAT_LOR). */
943	uint32_t fLor : 1;
944	/** Supports Lare Systems Extensons (FEAT_LSE). */
945	uint32_t fLse : 1;
946	/** Supports Privileged access never (FEAT_PAN). */
947	uint32_t fPan : 1;
948	/** Supports Armv8.1 PMU extensions (FEAT_PMUv3p1). */
949	uint32_t fPmuV3p1 : 1;
950	/** Supports Advanced SIMD rouding double multiply accumulate instructions (FEAT_RDM). */
951	uint32_t fRdm : 1;
952	/** Supports hardware management of the Access flag and dirty state (FEAT_HAFDBS). */
953	uint32_t fHafdbs : 1;
954	/** Supports Virtualization Host Extensions (FEAT_VHE). */
955	uint32_t fVhe : 1;
956	/** Supports 16-bit VMID (FEAT_VMID16). */
957	uint32_t fVmid16 : 1;
958	/** Supports AArch32 BFloat16 instructions (FEAT_AA32BF16). */
959	uint32_t fAa32Bf16 : 1;
960	/** Supports AArch32 Hierarchical permission disables (FEAT_AA32HPD). */
961	uint32_t fAa32Hpd : 1;
962	/** Supports AArch32 Int8 matrix multiplication instructions (FEAT_AA32I8MM). */
963	uint32_t fAa32I8mm : 1;
964	/** Supports AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN (FEAT_PAN2). */
965	uint32_t fPan2 : 1;
966	/** Supports AArch64 BFloat16 instructions (FEAT_BF16). */
967	uint32_t fBf16 : 1;
968	/** Supports DC CVADP instruction (FEAT_DPB2). */
969	uint32_t fDpb2 : 1;
970	/** Supports DC VAP instruction (FEAT_DPB). */
971	uint32_t fDpb : 1;
972	/** Supports Debug v8.2 (FEAT_Debugv8p2). */
973	uint32_t fDebugV8p2 : 1;
974	/** Supports Advanced SIMD dot product instructions (FEAT_DotProd). */
975	uint32_t fDotProd : 1;
976	/** Supports Enhanced Virtualization Traps (FEAT_EVT). */
977	uint32_t fEvt : 1;
978	/** Supports Single precision Matrix Multiplication (FEAT_F32MM). */
979	uint32_t fF32mm : 1;
980	/** Supports Double precision Matrix Multiplication (FEAT_F64MM). */
981	uint32_t fF64mm : 1;
982	/** Supports Floating-point half precision multiplication instructions (FEAT_FHM). */
983	uint32_t fFhm : 1;
984	/** Supports Half-precision floating point data processing (FEAT_FP16). */
985	uint32_t fFp16 : 1;
986	/** Supports AArch64 Int8 matrix multiplication instructions (FEAT_I8MM). */
987	uint32_t fI8mm : 1;
988	/** Supports Implicit Error Synchronization event (FEAT_IESB). */
989	uint32_t fIesb : 1;
990	/** Supports Large PA and IPA support (FEAT_LPA). */
991	uint32_t fLpa : 1;
992	/** Supports AArch32 Load/Store Multiple instructions atomicity and ordering controls (FEAT_LSMAOC). */
993	uint32_t fLsmaoc : 1;
994	/** Supports Large VA support (FEAT_LVA). */
995	uint32_t fLva : 1;
996	/** Supports Memory Partitioning and Monitoring Extension (FEAT_MPAM). */
997	uint32_t fMpam : 1;
998	/** Supports PC Sample-based Profiling Extension, version 8.2 (FEAT_PCSRv8p2). */
999	uint32_t fPcsrV8p2 : 1;
1000	/** Supports Advanced SIMD SHA3 instructions (FEAT_SHA3). */
1001	uint32_t fSha3 : 1;
1002	/** Supports Advanced SIMD SHA512 instructions (FEAT_SHA512). */
1003	uint32_t fSha512 : 1;
1004	/** Supports Advanced SIMD SM3 instructions (FEAT_SM3). */
1005	uint32_t fSm3 : 1;
1006	/** Supports Advanced SIMD SM4 instructions (FEAT_SM4). */
1007	uint32_t fSm4 : 1;
1008	/** Supports Statistical Profiling Extension (FEAT_SPE). */
1009	uint32_t fSpe : 1;
1010	/** Supports Scalable Vector Extension (FEAT_SVE). */
1011	uint32_t fSve : 1;
1012	/** Supports Translation Table Common not private translations (FEAT_TTCNP). */
1013	uint32_t fTtcnp : 1;
1014	/** Supports Hierarchical permission disables, version 2 (FEAT_HPDS2). */
1015	uint32_t fHpds2 : 1;
1016	/** Supports Translation table stage 2 Unprivileged Execute-never (FEAT_XNX). */
1017	uint32_t fXnx : 1;
1018	/** Supports Unprivileged Access Override control (FEAT_UAO). */
1019	uint32_t fUao : 1;
1020	/** Supports VMID-aware PIPT instruction cache (FEAT_VPIPT). */
1021	uint32_t fVpipt : 1;
1022	/** Supports Extended cache index (FEAT_CCIDX). */
1023	uint32_t fCcidx : 1;
1024	/** Supports Floating-point complex number instructions (FEAT_FCMA). */
1025	uint32_t fFcma : 1;
1026	/** Supports Debug over Powerdown (FEAT_DoPD). */
1027	uint32_t fDopd : 1;
1028	/** Supports Enhanced pointer authentication (FEAT_EPAC). */
1029	uint32_t fEpac : 1;
1030	/** Supports Faulting on AUT* instructions (FEAT_FPAC). */
1031	uint32_t fFpac : 1;
1032	/** Supports Faulting on combined pointer euthentication instructions (FEAT_FPACCOMBINE). */
1033	uint32_t fFpacCombine : 1;
1034	/** Supports JavaScript conversion instructions (FEAT_JSCVT). */
1035	uint32_t fJscvt : 1;
1036	/** Supports Load-Acquire RCpc instructions (FEAT_LRCPC). */
1037	uint32_t fLrcpc : 1;
1038	/** Supports Nexted Virtualization (FEAT_NV). */
1039	uint32_t fNv : 1;
1040	/** Supports QARMA5 pointer authentication algorithm (FEAT_PACQARMA5). */
1041	uint32_t fPacQarma5 : 1;
1042	/** Supports implementation defined pointer authentication algorithm (FEAT_PACIMP). */
1043	uint32_t fPacImp : 1;
1044	/** Supports Pointer authentication (FEAT_PAuth). */
1045	uint32_t fPAuth : 1;
1046	/** Supports Enhancements to pointer authentication (FEAT_PAuth2). */
1047	uint32_t fPAuth2 : 1;
1048	/** Supports Statistical Profiling Extensions version 1.1 (FEAT_SPEv1p1). */
1049	uint32_t fSpeV1p1 : 1;
1050	/** Supports Activity Monitor Extension, version 1 (FEAT_AMUv1). */
1051	uint32_t fAmuV1 : 1;
1052	/** Supports Generic Counter Scaling (FEAT_CNTSC). */
1053	uint32_t fCntsc : 1;
1054	/** Supports Debug v8.4 (FEAT_Debugv8p4). */
1055	uint32_t fDebugV8p4 : 1;
1056	/** Supports Double Fault Extension (FEAT_DoubleFault). */
1057	uint32_t fDoubleFault : 1;
1058	/** Supports Data Independent Timing instructions (FEAT_DIT). */
1059	uint32_t fDit : 1;
1060	/** Supports Condition flag manipulation isntructions (FEAT_FlagM). */
1061	uint32_t fFlagM : 1;
1062	/** Supports ID space trap handling (FEAT_IDST). */
1063	uint32_t fIdst : 1;
1064	/** Supports Load-Acquire RCpc instructions version 2 (FEAT_LRCPC2). */
1065	uint32_t fLrcpc2 : 1;
1066	/** Supports Large Sytem Extensions version 2 (FEAT_LSE2). */
1067	uint32_t fLse2 : 1;
1068	/** Supports Enhanced nested virtualization support (FEAT_NV2). */
1069	uint32_t fNv2 : 1;
1070	/** Supports Armv8.4 PMU Extensions (FEAT_PMUv3p4). */
1071	uint32_t fPmuV3p4 : 1;
1072	/** Supports RAS Extension v1.1 (FEAT_RASv1p1). */
1073	uint32_t fRasV1p1 : 1;
1074	/** Supports RAS Extension v1.1 System Architecture (FEAT_RASSAv1p1). */
1075	uint32_t fRassaV1p1 : 1;
1076	/** Supports Stage 2 forced Write-Back (FEAT_S2FWB). */
1077	uint32_t fS2Fwb : 1;
1078	/** Supports Secure El2 (FEAT_SEL2). */
1079	uint32_t fSecEl2 : 1;
1080	/** Supports TLB invalidate instructions on Outer Shareable domain (FEAT_TLBIOS). */
1081	uint32_t fTlbios : 1;
1082	/** Supports TLB invalidate range instructions (FEAT_TLBIRANGE). */
1083	uint32_t fTlbirange : 1;
1084	/** Supports Self-hosted Trace Extensions (FEAT_TRF). */
1085	uint32_t fTrf : 1;
1086	/** Supports Translation Table Level (FEAT_TTL). */
1087	uint32_t fTtl : 1;
1088	/** Supports Translation table break-before-make levels (FEAT_BBM). */
1089	uint32_t fBbm : 1;
1090	/** Supports Small translation tables (FEAT_TTST). */
1091	uint32_t fTtst : 1;
1092	/** Supports Branch Target Identification (FEAT_BTI). */
1093	uint32_t fBti : 1;
1094	/** Supports Enhancements to flag manipulation instructions (FEAT_FlagM2). */
1095	uint32_t fFlagM2 : 1;
1096	/** Supports Context synchronization and exception handling (FEAT_ExS). */
1097	uint32_t fExs : 1;
1098	/** Supports Preenting EL0 access to halves of address maps (FEAT_E0PD). */
1099	uint32_t fE0Pd : 1;
1100	/** Supports Floating-point to integer instructions (FEAT_FRINTTS). */
1101	uint32_t fFrintts : 1;
1102	/** Supports Guest translation granule size (FEAT_GTG). */
1103	uint32_t fGtg : 1;
1104	/** Supports Instruction-only Memory Tagging Extension (FEAT_MTE). */
1105	uint32_t fMte : 1;
1106	/** Supports memory Tagging Extension version 2 (FEAT_MTE2). */
1107	uint32_t fMte2 : 1;
1108	/** Supports Armv8.5 PMU Extensions (FEAT_PMUv3p5). */
1109	uint32_t fPmuV3p5 : 1;
1110	/** Supports Random number generator (FEAT_RNG). */
1111	uint32_t fRng : 1;
1112	/** Supports AMU Extensions version 1.1 (FEAT_AMUv1p1). */
1113	uint32_t fAmuV1p1 : 1;
1114	/** Supports Enhanced Counter Virtualization (FEAT_ECV). */
1115	uint32_t fEcv : 1;
1116	/** Supports Fine Grain Traps (FEAT_FGT). */
1117	uint32_t fFgt : 1;
1118	/** Supports Memory Partitioning and Monitoring version 0.1 (FEAT_MPAMv0p1). */
1119	uint32_t fMpamV0p1 : 1;
1120	/** Supports Memory Partitioning and Monitoring version 1.1 (FEAT_MPAMv1p1). */
1121	uint32_t fMpamV1p1 : 1;
1122	/** Supports Multi-threaded PMU Extensions (FEAT_MTPMU). */
1123	uint32_t fMtPmu : 1;
1124	/** Supports Delayed Trapping of WFE (FEAT_TWED). */
1125	uint32_t fTwed : 1;
1126	/** Supports Embbedded Trace Macrocell version 4 (FEAT_ETMv4). */
1127	uint32_t fEtmV4 : 1;
1128	/** Supports Embbedded Trace Macrocell version 4.1 (FEAT_ETMv4p1). */
1129	uint32_t fEtmV4p1 : 1;
1130	/** Supports Embbedded Trace Macrocell version 4.2 (FEAT_ETMv4p2). */
1131	uint32_t fEtmV4p2 : 1;
1132	/** Supports Embbedded Trace Macrocell version 4.3 (FEAT_ETMv4p3). */
1133	uint32_t fEtmV4p3 : 1;
1134	/** Supports Embbedded Trace Macrocell version 4.4 (FEAT_ETMv4p4). */
1135	uint32_t fEtmV4p4 : 1;
1136	/** Supports Embbedded Trace Macrocell version 4.5 (FEAT_ETMv4p5). */
1137	uint32_t fEtmV4p5 : 1;
1138	/** Supports Embbedded Trace Macrocell version 4.6 (FEAT_ETMv4p6). */
1139	uint32_t fEtmV4p6 : 1;
1140	/** Supports Generic Interrupt Controller version 3 (FEAT_GICv3). */
1141	uint32_t fGicV3 : 1;
1142	/** Supports Generic Interrupt Controller version 3.1 (FEAT_GICv3p1). */
1143	uint32_t fGicV3p1 : 1;
1144	/** Supports Trapping Non-secure EL1 writes to ICV_DIR (FEAT_GICv3_TDIR). */
1145	uint32_t fGicV3Tdir : 1;
1146	/** Supports Generic Interrupt Controller version 4 (FEAT_GICv4). */
1147	uint32_t fGicV4 : 1;
1148	/** Supports Generic Interrupt Controller version 4.1 (FEAT_GICv4p1). */
1149	uint32_t fGicV4p1 : 1;
1150	/** Supports PMU extension, version 3 (FEAT_PMUv3). */
1151	uint32_t fPmuV3 : 1;
1152	/** Supports Embedded Trace Extension (FEAT_ETE). */
1153	uint32_t fEte : 1;
1154	/** Supports Embedded Trace Extension, version 1.1 (FEAT_ETEv1p1). */
1155	uint32_t fEteV1p1 : 1;
1156	/** Supports Embedded Trace Extension, version 1.2 (FEAT_ETEv1p2). */
1157	uint32_t fEteV1p2 : 1;
1158	/** Supports Scalable Vector Extension version 2 (FEAT_SVE2). */
1159	uint32_t fSve2 : 1;
1160	/** Supports Scalable Vector AES instructions (FEAT_SVE_AES). */
1161	uint32_t fSveAes : 1;
1162	/** Supports Scalable Vector PMULL instructions (FEAT_SVE_PMULL128). */
1163	uint32_t fSvePmull128 : 1;
1164	/** Supports Scalable Vector Bit Permutes instructions (FEAT_SVE_BitPerm). */
1165	uint32_t fSveBitPerm : 1;
1166	/** Supports Scalable Vector SHA3 instructions (FEAT_SVE_SHA3). */
1167	uint32_t fSveSha3 : 1;
1168	/** Supports Scalable Vector SM4 instructions (FEAT_SVE_SM4). */
1169	uint32_t fSveSm4 : 1;
1170	/** Supports Transactional Memory Extension (FEAT_TME). */
1171	uint32_t fTme : 1;
1172	/** Supports Trace Buffer Extension (FEAT_TRBE). */
1173	uint32_t fTrbe : 1;
1174	/** Supports Scalable Matrix Extension (FEAT_SME). */
1175	uint32_t fSme : 1;
1176	/** @} */
1177
1178	/** @name 2020 Architecture Extensions.
1179	* @{ */
1180	/** Supports Alternate floating-point behavior (FEAT_AFP). */
1181	uint32_t fAfp : 1;
1182	/** Supports HCRX_EL2 register (FEAT_HCX). */
1183	uint32_t fHcx : 1;
1184	/** Supports Larger phsical address for 4KiB and 16KiB translation granules (FEAT_LPA2). */
1185	uint32_t fLpa2 : 1;
1186	/** Supports 64 byte loads and stores without return (FEAT_LS64). */
1187	uint32_t fLs64 : 1;
1188	/** Supports 64 byte stores with return (FEAT_LS64_V). */
1189	uint32_t fLs64V : 1;
1190	/** Supports 64 byte EL0 stores with return (FEAT_LS64_ACCDATA). */
1191	uint32_t fLs64Accdata : 1;
1192	/** Supports MTE Asymmetric Fault Handling (FEAT_MTE3). */
1193	uint32_t fMte3 : 1;
1194	/** Supports SCTLR_ELx.EPAN (FEAT_PAN3). */
1195	uint32_t fPan3 : 1;
1196	/** Supports Armv8.7 PMU extensions (FEAT_PMUv3p7). */
1197	uint32_t fPmuV3p7 : 1;
1198	/** Supports Increased precision of Reciprocal Extimate and Reciprocal Square Root Estimate (FEAT_RPRES). */
1199	uint32_t fRpres : 1;
1200	/** Supports Realm Management Extension (FEAT_RME). */
1201	uint32_t fRme : 1;
1202	/** Supports Full A64 instruction set support in Streaming SVE mode (FEAT_SME_FA64). */
1203	uint32_t fSmeFA64 : 1;
1204	/** Supports Double-precision floating-point outer product instructions (FEAT_SME_F64F64). */
1205	uint32_t fSmeF64F64 : 1;
1206	/** Supports 16-bit to 64-bit integer widening outer product instructions (FEAT_SME_I16I64). */
1207	uint32_t fSmeI16I64 : 1;
1208	/** Supports Statistical Profiling Extensions version 1.2 (FEAT_SPEv1p2). */
1209	uint32_t fSpeV1p2 : 1;
1210	/** Supports AArch64 Extended BFloat16 instructions (FEAT_EBF16). */
1211	uint32_t fEbf16 : 1;
1212	/** Supports WFE and WFI instructions with timeout (FEAT_WFxT). */
1213	uint32_t fWfxt : 1;
1214	/** Supports XS attribute (FEAT_XS). */
1215	uint32_t fXs : 1;
1216	/** Supports branch Record Buffer Extension (FEAT_BRBE). */
1217	uint32_t fBrbe : 1;
1218	/** @} */
1219
1220	/** @name 2021 Architecture Extensions.
1221	* @{ */
1222	/** Supports Control for cache maintenance permission (FEAT_CMOW). */
1223	uint32_t fCmow : 1;
1224	/** Supports PAC algorithm enhancement (FEAT_CONSTPACFIELD). */
1225	uint32_t fConstPacField : 1;
1226	/** Supports Debug v8.8 (FEAT_Debugv8p8). */
1227	uint32_t fDebugV8p8 : 1;
1228	/** Supports Hinted conditional branches (FEAT_HBC). */
1229	uint32_t fHbc : 1;
1230	/** Supports Setting of MDCR_EL2.HPMN to zero (FEAT_HPMN0). */
1231	uint32_t fHpmn0 : 1;
1232	/** Supports Non-Maskable Interrupts (FEAT_NMI). */
1233	uint32_t fNmi : 1;
1234	/** Supports GIC Non-Maskable Interrupts (FEAT_GICv3_NMI). */
1235	uint32_t fGicV3Nmi : 1;
1236	/** Supports Standardization of memory operations (FEAT_MOPS). */
1237	uint32_t fMops : 1;
1238	/** Supports Pointer authentication - QARMA3 algorithm (FEAT_PACQARMA3). */
1239	uint32_t fPacQarma3 : 1;
1240	/** Supports Event counting threshold (FEAT_PMUv3_TH). */
1241	uint32_t fPmuV3Th : 1;
1242	/** Supports Armv8.8 PMU extensions (FEAT_PMUv3p8). */
1243	uint32_t fPmuV3p8 : 1;
1244	/** Supports 64-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT64). */
1245	uint32_t fPmuV3Ext64 : 1;
1246	/** Supports 32-bit external interface to the Performance Monitors (FEAT_PMUv3_EXT32). */
1247	uint32_t fPmuV3Ext32 : 1;
1248	/** Supports External interface to the Performance Monitors (FEAT_PMUv3_EXT). */
1249	uint32_t fPmuV3Ext : 1;
1250	/** Supports Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP). */
1251	uint32_t fRngTrap : 1;
1252	/** Supports Statistical Profiling Extension version 1.3 (FEAT_SPEv1p3). */
1253	uint32_t fSpeV1p3 : 1;
1254	/** Supports EL0 use of IMPLEMENTATION DEFINEd functionality (FEAT_TIDCP1). */
1255	uint32_t fTidcp1 : 1;
1256	/** Supports Branch Record Buffer Extension version 1.1 (FEAT_BRBEv1p1). */
1257	uint32_t fBrbeV1p1 : 1;
1258	/** @} */
1259
1260	/** @name 2022 Architecture Extensions.
1261	* @{ */
1262	/** Supports Address Breakpoint Linking Extenions (FEAT_ABLE). */
1263	uint32_t fAble : 1;
1264	/** Supports Asynchronous Device error exceptions (FEAT_ADERR). */
1265	uint32_t fAderr : 1;
1266	/** Supports Memory Attribute Index Enhancement (FEAT_AIE). */
1267	uint32_t fAie : 1;
1268	/** Supports Asynchronous Normal error exception (FEAT_ANERR). */
1269	uint32_t fAnerr : 1;
1270	/** Supports Breakpoint Mismatch and Range Extension (FEAT_BWE). */
1271	uint32_t fBwe : 1;
1272	/** Supports Clear Branch History instruction (FEAT_CLRBHB). */
1273	uint32_t fClrBhb : 1;
1274	/** Supports Check Feature Status (FEAT_CHK). */
1275	uint32_t fChk : 1;
1276	/** Supports Common Short Sequence Compression instructions (FEAT_CSSC). */
1277	uint32_t fCssc : 1;
1278	/** Supports Cache Speculation Variant 2 version 3 (FEAT_CSV2_3). */
1279	uint32_t fCsv2v3 : 1;
1280	/** Supports 128-bit Translation Tables, 56 bit PA (FEAT_D128). */
1281	uint32_t fD128 : 1;
1282	/** Supports Debug v8.9 (FEAT_Debugv8p9). */
1283	uint32_t fDebugV8p9 : 1;
1284	/** Supports Enhancements to the Double Fault Extension (FEAT_DoubleFault2). */
1285	uint32_t fDoubleFault2 : 1;
1286	/** Supports Exception based Event Profiling (FEAT_EBEP). */
1287	uint32_t fEbep : 1;
1288	/** Supports Exploitative control using branch history information (FEAT_ECBHB). */
1289	uint32_t fEcBhb : 1;
1290	/** Supports for EDHSR (FEAT_EDHSR). */
1291	uint32_t fEdhsr : 1;
1292	/** Supports Embedded Trace Extension version 1.3 (FEAT_ETEv1p3). */
1293	uint32_t fEteV1p3 : 1;
1294	/** Supports Fine-grained traps 2 (FEAT_FGT2). */
1295	uint32_t fFgt2 : 1;
1296	/** Supports Guarded Control Stack Extension (FEAT_GCS). */
1297	uint32_t fGcs : 1;
1298	/** Supports Hardware managed Access Flag for Table descriptors (FEAT_HAFT). */
1299	uint32_t fHaft : 1;
1300	/** Supports Instrumentation Extension (FEAT_ITE). */
1301	uint32_t fIte : 1;
1302	/** Supports Load-Acquire RCpc instructions version 3 (FEAT_LRCPC3). */
1303	uint32_t fLrcpc3 : 1;
1304	/** Supports 128-bit atomics (FEAT_LSE128). */
1305	uint32_t fLse128 : 1;
1306	/** Supports 56-bit VA (FEAT_LVA3). */
1307	uint32_t fLva3 : 1;
1308	/** Supports Memory Encryption Contexts (FEAT_MEC). */
1309	uint32_t fMec : 1;
1310	/** Supports Enhanced Memory Tagging Extension (FEAT_MTE4). */
1311	uint32_t fMte4 : 1;
1312	/** Supports Canoncial Tag checking for untagged memory (FEAT_MTE_CANONCIAL_TAGS). */
1313	uint32_t fMteCanonicalTags : 1;
1314	/** Supports FAR_ELx on a Tag Check Fault (FEAT_MTE_TAGGED_FAR). */
1315	uint32_t fMteTaggedFar : 1;
1316	/** Supports Store only Tag checking (FEAT_MTE_STORE_ONLY). */
1317	uint32_t fMteStoreOnly : 1;
1318	/** Supports Memory tagging with Address tagging disabled (FEAT_MTE_NO_ADDRESS_TAGS). */
1319	uint32_t fMteNoAddressTags : 1;
1320	/** Supports Memory tagging asymmetric faults (FEAT_MTE_ASYM_FAULT). */
1321	uint32_t fMteAsymFault : 1;
1322	/** Supports Memory Tagging asynchronous faulting (FEAT_MTE_ASYNC). */
1323	uint32_t fMteAsync : 1;
1324	/** Supports Allocation tag access permission (FEAT_MTE_PERM_S1). */
1325	uint32_t fMtePermS1 : 1;
1326	/** Supports Armv8.9 PC Sample-based Profiling Extension (FEAT_PCSRv8p9). */
1327	uint32_t fPcsrV8p9 : 1;
1328	/** Supports Permission model enhancements (FEAT_S1PIE). */
1329	uint32_t fS1Pie : 1;
1330	/** Supports Permission model enhancements (FEAT_S2PIE). */
1331	uint32_t fS2Pie : 1;
1332	/** Supports Permission model enhancements (FEAT_S1POE). */
1333	uint32_t fS1Poe : 1;
1334	/** Supports Permission model enhancements (FEAT_S2POE). */
1335	uint32_t fS2Poe : 1;
1336	/** Supports Physical Fault Address Registers (FEAT_PFAR). */
1337	uint32_t fPfar : 1;
1338	/** Supports Armv8.9 PMU extensions (FEAT_PMUv3p9). */
1339	uint32_t fPmuV3p9 : 1;
1340	/** Supports PMU event edge detection (FEAT_PMUv3_EDGE). */
1341	uint32_t fPmuV3Edge : 1;
1342	/** Supports Fixed-function instruction counter (FEAT_PMUv3_ICNTR). */
1343	uint32_t fPmuV3Icntr : 1;
1344	/** Supports PMU Snapshot Extension (FEAT_PMUv3_SS). */
1345	uint32_t fPmuV3Ss : 1;
1346	/** Supports SLC traget for PRFM instructions (FEAT_PRFMSLC). */
1347	uint32_t fPrfmSlc : 1;
1348	/** Supports RAS version 2 (FEAT_RASv2). */
1349	uint32_t fRasV2 : 1;
1350	/** Supports RAS version 2 System Architecture (FEAT_RASSAv2). */
1351	uint32_t fRasSaV2 : 1;
1352	/** Supports for Range Prefetch Memory instruction (FEAT_RPRFM). */
1353	uint32_t fRprfm : 1;
1354	/** Supports extensions to SCTLR_ELx (FEAT_SCTLR2). */
1355	uint32_t fSctlr2 : 1;
1356	/** Supports Synchronous Exception-based Event Profiling (FEAT_SEBEP). */
1357	uint32_t fSebep : 1;
1358	/** Supports non-widening half-precision FP16 to FP16 arithmetic for SME2.1 (FEAT_SME_F16F16). */
1359	uint32_t fSmeF16F16 : 1;
1360	/** Supports Scalable Matrix Extension version 2 (FEAT_SME2). */
1361	uint32_t fSme2 : 1;
1362	/** Supports Scalable Matrix Extension version 2.1 (FEAT_SME2p1). */
1363	uint32_t fSme2p1 : 1;
1364	/** Supports Enhanced speculation restriction instructions (FEAT_SPECRES2). */
1365	uint32_t fSpecres2 : 1;
1366	/** Supports System Performance Monitors Extension (FEAT_SPMU). */
1367	uint32_t fSpmu : 1;
1368	/** Supports Statistical profiling Extension version 1.4 (FEAT_SPEv1p4). */
1369	uint32_t fSpeV1p4 : 1;
1370	/** Supports Call Return Branch Records (FEAT_SPE_CRR). */
1371	uint32_t fSpeCrr : 1;
1372	/** Supports Data Source Filtering (FEAT_SPE_FDS). */
1373	uint32_t fSpeFds : 1;
1374	/** Supports Scalable Vector Extension version SVE2.1 (FEAT_SVE2p1). */
1375	uint32_t fSve2p1 : 1;
1376	/** Supports Non-widening BFloat16 to BFloat16 arithmetic for SVE (FEAT_SVE_B16B16). */
1377	uint32_t fSveB16B16 : 1;
1378	/** Supports 128-bit System instructions (FEAT_SYSINSTR128). */
1379	uint32_t fSysInstr128 : 1;
1380	/** Supports 128-bit System registers (FEAT_SYSREG128). */
1381	uint32_t fSysReg128 : 1;
1382	/** Supports Extension to TCR_ELx (FEAT_TCR2). */
1383	uint32_t fTcr2 : 1;
1384	/** Supports Translation Hardening Extension (FEAT_THE). */
1385	uint32_t fThe : 1;
1386	/** Supports Trace Buffer external mode (FEAT_TRBE_EXT). */
1387	uint32_t fTrbeExt : 1;
1388	/** Supports Trace Buffer MPAM extension (FEAT_TRBE_MPAM). */
1389	uint32_t fTrbeMpam : 1;
1390	/** @} */
1391
1392	/** Padding to the required size to match CPUMFEATURESX86. */
1393	uint32_t auPadding[5];
1394	} CPUMFEATURESARMV8;
1395	#ifndef VBOX_FOR_DTRACE_LIB
1396	AssertCompileSize(CPUMFEATURESARMV8, 64);
1397	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch, CPUMFEATURESARMV8, enmMicroarch);
1398	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor, CPUMFEATURESARMV8, enmCpuVendor);
1399	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth, CPUMFEATURESARMV8, cMaxPhysAddrWidth);
1400	AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth, CPUMFEATURESARMV8, cMaxLinearAddrWidth);
1401	#endif
1402
1403
1404	/**
1405	* Chameleon wrapper structure for the host CPU features.
1406	*
1407	* This is used for the globally readable g_CpumHostFeatures variable, which is
1408	* initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1409	* ring-3. To reflect this immutability after load/init, we use this wrapper
1410	* structure to switch it between const and non-const depending on the context.
1411	* Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1412	*/
1413	typedef union CPUHOSTFEATURES
1414	{
1415	/** Fields common to all CPU types. */
1416	CPUMFEATURESCOMMON Common;
1417	/** The host specific structure. */
1418	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1419	CPUMFEATURESX86
1420	#elif defined(RT_ARCH_ARM64)
1421	CPUMFEATURESARMV8
1422	#else
1423	# error "port me"
1424	#endif
1425	#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1426	const
1427	#endif
1428	s;
1429	} CPUHOSTFEATURES;
1430	#ifndef VBOX_FOR_DTRACE_LIB
1431	AssertCompileSize(CPUHOSTFEATURES, 64);
1432	#endif
1433	/** Pointer to a const host CPU feature structure. */
1434	typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1435
1436	/** Host CPU features.
1437	* @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1438	* module init. */
1439	extern CPUHOSTFEATURES g_CpumHostFeatures;
1440
1441
1442	/** The target CPU feature structure.
1443	* @todo this should have a chameleon wrapper as well (ring-0). */
1444	#ifndef VBOX_VMM_TARGET_ARMV8
1445	typedef CPUMFEATURESX86 CPUMFEATURES;
1446	#else
1447	typedef CPUMFEATURESARMV8 CPUMFEATURES;
1448	#endif
1449	/** Pointer to a CPU feature structure. */
1450	typedef CPUMFEATURES *PCPUMFEATURES;
1451	/** Pointer to a const CPU feature structure. */
1452	typedef CPUMFEATURES const *PCCPUMFEATURES;
1453
1454
1455
1456	/**
1457	* ARMv8 CPU ID registers.
1458	*/
1459	typedef struct CPUMARMV8IDREGS
1460	{
1461	/** Content of the ID_AA64PFR0_EL1 register. */
1462	uint64_t u64RegIdAa64Pfr0El1;
1463	/** Content of the ID_AA64PFR1_EL1 register. */
1464	uint64_t u64RegIdAa64Pfr1El1;
1465	/** Content of the ID_AA64DFR0_EL1 register. */
1466	uint64_t u64RegIdAa64Dfr0El1;
1467	/** Content of the ID_AA64DFR1_EL1 register. */
1468	uint64_t u64RegIdAa64Dfr1El1;
1469	/** Content of the ID_AA64AFR0_EL1 register. */
1470	uint64_t u64RegIdAa64Afr0El1;
1471	/** Content of the ID_AA64AFR1_EL1 register. */
1472	uint64_t u64RegIdAa64Afr1El1;
1473	/** Content of the ID_AA64ISAR0_EL1 register. */
1474	uint64_t u64RegIdAa64Isar0El1;
1475	/** Content of the ID_AA64ISAR1_EL1 register. */
1476	uint64_t u64RegIdAa64Isar1El1;
1477	/** Content of the ID_AA64ISAR2_EL1 register. */
1478	uint64_t u64RegIdAa64Isar2El1;
1479	/** Content of the ID_AA64MMFR0_EL1 register. */
1480	uint64_t u64RegIdAa64Mmfr0El1;
1481	/** Content of the ID_AA64MMFR1_EL1 register. */
1482	uint64_t u64RegIdAa64Mmfr1El1;
1483	/** Content of the ID_AA64MMFR2_EL1 register. */
1484	uint64_t u64RegIdAa64Mmfr2El1;
1485	/** Content of the CLIDR_EL1 register. */
1486	uint64_t u64RegClidrEl1;
1487	/** Content of the CTR_EL0 register. */
1488	uint64_t u64RegCtrEl0;
1489	/** Content of the DCZID_EL0 register. */
1490	uint64_t u64RegDczidEl0;
1491	/** @todo we need MIDR_EL1 here, possibly also MPIDR_EL1 and REVIDR_EL1. */
1492	} CPUMARMV8IDREGS;
1493	/** Pointer to CPU ID registers. */
1494	typedef CPUMARMV8IDREGS *PCPUMARMV8IDREGS;
1495	/** Pointer to a const CPU ID registers structure. */
1496	typedef CPUMARMV8IDREGS const *PCCPUMARMV8IDREGS;
1497
1498
1499	/*
1500	* Include the target specific header.
1501	* This uses several of the above types, so it must be postponed till here.
1502	*/
1503	#ifndef VBOX_VMM_TARGET_ARMV8
1504	# include <VBox/vmm/cpum-x86-amd64.h>
1505	#else
1506	# include <VBox/vmm/cpum-armv8.h>
1507	#endif
1508
1509
1510
1511	RT_C_DECLS_BEGIN
1512
1513	#ifndef VBOX_FOR_DTRACE_LIB
1514
1515	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1516	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1517	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1518	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1519	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1520
1521	/** @name Guest Register Getters.
1522	* @{ */
1523	VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1524	VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1525	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1526	VMMDECL(CPUMARCH) CPUMGetGuestArch(PCVM pVM);
1527	VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1528	VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t pcPhysAddrWidth, uint8_t pcLinearAddrWidth);
1529	/** @} */
1530
1531	/** @name Misc Guest Predicate Functions.
1532	* @{ */
1533	VMMDECL(bool) CPUMIsGuestIn64BitCode(PCVMCPU pVCpu);
1534	/** @} */
1535
1536	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1537	VMMDECL(CPUMARCH) CPUMGetHostArch(PCVM pVM);
1538	VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1539
1540	VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
1541	VMMDECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
1542
1543	VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1544	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1545	VMMDECL(int) CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1546	#endif
1547	#if defined(RT_ARCH_ARM64)
1548	VMMDECL(int) CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs);
1549	#endif
1550
1551	#ifdef IN_RING3
1552	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1553	* @{
1554	*/
1555
1556	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1557	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1558	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
1559	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1560	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1561	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1562	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1563	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1564
1565	VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
1566	/** Pointer to CPUMR3DbGetEntries. */
1567	typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
1568	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
1569	/** Pointer to CPUMR3DbGetEntryByIndex. */
1570	typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
1571	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
1572	/** Pointer to CPUMR3DbGetEntryByName. */
1573	typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
1574
1575	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
1576	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
1577	/** @} */
1578	#endif /* IN_RING3 */
1579
1580	#endif /* !VBOX_FOR_DTRACE_LIB */
1581	/** @} */
1582	RT_C_DECLS_END
1583
1584
1585	#endif /* !VBOX_INCLUDED_vmm_cpum_h */
1586

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 107650

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