VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 42407

Last change on this file since 42407 was 42407, checked in by vboxsync, 12 years ago

VMM: Futher work on dealing with hidden segment register, esp. when going stale.
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File size: 21.2 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpum_h
27#define ___VBox_vmm_cpum_h
28
29#include <iprt/x86.h>
30#include <VBox/types.h>
31#include <VBox/vmm/cpumctx.h>
32
33RT_C_DECLS_BEGIN
34
35/** @defgroup grp_cpum The CPU Monitor / Manager API
36 * @{
37 */
38
39/**
40 * CPUID feature to set or clear.
41 */
42typedef enum CPUMCPUIDFEATURE
43{
44 CPUMCPUIDFEATURE_INVALID = 0,
45 /** The APIC feature bit. (Std+Ext) */
46 CPUMCPUIDFEATURE_APIC,
47 /** The sysenter/sysexit feature bit. (Std) */
48 CPUMCPUIDFEATURE_SEP,
49 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
50 CPUMCPUIDFEATURE_SYSCALL,
51 /** The PAE feature bit. (Std+Ext) */
52 CPUMCPUIDFEATURE_PAE,
53 /** The NX feature bit. (Ext) */
54 CPUMCPUIDFEATURE_NX,
55 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
56 CPUMCPUIDFEATURE_LAHF,
57 /** The LONG MODE feature bit. (Ext) */
58 CPUMCPUIDFEATURE_LONG_MODE,
59 /** The PAT feature bit. (Std+Ext) */
60 CPUMCPUIDFEATURE_PAT,
61 /** The x2APIC feature bit. (Std) */
62 CPUMCPUIDFEATURE_X2APIC,
63 /** The RDTSCP feature bit. (Ext) */
64 CPUMCPUIDFEATURE_RDTSCP,
65 /** The Hypervisor Present bit. (Std) */
66 CPUMCPUIDFEATURE_HVP,
67 /** 32bit hackishness. */
68 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
69} CPUMCPUIDFEATURE;
70
71/**
72 * CPU Vendor.
73 */
74typedef enum CPUMCPUVENDOR
75{
76 CPUMCPUVENDOR_INVALID = 0,
77 CPUMCPUVENDOR_INTEL,
78 CPUMCPUVENDOR_AMD,
79 CPUMCPUVENDOR_VIA,
80 CPUMCPUVENDOR_UNKNOWN,
81 CPUMCPUVENDOR_SYNTHETIC,
82 /** 32bit hackishness. */
83 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
84} CPUMCPUVENDOR;
85
86
87/** @name Guest Register Getters.
88 * @{ */
89VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
90VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
91VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
92VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
93VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
94VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
95VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
96VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
97VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
98VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
99VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
100VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
101VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
102VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
103VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
104VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
105VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
106VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
107VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
108VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
109VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
110VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
111VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
112VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
113VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
114VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
115VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
116VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
117VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
118VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
119VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
120VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
121VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
122VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
123VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
124VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
125VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
126VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
127VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
128VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
129VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
130VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
131VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
132/** @} */
133
134/** @name Guest Register Setters.
135 * @{ */
136VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
137VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
138VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
139VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
140VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
141VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
142VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
143VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
144VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
145VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
146VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
147VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
148VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
149VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
150VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
151VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
152VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
153VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
154VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
155VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
156VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
157VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
158VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
159VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
160VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
161VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
162VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
163VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
164VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
165VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
166VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
167VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
168VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
169VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
170VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
171VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
172VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
173VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
174/** @} */
175
176
177/** @name Misc Guest Predicate Functions.
178 * @{ */
179
180VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
181VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
182VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
183VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
184VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
185VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
186VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
187VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
188VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
189VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
190VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
191VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
192VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
193VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
194
195#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
196
197/**
198 * Tests if the guest is running in real mode or not.
199 *
200 * @returns true if in real mode, otherwise false.
201 * @param pCtx Current CPU context
202 */
203DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
204{
205 return !(pCtx->cr0 & X86_CR0_PE);
206}
207
208/**
209 * Tests if the guest is running in real or virtual 8086 mode.
210 *
211 * @returns @c true if it is, @c false if not.
212 * @param pCtx Current CPU context
213 */
214DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
215{
216 return !(pCtx->cr0 & X86_CR0_PE)
217 || pCtx->eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
218}
219
220/**
221 * Tests if the guest is running in paged protected or not.
222 *
223 * @returns true if in paged protected mode, otherwise false.
224 * @param pVM The VM handle.
225 */
226DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
227{
228 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
229}
230
231/**
232 * Tests if the guest is running in long mode or not.
233 *
234 * @returns true if in long mode, otherwise false.
235 * @param pCtx Current CPU context
236 */
237DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
238{
239 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
240}
241
242VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
243
244/**
245 * Tests if the guest is running in 64 bits mode or not.
246 *
247 * @returns true if in 64 bits protected mode, otherwise false.
248 * @param pVCpu The current virtual CPU.
249 * @param pCtx Current CPU context
250 */
251DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
252{
253 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
254 return false;
255 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
256 return CPUMIsGuestIn64BitCodeSlow(pCtx);
257 return pCtx->cs.Attr.n.u1Long;
258}
259
260/**
261 * Tests if the guest is running in PAE mode or not.
262 *
263 * @returns true if in PAE mode, otherwise false.
264 * @param pCtx Current CPU context
265 */
266DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
267{
268 return ( (pCtx->cr4 & X86_CR4_PAE)
269 && CPUMIsGuestInPagedProtectedModeEx(pCtx)
270 && !CPUMIsGuestInLongModeEx(pCtx));
271}
272
273#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
274
275/** @} */
276
277
278/** @name Hypervisor Register Getters.
279 * @{ */
280VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
281VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
282VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
283VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
284VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
285VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
286#if 0 /* these are not correct. */
287VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
288VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
289VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
290VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
291#endif
292/** This register is only saved on fatal traps. */
293VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
294VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
295/** This register is only saved on fatal traps. */
296VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
297/** This register is only saved on fatal traps. */
298VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
299VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
300VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
301VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
302VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
303VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
304VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
305VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
306VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
307VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
308VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
309VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
310VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
311VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
312VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
313VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
314VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
315VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
316VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
317/** @} */
318
319/** @name Hypervisor Register Setters.
320 * @{ */
321VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
322VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
323VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
324VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
325VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
326VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
327VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
328VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
329VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
330VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
331VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
332VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
333VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
334VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
335VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
336VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
337VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
338VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
339VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
340VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
341VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
342VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
343VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu);
344/** @} */
345
346VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
347VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
348VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
349VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
350VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
351VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
352VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
353VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
354VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
355VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
356VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
357
358/** @name Changed flags
359 * These flags are used to keep track of which important register that
360 * have been changed since last they were reset. The only one allowed
361 * to clear them is REM!
362 * @{
363 */
364#define CPUM_CHANGED_FPU_REM RT_BIT(0)
365#define CPUM_CHANGED_CR0 RT_BIT(1)
366#define CPUM_CHANGED_CR4 RT_BIT(2)
367#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
368#define CPUM_CHANGED_CR3 RT_BIT(4)
369#define CPUM_CHANGED_GDTR RT_BIT(5)
370#define CPUM_CHANGED_IDTR RT_BIT(6)
371#define CPUM_CHANGED_LDTR RT_BIT(7)
372#define CPUM_CHANGED_TR RT_BIT(8)
373#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
374#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
375#define CPUM_CHANGED_CPUID RT_BIT(11)
376/** All except CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
377#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
378 | CPUM_CHANGED_CR0 \
379 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
380 | CPUM_CHANGED_CR3 \
381 | CPUM_CHANGED_CR4 \
382 | CPUM_CHANGED_GDTR \
383 | CPUM_CHANGED_IDTR \
384 | CPUM_CHANGED_LDTR \
385 | CPUM_CHANGED_TR \
386 | CPUM_CHANGED_SYSENTER_MSR \
387 | CPUM_CHANGED_HIDDEN_SEL_REGS \
388 | CPUM_CHANGED_CPUID )
389/** This one is used by raw-mode to indicate that the hidden register
390 * information is not longer reliable and have to be re-determined.
391 *
392 * @remarks This must not be part of CPUM_CHANGED_ALL! */
393#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
394/** @} */
395
396VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
397VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
398VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
399VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
400VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
401VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
402VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
403VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
404VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
405VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
406VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
407VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu);
408VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
409VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu);
410VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
411VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
412VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
413
414
415#ifdef IN_RING3
416/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
417 * @ingroup grp_cpum
418 * @{
419 */
420
421VMMR3DECL(int) CPUMR3Init(PVM pVM);
422VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
423VMMR3DECL(int) CPUMR3Term(PVM pVM);
424VMMR3DECL(void) CPUMR3Reset(PVM pVM);
425VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu);
426VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
427VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
428VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
429VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
430VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
431VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
432VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
433
434/** @} */
435#endif /* IN_RING3 */
436
437#ifdef IN_RC
438/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
439 * @ingroup grp_cpum
440 * @{
441 */
442
443/**
444 * Calls a guest trap/interrupt handler directly
445 *
446 * Assumes a trap stack frame has already been setup on the guest's stack!
447 * This function does not return!
448 *
449 * @param pRegFrame Original trap/interrupt context
450 * @param selCS Code selector of handler
451 * @param pHandler GC virtual address of handler
452 * @param eflags Callee's EFLAGS
453 * @param selSS Stack selector for handler
454 * @param pEsp Stack address for handler
455 */
456DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
457 uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
458
459/**
460 * Call guest V86 code directly.
461 *
462 * This function does not return!
463 *
464 * @param pRegFrame Original trap/interrupt context
465 */
466DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
467
468/** @} */
469#endif /* IN_RC */
470
471#ifdef IN_RING0
472/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
473 * @ingroup grp_cpum
474 * @{
475 */
476VMMR0DECL(int) CPUMR0ModuleInit(void);
477VMMR0DECL(int) CPUMR0ModuleTerm(void);
478VMMR0DECL(int) CPUMR0Init(PVM pVM);
479VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
480VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
481VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
482VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
483VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu);
484VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
485VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
486#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
487VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu);
488#endif
489
490/** @} */
491#endif /* IN_RING0 */
492
493/** @} */
494RT_C_DECLS_END
495
496
497#endif
498
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