1 | /** @file
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2 | * CPUM - CPU Monitor(/ Manager).
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2012 Oracle Corporation
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | */
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25 |
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26 | #ifndef ___VBox_vmm_cpum_h
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27 | #define ___VBox_vmm_cpum_h
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28 |
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29 | #include <iprt/x86.h>
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30 | #include <VBox/types.h>
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31 | #include <VBox/vmm/cpumctx.h>
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32 |
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33 | RT_C_DECLS_BEGIN
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34 |
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35 | /** @defgroup grp_cpum The CPU Monitor / Manager API
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36 | * @{
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37 | */
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38 |
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39 | /**
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40 | * CPUID feature to set or clear.
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41 | */
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42 | typedef enum CPUMCPUIDFEATURE
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43 | {
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44 | CPUMCPUIDFEATURE_INVALID = 0,
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45 | /** The APIC feature bit. (Std+Ext) */
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46 | CPUMCPUIDFEATURE_APIC,
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47 | /** The sysenter/sysexit feature bit. (Std) */
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48 | CPUMCPUIDFEATURE_SEP,
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49 | /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
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50 | CPUMCPUIDFEATURE_SYSCALL,
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51 | /** The PAE feature bit. (Std+Ext) */
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52 | CPUMCPUIDFEATURE_PAE,
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53 | /** The NX feature bit. (Ext) */
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54 | CPUMCPUIDFEATURE_NX,
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55 | /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
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56 | CPUMCPUIDFEATURE_LAHF,
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57 | /** The LONG MODE feature bit. (Ext) */
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58 | CPUMCPUIDFEATURE_LONG_MODE,
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59 | /** The PAT feature bit. (Std+Ext) */
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60 | CPUMCPUIDFEATURE_PAT,
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61 | /** The x2APIC feature bit. (Std) */
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62 | CPUMCPUIDFEATURE_X2APIC,
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63 | /** The RDTSCP feature bit. (Ext) */
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64 | CPUMCPUIDFEATURE_RDTSCP,
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65 | /** The Hypervisor Present bit. (Std) */
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66 | CPUMCPUIDFEATURE_HVP,
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67 | /** 32bit hackishness. */
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68 | CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
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69 | } CPUMCPUIDFEATURE;
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70 |
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71 | /**
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72 | * CPU Vendor.
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73 | */
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74 | typedef enum CPUMCPUVENDOR
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75 | {
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76 | CPUMCPUVENDOR_INVALID = 0,
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77 | CPUMCPUVENDOR_INTEL,
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78 | CPUMCPUVENDOR_AMD,
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79 | CPUMCPUVENDOR_VIA,
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80 | CPUMCPUVENDOR_UNKNOWN,
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81 | CPUMCPUVENDOR_SYNTHETIC,
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82 | /** 32bit hackishness. */
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83 | CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
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84 | } CPUMCPUVENDOR;
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85 |
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86 |
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87 | /** @name Guest Register Getters.
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88 | * @{ */
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89 | VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
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90 | VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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91 | VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
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92 | VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
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93 | VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
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94 | VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
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95 | VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
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96 | VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
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97 | VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
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98 | VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
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99 | VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
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100 | VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
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101 | VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
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102 | VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
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103 | VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
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104 | VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
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105 | VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
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106 | VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
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107 | VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
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108 | VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
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109 | VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
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110 | VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
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111 | VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
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112 | VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
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113 | VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
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114 | VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
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115 | VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
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116 | VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
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117 | VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
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118 | VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
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119 | VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
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120 | VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
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121 | VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
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122 | VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
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123 | VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
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124 | VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
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125 | VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
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126 | VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
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127 | VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
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128 | VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
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129 | VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
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130 | VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
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131 | VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
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132 | VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
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133 | /** @} */
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134 |
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135 | /** @name Guest Register Setters.
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136 | * @{ */
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137 | VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
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138 | VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
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139 | VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
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140 | VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
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141 | VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
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142 | VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
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143 | VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
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144 | VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
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145 | VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
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146 | VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
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147 | VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
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148 | VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
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149 | VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
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150 | VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
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151 | VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
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152 | VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
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153 | VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
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154 | VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
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155 | VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
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156 | VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
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157 | VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
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158 | VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
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159 | VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
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160 | VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
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161 | VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
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162 | VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
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163 | VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
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164 | VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
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165 | VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
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166 | VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
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167 | VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
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168 | VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
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169 | VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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170 | VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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171 | VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
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172 | VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
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173 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
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174 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
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175 | /** @} */
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176 |
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177 |
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178 | /** @name Misc Guest Predicate Functions.
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179 | * @{ */
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180 |
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181 | VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
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182 | VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
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183 | VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
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184 | VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
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185 | VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
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186 | VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
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187 | VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
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188 | VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
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189 | VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
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190 | VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
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191 | VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
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192 | VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
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193 | VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
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194 | VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
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195 |
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196 | #ifndef VBOX_WITHOUT_UNNAMED_UNIONS
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197 |
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198 | /**
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199 | * Tests if the guest is running in real mode or not.
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200 | *
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201 | * @returns true if in real mode, otherwise false.
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202 | * @param pCtx Current CPU context
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203 | */
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204 | DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
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205 | {
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206 | return !(pCtx->cr0 & X86_CR0_PE);
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207 | }
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208 |
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209 | /**
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210 | * Tests if the guest is running in real or virtual 8086 mode.
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211 | *
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212 | * @returns @c true if it is, @c false if not.
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213 | * @param pCtx Current CPU context
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214 | */
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215 | DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
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216 | {
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217 | return !(pCtx->cr0 & X86_CR0_PE)
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218 | || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
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219 | }
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220 |
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221 | /**
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222 | * Tests if the guest is running in paged protected or not.
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223 | *
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224 | * @returns true if in paged protected mode, otherwise false.
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225 | * @param pVM The VM handle.
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226 | */
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227 | DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
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228 | {
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229 | return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
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230 | }
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231 |
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232 | /**
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233 | * Tests if the guest is running in long mode or not.
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234 | *
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235 | * @returns true if in long mode, otherwise false.
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236 | * @param pCtx Current CPU context
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237 | */
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238 | DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
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239 | {
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240 | return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
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241 | }
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242 |
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243 | VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
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244 |
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245 | /**
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246 | * Tests if the guest is running in 64 bits mode or not.
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247 | *
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248 | * @returns true if in 64 bits protected mode, otherwise false.
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249 | * @param pVCpu The current virtual CPU.
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250 | * @param pCtx Current CPU context
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251 | */
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252 | DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
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253 | {
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254 | if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
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255 | return false;
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256 | if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
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257 | return CPUMIsGuestIn64BitCodeSlow(pCtx);
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258 | return pCtx->cs.Attr.n.u1Long;
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259 | }
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260 |
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261 | /**
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262 | * Tests if the guest is running in PAE mode or not.
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263 | *
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264 | * @returns true if in PAE mode, otherwise false.
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265 | * @param pCtx Current CPU context
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266 | */
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267 | DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
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268 | {
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269 | return ( (pCtx->cr4 & X86_CR4_PAE)
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270 | && CPUMIsGuestInPagedProtectedModeEx(pCtx)
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271 | && !CPUMIsGuestInLongModeEx(pCtx));
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272 | }
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273 |
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274 | #endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
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275 |
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276 | /** @} */
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277 |
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278 |
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279 | /** @name Hypervisor Register Getters.
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280 | * @{ */
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281 | VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
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282 | VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
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283 | VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
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284 | VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
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285 | VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
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286 | VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
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287 | #if 0 /* these are not correct. */
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288 | VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
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289 | VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
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290 | VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
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291 | VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
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292 | #endif
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293 | /** This register is only saved on fatal traps. */
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294 | VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
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295 | VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
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296 | /** This register is only saved on fatal traps. */
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297 | VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
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298 | /** This register is only saved on fatal traps. */
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299 | VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
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300 | VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
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301 | VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
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302 | VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
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303 | VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
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304 | VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
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305 | VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
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306 | VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
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307 | VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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308 | VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
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309 | VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
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310 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
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311 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
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312 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
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313 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
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314 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
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315 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
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316 | VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
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317 | VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
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318 | /** @} */
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319 |
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320 | /** @name Hypervisor Register Setters.
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321 | * @{ */
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322 | VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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323 | VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
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324 | VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
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325 | VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
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326 | VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
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327 | VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
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328 | VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
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329 | VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
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330 | VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
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331 | VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
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332 | VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
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333 | VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
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334 | VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
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335 | VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
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336 | VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
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337 | VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
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338 | VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
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339 | VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
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340 | VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
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341 | VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
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342 | VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
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343 | VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
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344 | VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu);
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345 | /** @} */
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346 |
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347 | VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
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348 | VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
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349 | VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
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350 | VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
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351 | VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
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352 | VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
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353 | VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
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354 | VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
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355 | VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
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356 | VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
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357 | VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
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358 |
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359 | /** @name Changed flags.
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360 | * These flags are used to keep track of which important register that
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361 | * have been changed since last they were reset. The only one allowed
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362 | * to clear them is REM!
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363 | * @{
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364 | */
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365 | #define CPUM_CHANGED_FPU_REM RT_BIT(0)
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366 | #define CPUM_CHANGED_CR0 RT_BIT(1)
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367 | #define CPUM_CHANGED_CR4 RT_BIT(2)
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368 | #define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
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369 | #define CPUM_CHANGED_CR3 RT_BIT(4)
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370 | #define CPUM_CHANGED_GDTR RT_BIT(5)
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371 | #define CPUM_CHANGED_IDTR RT_BIT(6)
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372 | #define CPUM_CHANGED_LDTR RT_BIT(7)
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373 | #define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
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374 | #define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
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375 | #define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
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376 | #define CPUM_CHANGED_CPUID RT_BIT(11)
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377 | #define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
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378 | | CPUM_CHANGED_CR0 \
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379 | | CPUM_CHANGED_CR4 \
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380 | | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
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381 | | CPUM_CHANGED_CR3 \
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382 | | CPUM_CHANGED_GDTR \
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383 | | CPUM_CHANGED_IDTR \
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384 | | CPUM_CHANGED_LDTR \
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385 | | CPUM_CHANGED_TR \
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386 | | CPUM_CHANGED_SYSENTER_MSR \
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387 | | CPUM_CHANGED_HIDDEN_SEL_REGS \
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388 | | CPUM_CHANGED_CPUID )
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389 | /** @} */
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390 |
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391 | VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
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392 | VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
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393 | VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
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394 | VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
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395 | VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
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396 | VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
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397 | VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
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398 | VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
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399 | VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
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400 | VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
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401 | VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
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402 | VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu);
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403 | VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
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404 | VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
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405 | VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
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406 | VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
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407 |
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408 |
|
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409 | #ifdef IN_RING3
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410 | /** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
|
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411 | * @ingroup grp_cpum
|
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412 | * @{
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413 | */
|
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414 |
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415 | VMMR3DECL(int) CPUMR3Init(PVM pVM);
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416 | VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM);
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417 | VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
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418 | VMMR3DECL(int) CPUMR3Term(PVM pVM);
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419 | VMMR3DECL(void) CPUMR3Reset(PVM pVM);
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420 | VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu);
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421 | VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
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422 | VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
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423 | VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
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424 | VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
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425 | VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
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426 | VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
|
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427 | VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
|
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428 |
|
---|
429 | /** @} */
|
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430 | #endif /* IN_RING3 */
|
---|
431 |
|
---|
432 | #ifdef IN_RC
|
---|
433 | /** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
|
---|
434 | * @ingroup grp_cpum
|
---|
435 | * @{
|
---|
436 | */
|
---|
437 |
|
---|
438 | /**
|
---|
439 | * Calls a guest trap/interrupt handler directly
|
---|
440 | *
|
---|
441 | * Assumes a trap stack frame has already been setup on the guest's stack!
|
---|
442 | * This function does not return!
|
---|
443 | *
|
---|
444 | * @param pRegFrame Original trap/interrupt context
|
---|
445 | * @param selCS Code selector of handler
|
---|
446 | * @param pHandler GC virtual address of handler
|
---|
447 | * @param eflags Callee's EFLAGS
|
---|
448 | * @param selSS Stack selector for handler
|
---|
449 | * @param pEsp Stack address for handler
|
---|
450 | */
|
---|
451 | DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
|
---|
452 | uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
|
---|
453 |
|
---|
454 | /**
|
---|
455 | * Call guest V86 code directly.
|
---|
456 | *
|
---|
457 | * This function does not return!
|
---|
458 | *
|
---|
459 | * @param pRegFrame Original trap/interrupt context
|
---|
460 | */
|
---|
461 | DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
|
---|
462 |
|
---|
463 | /** @} */
|
---|
464 | #endif /* IN_RC */
|
---|
465 |
|
---|
466 | #ifdef IN_RING0
|
---|
467 | /** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
|
---|
468 | * @ingroup grp_cpum
|
---|
469 | * @{
|
---|
470 | */
|
---|
471 | VMMR0DECL(int) CPUMR0ModuleInit(void);
|
---|
472 | VMMR0DECL(int) CPUMR0ModuleTerm(void);
|
---|
473 | VMMR0DECL(int) CPUMR0Init(PVM pVM);
|
---|
474 | VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
|
---|
475 | VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
|
---|
476 | VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
|
---|
477 | VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
|
---|
478 | VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu);
|
---|
479 | VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
|
---|
480 | VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
|
---|
481 | #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
|
---|
482 | VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu);
|
---|
483 | #endif
|
---|
484 |
|
---|
485 | /** @} */
|
---|
486 | #endif /* IN_RING0 */
|
---|
487 |
|
---|
488 | /** @} */
|
---|
489 | RT_C_DECLS_END
|
---|
490 |
|
---|
491 |
|
---|
492 | #endif
|
---|
493 |
|
---|