cpum.h@ 55000

Last change on this file since 55000 was 55000, checked in by vboxsync, 10 years ago
CPUMCTXCORE elimination.
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Line
1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpum_h
27	#define ___VBox_vmm_cpum_h
28
29	#include <iprt/x86.h>
30	#include <VBox/types.h>
31	#include <VBox/vmm/cpumctx.h>
32	#include <VBox/vmm/stam.h>
33
34	RT_C_DECLS_BEGIN
35
36	/** @defgroup grp_cpum The CPU Monitor / Manager API
37	* @{
38	*/
39
40	/**
41	* CPUID feature to set or clear.
42	*/
43	typedef enum CPUMCPUIDFEATURE
44	{
45	CPUMCPUIDFEATURE_INVALID = 0,
46	/** The APIC feature bit. (Std+Ext) */
47	CPUMCPUIDFEATURE_APIC,
48	/** The sysenter/sysexit feature bit. (Std) */
49	CPUMCPUIDFEATURE_SEP,
50	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
51	CPUMCPUIDFEATURE_SYSCALL,
52	/** The PAE feature bit. (Std+Ext) */
53	CPUMCPUIDFEATURE_PAE,
54	/** The NX feature bit. (Ext) */
55	CPUMCPUIDFEATURE_NX,
56	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
57	CPUMCPUIDFEATURE_LAHF,
58	/** The LONG MODE feature bit. (Ext) */
59	CPUMCPUIDFEATURE_LONG_MODE,
60	/** The PAT feature bit. (Std+Ext) */
61	CPUMCPUIDFEATURE_PAT,
62	/** The x2APIC feature bit. (Std) */
63	CPUMCPUIDFEATURE_X2APIC,
64	/** The RDTSCP feature bit. (Ext) */
65	CPUMCPUIDFEATURE_RDTSCP,
66	/** The Hypervisor Present bit. (Std) */
67	CPUMCPUIDFEATURE_HVP,
68	/** The MWait Extensions bits (Std) */
69	CPUMCPUIDFEATURE_MWAIT_EXTS,
70	/** 32bit hackishness. */
71	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
72	} CPUMCPUIDFEATURE;
73
74	/**
75	* CPU Vendor.
76	*/
77	typedef enum CPUMCPUVENDOR
78	{
79	CPUMCPUVENDOR_INVALID = 0,
80	CPUMCPUVENDOR_INTEL,
81	CPUMCPUVENDOR_AMD,
82	CPUMCPUVENDOR_VIA,
83	CPUMCPUVENDOR_CYRIX,
84	CPUMCPUVENDOR_UNKNOWN,
85	/** 32bit hackishness. */
86	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
87	} CPUMCPUVENDOR;
88
89
90	/**
91	* X86 and AMD64 CPU microarchitectures and in processor generations.
92	*
93	* @remarks The separation here is sometimes a little bit too finely grained,
94	* and the differences is more like processor generation than micro
95	* arch. This can be useful, so we'll provide functions for getting at
96	* more coarse grained info.
97	*/
98	typedef enum CPUMMICROARCH
99	{
100	kCpumMicroarch_Invalid = 0,
101
102	kCpumMicroarch_Intel_First,
103
104	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
105	kCpumMicroarch_Intel_80186,
106	kCpumMicroarch_Intel_80286,
107	kCpumMicroarch_Intel_80386,
108	kCpumMicroarch_Intel_80486,
109	kCpumMicroarch_Intel_P5,
110
111	kCpumMicroarch_Intel_P6_Core_Atom_First,
112	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
113	kCpumMicroarch_Intel_P6_II,
114	kCpumMicroarch_Intel_P6_III,
115
116	kCpumMicroarch_Intel_P6_M_Banias,
117	kCpumMicroarch_Intel_P6_M_Dothan,
118	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
119
120	kCpumMicroarch_Intel_Core2_First,
121	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
122	kCpumMicroarch_Intel_Core2_Penryn,
123
124	kCpumMicroarch_Intel_Core7_First,
125	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
126	kCpumMicroarch_Intel_Core7_Westmere,
127	kCpumMicroarch_Intel_Core7_SandyBridge,
128	kCpumMicroarch_Intel_Core7_IvyBridge,
129	kCpumMicroarch_Intel_Core7_Haswell,
130	kCpumMicroarch_Intel_Core7_Broadwell,
131	kCpumMicroarch_Intel_Core7_Skylake,
132	kCpumMicroarch_Intel_Core7_Cannonlake,
133	kCpumMicroarch_Intel_Core7_End,
134
135	kCpumMicroarch_Intel_Atom_First,
136	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
137	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
138	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
139	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
140	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
141	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
142	kCpumMicroarch_Intel_Atom_Unknown,
143	kCpumMicroarch_Intel_Atom_End,
144
145	kCpumMicroarch_Intel_P6_Core_Atom_End,
146
147	kCpumMicroarch_Intel_NB_First,
148	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
149	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
150	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
151	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
152	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
153	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
154	kCpumMicroarch_Intel_NB_Unknown,
155	kCpumMicroarch_Intel_NB_End,
156
157	kCpumMicroarch_Intel_Unknown,
158	kCpumMicroarch_Intel_End,
159
160	kCpumMicroarch_AMD_First,
161	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
162	kCpumMicroarch_AMD_Am386,
163	kCpumMicroarch_AMD_Am486,
164	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
165	kCpumMicroarch_AMD_K5,
166	kCpumMicroarch_AMD_K6,
167
168	kCpumMicroarch_AMD_K7_First,
169	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
170	kCpumMicroarch_AMD_K7_Spitfire,
171	kCpumMicroarch_AMD_K7_Thunderbird,
172	kCpumMicroarch_AMD_K7_Morgan,
173	kCpumMicroarch_AMD_K7_Thoroughbred,
174	kCpumMicroarch_AMD_K7_Barton,
175	kCpumMicroarch_AMD_K7_Unknown,
176	kCpumMicroarch_AMD_K7_End,
177
178	kCpumMicroarch_AMD_K8_First,
179	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
180	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
181	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
182	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
183	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
184	kCpumMicroarch_AMD_K8_End,
185
186	kCpumMicroarch_AMD_K10,
187	kCpumMicroarch_AMD_K10_Lion,
188	kCpumMicroarch_AMD_K10_Llano,
189	kCpumMicroarch_AMD_Bobcat,
190	kCpumMicroarch_AMD_Jaguar,
191
192	kCpumMicroarch_AMD_15h_First,
193	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
194	kCpumMicroarch_AMD_15h_Piledriver,
195	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
196	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
197	kCpumMicroarch_AMD_15h_Unknown,
198	kCpumMicroarch_AMD_15h_End,
199
200	kCpumMicroarch_AMD_16h_First,
201	kCpumMicroarch_AMD_16h_End,
202
203	kCpumMicroarch_AMD_Unknown,
204	kCpumMicroarch_AMD_End,
205
206	kCpumMicroarch_VIA_First,
207	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
208	kCpumMicroarch_Centaur_C2,
209	kCpumMicroarch_Centaur_C3,
210	kCpumMicroarch_VIA_C3_M2,
211	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
212	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
213	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
214	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
215	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
216	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
217	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
218	kCpumMicroarch_VIA_Isaiah,
219	kCpumMicroarch_VIA_Unknown,
220	kCpumMicroarch_VIA_End,
221
222	kCpumMicroarch_Cyrix_First,
223	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
224	kCpumMicroarch_Cyrix_M1,
225	kCpumMicroarch_Cyrix_MediaGX,
226	kCpumMicroarch_Cyrix_MediaGXm,
227	kCpumMicroarch_Cyrix_M2,
228	kCpumMicroarch_Cyrix_Unknown,
229	kCpumMicroarch_Cyrix_End,
230
231	kCpumMicroarch_Unknown,
232
233	kCpumMicroarch_32BitHack = 0x7fffffff
234	} CPUMMICROARCH;
235
236
237	/** Predicate macro for catching netburst CPUs. */
238	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
239	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
240
241	/** Predicate macro for catching Core7 CPUs. */
242	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
243	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
244
245	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
246	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
247	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
248
249	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
250	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
251
252	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
253	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
254
255	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
256	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
257
258	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
259	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
260
261	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
262	* decendants). */
263	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
264	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
265
266	/** Predicate macro for catching AMD Family 16H CPUs. */
267	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
268	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
269
270
271
272	/**
273	* CPUID leaf.
274	*
275	* @remarks This structure is used by the patch manager and is therefore
276	* more or less set in stone.
277	*/
278	typedef struct CPUMCPUIDLEAF
279	{
280	/** The leaf number. */
281	uint32_t uLeaf;
282	/** The sub-leaf number. */
283	uint32_t uSubLeaf;
284	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
285	uint32_t fSubLeafMask;
286
287	/** The EAX value. */
288	uint32_t uEax;
289	/** The EBX value. */
290	uint32_t uEbx;
291	/** The ECX value. */
292	uint32_t uEcx;
293	/** The EDX value. */
294	uint32_t uEdx;
295
296	/** Flags. */
297	uint32_t fFlags;
298	} CPUMCPUIDLEAF;
299	AssertCompileSize(CPUMCPUIDLEAF, 32);
300	/** Pointer to a CPUID leaf. */
301	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
302	/** Pointer to a const CPUID leaf. */
303	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
304
305	/** @name CPUMCPUIDLEAF::fFlags
306	* @{ */
307	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
308	* and EDX containing the extended APIC ID. */
309	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
310	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
311	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
312	/** Mask of the valid flags. */
313	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0x3)
314	/** @} */
315
316	/**
317	* Method used to deal with unknown CPUID leaves.
318	* @remarks Used in patch code.
319	*/
320	typedef enum CPUMUNKNOWNCPUID
321	{
322	/** Invalid zero value. */
323	CPUMUNKNOWNCPUID_INVALID = 0,
324	/** Use given default values (DefCpuId). */
325	CPUMUNKNOWNCPUID_DEFAULTS,
326	/** Return the last standard leaf.
327	* Intel Sandy Bridge has been observed doing this. */
328	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
329	/** Return the last standard leaf, with ecx observed.
330	* Intel Sandy Bridge has been observed doing this. */
331	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
332	/** The register values are passed thru unmodified. */
333	CPUMUNKNOWNCPUID_PASSTHRU,
334	/** End of valid value. */
335	CPUMUNKNOWNCPUID_END,
336	/** Ensure 32-bit type. */
337	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
338	} CPUMUNKNOWNCPUID;
339	/** Pointer to unknown CPUID leaf method. */
340	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
341
342
343	/**
344	* MSR read functions.
345	*/
346	typedef enum CPUMMSRRDFN
347	{
348	/** Invalid zero value. */
349	kCpumMsrRdFn_Invalid = 0,
350	/** Return the CPUMMSRRANGE::uValue. */
351	kCpumMsrRdFn_FixedValue,
352	/** Alias to the MSR range starting at the MSR given by
353	* CPUMMSRRANGE::uValue. Must be used in pair with
354	* kCpumMsrWrFn_MsrAlias. */
355	kCpumMsrRdFn_MsrAlias,
356	/** Write only register, GP all read attempts. */
357	kCpumMsrRdFn_WriteOnly,
358
359	kCpumMsrRdFn_Ia32P5McAddr,
360	kCpumMsrRdFn_Ia32P5McType,
361	kCpumMsrRdFn_Ia32TimestampCounter,
362	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
363	kCpumMsrRdFn_Ia32ApicBase,
364	kCpumMsrRdFn_Ia32FeatureControl,
365	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
366	kCpumMsrRdFn_Ia32SmmMonitorCtl,
367	kCpumMsrRdFn_Ia32PmcN,
368	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
369	kCpumMsrRdFn_Ia32MPerf,
370	kCpumMsrRdFn_Ia32APerf,
371	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
372	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
373	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
374	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
375	kCpumMsrRdFn_Ia32MtrrDefType,
376	kCpumMsrRdFn_Ia32Pat,
377	kCpumMsrRdFn_Ia32SysEnterCs,
378	kCpumMsrRdFn_Ia32SysEnterEsp,
379	kCpumMsrRdFn_Ia32SysEnterEip,
380	kCpumMsrRdFn_Ia32McgCap,
381	kCpumMsrRdFn_Ia32McgStatus,
382	kCpumMsrRdFn_Ia32McgCtl,
383	kCpumMsrRdFn_Ia32DebugCtl,
384	kCpumMsrRdFn_Ia32SmrrPhysBase,
385	kCpumMsrRdFn_Ia32SmrrPhysMask,
386	kCpumMsrRdFn_Ia32PlatformDcaCap,
387	kCpumMsrRdFn_Ia32CpuDcaCap,
388	kCpumMsrRdFn_Ia32Dca0Cap,
389	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
390	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
391	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
392	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
393	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
394	kCpumMsrRdFn_Ia32FixedCtrCtrl,
395	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
396	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
397	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
398	kCpumMsrRdFn_Ia32PebsEnable,
399	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
400	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
401	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
402	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
403	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
404	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
405	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
406	kCpumMsrRdFn_Ia32DsArea,
407	kCpumMsrRdFn_Ia32TscDeadline,
408	kCpumMsrRdFn_Ia32X2ApicN,
409	kCpumMsrRdFn_Ia32DebugInterface,
410	kCpumMsrRdFn_Ia32VmxBase, /*< Takes real value as reference. /
411	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
412	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
413	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
414	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
415	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
416	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
417	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
418	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
419	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
420	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
421	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
422	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
423	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
424	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
425	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
426	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
427
428	kCpumMsrRdFn_Amd64Efer,
429	kCpumMsrRdFn_Amd64SyscallTarget,
430	kCpumMsrRdFn_Amd64LongSyscallTarget,
431	kCpumMsrRdFn_Amd64CompSyscallTarget,
432	kCpumMsrRdFn_Amd64SyscallFlagMask,
433	kCpumMsrRdFn_Amd64FsBase,
434	kCpumMsrRdFn_Amd64GsBase,
435	kCpumMsrRdFn_Amd64KernelGsBase,
436	kCpumMsrRdFn_Amd64TscAux,
437
438	kCpumMsrRdFn_IntelEblCrPowerOn,
439	kCpumMsrRdFn_IntelI7CoreThreadCount,
440	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
441	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
442	kCpumMsrRdFn_IntelP4EbcFrequencyId,
443	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
444	kCpumMsrRdFn_IntelPlatformInfo,
445	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
446	kCpumMsrRdFn_IntelPkgCStConfigControl,
447	kCpumMsrRdFn_IntelPmgIoCaptureBase,
448	kCpumMsrRdFn_IntelLastBranchFromToN,
449	kCpumMsrRdFn_IntelLastBranchFromN,
450	kCpumMsrRdFn_IntelLastBranchToN,
451	kCpumMsrRdFn_IntelLastBranchTos,
452	kCpumMsrRdFn_IntelBblCrCtl,
453	kCpumMsrRdFn_IntelBblCrCtl3,
454	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
455	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
456	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
457	kCpumMsrRdFn_IntelP6CrN,
458	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
459	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
460	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
461	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
462	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
463	kCpumMsrRdFn_IntelI7LbrSelect,
464	kCpumMsrRdFn_IntelI7SandyErrorControl,
465	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
466	kCpumMsrRdFn_IntelI7PowerCtl,
467	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
468	kCpumMsrRdFn_IntelI7PebsLdLat,
469	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
470	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
471	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
472	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
473	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
474	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
475	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
476	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
477	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
478	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
479	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
480	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
481	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
482	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
483	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
484	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
485	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
486	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
487	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
488	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
489	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
490	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
491	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
492	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
493	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
494	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
495	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
496	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
497	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
498	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
499	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
500	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
501	kCpumMsrRdFn_IntelI7UncCBoxConfig,
502	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
503	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
504	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
505	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
506	kCpumMsrRdFn_IntelCore1ExtConfig,
507	kCpumMsrRdFn_IntelCore1DtsCalControl,
508	kCpumMsrRdFn_IntelCore2PeciControl,
509
510	kCpumMsrRdFn_P6LastBranchFromIp,
511	kCpumMsrRdFn_P6LastBranchToIp,
512	kCpumMsrRdFn_P6LastIntFromIp,
513	kCpumMsrRdFn_P6LastIntToIp,
514
515	kCpumMsrRdFn_AmdFam15hTscRate,
516	kCpumMsrRdFn_AmdFam15hLwpCfg,
517	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
518	kCpumMsrRdFn_AmdFam10hMc4MiscN,
519	kCpumMsrRdFn_AmdK8PerfCtlN,
520	kCpumMsrRdFn_AmdK8PerfCtrN,
521	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
522	kCpumMsrRdFn_AmdK8HwCr,
523	kCpumMsrRdFn_AmdK8IorrBaseN,
524	kCpumMsrRdFn_AmdK8IorrMaskN,
525	kCpumMsrRdFn_AmdK8TopOfMemN,
526	kCpumMsrRdFn_AmdK8NbCfg1,
527	kCpumMsrRdFn_AmdK8McXcptRedir,
528	kCpumMsrRdFn_AmdK8CpuNameN,
529	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
530	kCpumMsrRdFn_AmdK8SwThermalCtrl,
531	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
532	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
533	kCpumMsrRdFn_AmdK8McCtlMaskN,
534	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
535	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
536	kCpumMsrRdFn_AmdK8IntPendingMessage,
537	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
538	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
539	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
540	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
541	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
542	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
543	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
544	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
545	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
546	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
547	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
548	kCpumMsrRdFn_AmdK8SmmBase,
549	kCpumMsrRdFn_AmdK8SmmAddr,
550	kCpumMsrRdFn_AmdK8SmmMask,
551	kCpumMsrRdFn_AmdK8VmCr,
552	kCpumMsrRdFn_AmdK8IgnNe,
553	kCpumMsrRdFn_AmdK8SmmCtl,
554	kCpumMsrRdFn_AmdK8VmHSavePa,
555	kCpumMsrRdFn_AmdFam10hVmLockKey,
556	kCpumMsrRdFn_AmdFam10hSmmLockKey,
557	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
558	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
559	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
560	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
561	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
562	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
563	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
564	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
565	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
566	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
567	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
568	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
569	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
570	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
571	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
572	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
573	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
574	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
575	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
576	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
577	kCpumMsrRdFn_AmdK7NodeId,
578	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
579	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
580	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
581	kCpumMsrRdFn_AmdK7LoadStoreCfg,
582	kCpumMsrRdFn_AmdK7InstrCacheCfg,
583	kCpumMsrRdFn_AmdK7DataCacheCfg,
584	kCpumMsrRdFn_AmdK7BusUnitCfg,
585	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
586	kCpumMsrRdFn_AmdFam15hFpuCfg,
587	kCpumMsrRdFn_AmdFam15hDecoderCfg,
588	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
589	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
590	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
591	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
592	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
593	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
594	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
595	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
596	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
597	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
598	kCpumMsrRdFn_AmdFam10hIbsOpRip,
599	kCpumMsrRdFn_AmdFam10hIbsOpData,
600	kCpumMsrRdFn_AmdFam10hIbsOpData2,
601	kCpumMsrRdFn_AmdFam10hIbsOpData3,
602	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
603	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
604	kCpumMsrRdFn_AmdFam10hIbsCtl,
605	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
606
607	kCpumMsrRdFn_Gim,
608
609	/** End of valid MSR read function indexes. */
610	kCpumMsrRdFn_End
611	} CPUMMSRRDFN;
612
613	/**
614	* MSR write functions.
615	*/
616	typedef enum CPUMMSRWRFN
617	{
618	/** Invalid zero value. */
619	kCpumMsrWrFn_Invalid = 0,
620	/** Writes are ignored, the fWrGpMask is observed though. */
621	kCpumMsrWrFn_IgnoreWrite,
622	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
623	kCpumMsrWrFn_ReadOnly,
624	/** Alias to the MSR range starting at the MSR given by
625	* CPUMMSRRANGE::uValue. Must be used in pair with
626	* kCpumMsrRdFn_MsrAlias. */
627	kCpumMsrWrFn_MsrAlias,
628
629	kCpumMsrWrFn_Ia32P5McAddr,
630	kCpumMsrWrFn_Ia32P5McType,
631	kCpumMsrWrFn_Ia32TimestampCounter,
632	kCpumMsrWrFn_Ia32ApicBase,
633	kCpumMsrWrFn_Ia32FeatureControl,
634	kCpumMsrWrFn_Ia32BiosSignId,
635	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
636	kCpumMsrWrFn_Ia32SmmMonitorCtl,
637	kCpumMsrWrFn_Ia32PmcN,
638	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
639	kCpumMsrWrFn_Ia32MPerf,
640	kCpumMsrWrFn_Ia32APerf,
641	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
642	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
643	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
644	kCpumMsrWrFn_Ia32MtrrDefType,
645	kCpumMsrWrFn_Ia32Pat,
646	kCpumMsrWrFn_Ia32SysEnterCs,
647	kCpumMsrWrFn_Ia32SysEnterEsp,
648	kCpumMsrWrFn_Ia32SysEnterEip,
649	kCpumMsrWrFn_Ia32McgStatus,
650	kCpumMsrWrFn_Ia32McgCtl,
651	kCpumMsrWrFn_Ia32DebugCtl,
652	kCpumMsrWrFn_Ia32SmrrPhysBase,
653	kCpumMsrWrFn_Ia32SmrrPhysMask,
654	kCpumMsrWrFn_Ia32PlatformDcaCap,
655	kCpumMsrWrFn_Ia32Dca0Cap,
656	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
657	kCpumMsrWrFn_Ia32PerfStatus,
658	kCpumMsrWrFn_Ia32PerfCtl,
659	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
660	kCpumMsrWrFn_Ia32PerfCapabilities,
661	kCpumMsrWrFn_Ia32FixedCtrCtrl,
662	kCpumMsrWrFn_Ia32PerfGlobalStatus,
663	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
664	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
665	kCpumMsrWrFn_Ia32PebsEnable,
666	kCpumMsrWrFn_Ia32ClockModulation,
667	kCpumMsrWrFn_Ia32ThermInterrupt,
668	kCpumMsrWrFn_Ia32ThermStatus,
669	kCpumMsrWrFn_Ia32Therm2Ctl,
670	kCpumMsrWrFn_Ia32MiscEnable,
671	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
672	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
673	kCpumMsrWrFn_Ia32DsArea,
674	kCpumMsrWrFn_Ia32TscDeadline,
675	kCpumMsrWrFn_Ia32X2ApicN,
676	kCpumMsrWrFn_Ia32DebugInterface,
677
678	kCpumMsrWrFn_Amd64Efer,
679	kCpumMsrWrFn_Amd64SyscallTarget,
680	kCpumMsrWrFn_Amd64LongSyscallTarget,
681	kCpumMsrWrFn_Amd64CompSyscallTarget,
682	kCpumMsrWrFn_Amd64SyscallFlagMask,
683	kCpumMsrWrFn_Amd64FsBase,
684	kCpumMsrWrFn_Amd64GsBase,
685	kCpumMsrWrFn_Amd64KernelGsBase,
686	kCpumMsrWrFn_Amd64TscAux,
687	kCpumMsrWrFn_IntelEblCrPowerOn,
688	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
689	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
690	kCpumMsrWrFn_IntelP4EbcFrequencyId,
691	kCpumMsrWrFn_IntelFlexRatio,
692	kCpumMsrWrFn_IntelPkgCStConfigControl,
693	kCpumMsrWrFn_IntelPmgIoCaptureBase,
694	kCpumMsrWrFn_IntelLastBranchFromToN,
695	kCpumMsrWrFn_IntelLastBranchFromN,
696	kCpumMsrWrFn_IntelLastBranchToN,
697	kCpumMsrWrFn_IntelLastBranchTos,
698	kCpumMsrWrFn_IntelBblCrCtl,
699	kCpumMsrWrFn_IntelBblCrCtl3,
700	kCpumMsrWrFn_IntelI7TemperatureTarget,
701	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
702	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
703	kCpumMsrWrFn_IntelP6CrN,
704	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
705	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
706	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
707	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
708	kCpumMsrWrFn_IntelI7TurboRatioLimit,
709	kCpumMsrWrFn_IntelI7LbrSelect,
710	kCpumMsrWrFn_IntelI7SandyErrorControl,
711	kCpumMsrWrFn_IntelI7PowerCtl,
712	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
713	kCpumMsrWrFn_IntelI7PebsLdLat,
714	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
715	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
716	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
717	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
718	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
719	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
720	kCpumMsrWrFn_IntelI7RaplPp0Policy,
721	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
722	kCpumMsrWrFn_IntelI7RaplPp1Policy,
723	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
724	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
725	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
726	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
727	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
728	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
729	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
730	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
731	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
732	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
733	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
734	kCpumMsrWrFn_IntelCore1ExtConfig,
735	kCpumMsrWrFn_IntelCore1DtsCalControl,
736	kCpumMsrWrFn_IntelCore2PeciControl,
737
738	kCpumMsrWrFn_P6LastIntFromIp,
739	kCpumMsrWrFn_P6LastIntToIp,
740
741	kCpumMsrWrFn_AmdFam15hTscRate,
742	kCpumMsrWrFn_AmdFam15hLwpCfg,
743	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
744	kCpumMsrWrFn_AmdFam10hMc4MiscN,
745	kCpumMsrWrFn_AmdK8PerfCtlN,
746	kCpumMsrWrFn_AmdK8PerfCtrN,
747	kCpumMsrWrFn_AmdK8SysCfg,
748	kCpumMsrWrFn_AmdK8HwCr,
749	kCpumMsrWrFn_AmdK8IorrBaseN,
750	kCpumMsrWrFn_AmdK8IorrMaskN,
751	kCpumMsrWrFn_AmdK8TopOfMemN,
752	kCpumMsrWrFn_AmdK8NbCfg1,
753	kCpumMsrWrFn_AmdK8McXcptRedir,
754	kCpumMsrWrFn_AmdK8CpuNameN,
755	kCpumMsrWrFn_AmdK8HwThermalCtrl,
756	kCpumMsrWrFn_AmdK8SwThermalCtrl,
757	kCpumMsrWrFn_AmdK8FidVidControl,
758	kCpumMsrWrFn_AmdK8McCtlMaskN,
759	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
760	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
761	kCpumMsrWrFn_AmdK8IntPendingMessage,
762	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
763	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
764	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
765	kCpumMsrWrFn_AmdFam10hPStateControl,
766	kCpumMsrWrFn_AmdFam10hPStateStatus,
767	kCpumMsrWrFn_AmdFam10hPStateN,
768	kCpumMsrWrFn_AmdFam10hCofVidControl,
769	kCpumMsrWrFn_AmdFam10hCofVidStatus,
770	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
771	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
772	kCpumMsrWrFn_AmdK8SmmBase,
773	kCpumMsrWrFn_AmdK8SmmAddr,
774	kCpumMsrWrFn_AmdK8SmmMask,
775	kCpumMsrWrFn_AmdK8VmCr,
776	kCpumMsrWrFn_AmdK8IgnNe,
777	kCpumMsrWrFn_AmdK8SmmCtl,
778	kCpumMsrWrFn_AmdK8VmHSavePa,
779	kCpumMsrWrFn_AmdFam10hVmLockKey,
780	kCpumMsrWrFn_AmdFam10hSmmLockKey,
781	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
782	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
783	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
784	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
785	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
786	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
787	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
788	kCpumMsrWrFn_AmdK7MicrocodeCtl,
789	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
790	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
791	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
792	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
793	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
794	kCpumMsrWrFn_AmdK8PatchLoader,
795	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
796	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
797	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
798	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
799	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
800	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
801	kCpumMsrWrFn_AmdK7NodeId,
802	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
803	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
804	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
805	kCpumMsrWrFn_AmdK7LoadStoreCfg,
806	kCpumMsrWrFn_AmdK7InstrCacheCfg,
807	kCpumMsrWrFn_AmdK7DataCacheCfg,
808	kCpumMsrWrFn_AmdK7BusUnitCfg,
809	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
810	kCpumMsrWrFn_AmdFam15hFpuCfg,
811	kCpumMsrWrFn_AmdFam15hDecoderCfg,
812	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
813	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
814	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
815	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
816	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
817	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
818	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
819	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
820	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
821	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
822	kCpumMsrWrFn_AmdFam10hIbsOpRip,
823	kCpumMsrWrFn_AmdFam10hIbsOpData,
824	kCpumMsrWrFn_AmdFam10hIbsOpData2,
825	kCpumMsrWrFn_AmdFam10hIbsOpData3,
826	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
827	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
828	kCpumMsrWrFn_AmdFam10hIbsCtl,
829	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
830
831	kCpumMsrWrFn_Gim,
832
833	/** End of valid MSR write function indexes. */
834	kCpumMsrWrFn_End
835	} CPUMMSRWRFN;
836
837	/**
838	* MSR range.
839	*/
840	typedef struct CPUMMSRRANGE
841	{
842	/** The first MSR. [0] */
843	uint32_t uFirst;
844	/** The last MSR. [4] */
845	uint32_t uLast;
846	/** The read function (CPUMMSRRDFN). [8] */
847	uint16_t enmRdFn;
848	/** The write function (CPUMMSRWRFN). [10] */
849	uint16_t enmWrFn;
850	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
851	* UINT16_MAX if not used by the read and write functions. [12] */
852	uint16_t offCpumCpu;
853	/** Reserved for future hacks. [14] */
854	uint16_t fReserved;
855	/** The init/read value. [16]
856	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
857	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
858	* offset into CPUM. */
859	uint64_t uValue;
860	/** The bits to ignore when writing. [24] */
861	uint64_t fWrIgnMask;
862	/** The bits that will cause a GP(0) when writing. [32]
863	* This is always checked prior to calling the write function. Using
864	* UINT64_MAX effectively marks the MSR as read-only. */
865	uint64_t fWrGpMask;
866	/** The register name, if applicable. [40] */
867	char szName[56];
868
869	#ifdef VBOX_WITH_STATISTICS
870	/** The number of reads. */
871	STAMCOUNTER cReads;
872	/** The number of writes. */
873	STAMCOUNTER cWrites;
874	/** The number of times ignored bits were written. */
875	STAMCOUNTER cIgnoredBits;
876	/** The number of GPs generated. */
877	STAMCOUNTER cGps;
878	#endif
879	} CPUMMSRRANGE;
880	#ifdef VBOX_WITH_STATISTICS
881	AssertCompileSize(CPUMMSRRANGE, 128);
882	#else
883	AssertCompileSize(CPUMMSRRANGE, 96);
884	#endif
885	/** Pointer to an MSR range. */
886	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
887	/** Pointer to a const MSR range. */
888	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
889
890
891	/** @name Guest Register Getters.
892	* @{ */
893	VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
894	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
895	VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
896	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
897	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
898	VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
899	VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
900	VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
901	VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
902	VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
903	VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
904	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
905	VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
906	VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
907	VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
908	VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
909	VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
910	VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
911	VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
912	VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
913	VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
914	VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
915	VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
916	VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
917	VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
918	VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
919	VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
920	VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
921	VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
922	VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
923	VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
924	VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
925	VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
926	VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
927	VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
928	VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
929	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
930	VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
931	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
932	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
933	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
934	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
935	/** @} */
936
937	/** @name Guest Register Setters.
938	* @{ */
939	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
940	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
941	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
942	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
943	VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
944	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
945	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
946	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
947	VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
948	VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
949	VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
950	VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
951	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
952	VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
953	VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
954	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
955	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
956	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
957	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
958	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
959	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
960	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
961	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
962	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
963	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
964	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
965	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
966	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
967	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
968	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
969	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
970	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
971	VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
972	VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
973	VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
974	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
975	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
976	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
977	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
978	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
979	/** @} */
980
981
982	/** @name Misc Guest Predicate Functions.
983	* @{ */
984
985	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
986	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
987	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
988	VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
989	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
990	VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
991	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
992	VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
993	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
994	VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
995	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
996	VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
997	VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
998	VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
999
1000	#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
1001
1002	/**
1003	* Tests if the guest is running in real mode or not.
1004	*
1005	* @returns true if in real mode, otherwise false.
1006	* @param pCtx Current CPU context
1007	*/
1008	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1009	{
1010	return !(pCtx->cr0 & X86_CR0_PE);
1011	}
1012
1013	/**
1014	* Tests if the guest is running in real or virtual 8086 mode.
1015	*
1016	* @returns @c true if it is, @c false if not.
1017	* @param pCtx Current CPU context
1018	*/
1019	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1020	{
1021	return !(pCtx->cr0 & X86_CR0_PE)
1022	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1023	}
1024
1025	/**
1026	* Tests if the guest is running in virtual 8086 mode.
1027	*
1028	* @returns @c true if it is, @c false if not.
1029	* @param pCtx Current CPU context
1030	*/
1031	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1032	{
1033	return (pCtx->eflags.Bits.u1VM == 1);
1034	}
1035
1036	/**
1037	* Tests if the guest is running in paged protected or not.
1038	*
1039	* @returns true if in paged protected mode, otherwise false.
1040	* @param pVM The VM handle.
1041	*/
1042	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1043	{
1044	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1045	}
1046
1047	/**
1048	* Tests if the guest is running in long mode or not.
1049	*
1050	* @returns true if in long mode, otherwise false.
1051	* @param pCtx Current CPU context
1052	*/
1053	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1054	{
1055	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1056	}
1057
1058	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1059
1060	/**
1061	* Tests if the guest is running in 64 bits mode or not.
1062	*
1063	* @returns true if in 64 bits protected mode, otherwise false.
1064	* @param pVCpu The current virtual CPU.
1065	* @param pCtx Current CPU context
1066	*/
1067	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1068	{
1069	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1070	return false;
1071	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1072	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1073	return pCtx->cs.Attr.n.u1Long;
1074	}
1075
1076	/**
1077	* Tests if the guest has paging enabled or not.
1078	*
1079	* @returns true if paging is enabled, otherwise false.
1080	* @param pCtx Current CPU context
1081	*/
1082	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1083	{
1084	return !!(pCtx->cr0 & X86_CR0_PG);
1085	}
1086
1087	/**
1088	* Tests if the guest is running in PAE mode or not.
1089	*
1090	* @returns true if in PAE mode, otherwise false.
1091	* @param pCtx Current CPU context
1092	*/
1093	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1094	{
1095	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1096	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1097	return ( (pCtx->cr4 & X86_CR4_PAE)
1098	&& CPUMIsGuestPagingEnabledEx(pCtx)
1099	&& !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1100	}
1101
1102	#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
1103
1104	/** @} */
1105
1106
1107	/** @name Hypervisor Register Getters.
1108	* @{ */
1109	VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1110	VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1111	VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1112	VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1113	VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1114	VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1115	#if 0 /* these are not correct. */
1116	VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1117	VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1118	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1119	VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1120	#endif
1121	/** This register is only saved on fatal traps. */
1122	VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1123	VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1124	/** This register is only saved on fatal traps. */
1125	VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1126	/** This register is only saved on fatal traps. */
1127	VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1128	VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1129	VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1130	VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1131	VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1132	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1133	VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1134	VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1135	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1136	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1137	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1138	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1139	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1140	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1141	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1142	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1143	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1144	VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1145	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1146	/** @} */
1147
1148	/** @name Hypervisor Register Setters.
1149	* @{ */
1150	VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1151	VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1152	VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1153	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1154	VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1155	VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1156	VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1157	VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1158	VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1159	VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1160	VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1161	VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1162	VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1163	VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1164	VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1165	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1166	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1167	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1168	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1169	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1170	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1171	VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1172	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1173	/** @} */
1174
1175	VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1176	VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1177	VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1178	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1179	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1180	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1181	VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1182	VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1183	VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1184	VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1185
1186	/** @name Changed flags.
1187	* These flags are used to keep track of which important register that
1188	* have been changed since last they were reset. The only one allowed
1189	* to clear them is REM!
1190	* @{
1191	*/
1192	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1193	#define CPUM_CHANGED_CR0 RT_BIT(1)
1194	#define CPUM_CHANGED_CR4 RT_BIT(2)
1195	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1196	#define CPUM_CHANGED_CR3 RT_BIT(4)
1197	#define CPUM_CHANGED_GDTR RT_BIT(5)
1198	#define CPUM_CHANGED_IDTR RT_BIT(6)
1199	#define CPUM_CHANGED_LDTR RT_BIT(7)
1200	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
1201	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1202	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
1203	#define CPUM_CHANGED_CPUID RT_BIT(11)
1204	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1205	\| CPUM_CHANGED_CR0 \
1206	\| CPUM_CHANGED_CR4 \
1207	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1208	\| CPUM_CHANGED_CR3 \
1209	\| CPUM_CHANGED_GDTR \
1210	\| CPUM_CHANGED_IDTR \
1211	\| CPUM_CHANGED_LDTR \
1212	\| CPUM_CHANGED_TR \
1213	\| CPUM_CHANGED_SYSENTER_MSR \
1214	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
1215	\| CPUM_CHANGED_CPUID )
1216	/** @} */
1217
1218	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
1219	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1220	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1221	VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
1222	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1223	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1224	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1225	VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
1226	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1227	VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1228	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1229	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1230	VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1231	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1232	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1233	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1234	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1235	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1236
1237	/** @name Typical scalable bus frequency values.
1238	* @{ */
1239	/** Special internal value indicating that we don't know the frequency.
1240	* @internal */
1241	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1242	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1243	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1244	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1245	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1246	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1247	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1248	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1249	/** @} */
1250
1251
1252	#ifdef IN_RING3
1253	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1254	* @{
1255	*/
1256
1257	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1258	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM);
1259	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1260	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1261	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1262	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1263	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1264	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1265	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1266	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1267
1268	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1269	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1270	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1271	uint8_t bModel, uint8_t bStepping);
1272	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1273	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1274	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1275	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1276	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1277	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1278
1279	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1280
1281	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
1282	/** @name APIs for the CPUID raw-mode patch (legacy).
1283	* @{ */
1284	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1285	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1286	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1287	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1288	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1289	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1290	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1291	/** @} */
1292	# endif
1293
1294	/** @} */
1295	#endif /* IN_RING3 */
1296
1297	#ifdef IN_RC
1298	/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1299	* @{
1300	*/
1301
1302	/**
1303	* Calls a guest trap/interrupt handler directly
1304	*
1305	* Assumes a trap stack frame has already been setup on the guest's stack!
1306	* This function does not return!
1307	*
1308	* @param pRegFrame Original trap/interrupt context
1309	* @param selCS Code selector of handler
1310	* @param pHandler GC virtual address of handler
1311	* @param eflags Callee's EFLAGS
1312	* @param selSS Stack selector for handler
1313	* @param pEsp Stack address for handler
1314	*/
1315	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1316	uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1317
1318	/**
1319	* Call guest V86 code directly.
1320	*
1321	* This function does not return!
1322	*
1323	* @param pRegFrame Original trap/interrupt context
1324	*/
1325	DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1326
1327	VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1328	VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1329	#ifdef VBOX_WITH_RAW_RING1
1330	VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1331	#endif
1332
1333	/** @} */
1334	#endif /* IN_RC */
1335
1336	#ifdef IN_RING0
1337	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1338	* @{
1339	*/
1340	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1341	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1342	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1343	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1344	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1345	VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1346	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1347	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1348	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1349
1350	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1351	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1352	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1353	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1354	#endif
1355
1356	/** @} */
1357	#endif /* IN_RING0 */
1358
1359	/** @} */
1360	RT_C_DECLS_END
1361
1362
1363	#endif
1364

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 55000

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