VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 60188

Last change on this file since 60188 was 58996, checked in by vboxsync, 9 years ago

CPUM: dtrace library fixes.
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2015 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpum_h
27#define ___VBox_vmm_cpum_h
28
29#include <iprt/x86.h>
30#include <VBox/types.h>
31#include <VBox/vmm/cpumctx.h>
32#include <VBox/vmm/stam.h>
33
34RT_C_DECLS_BEGIN
35
36/** @defgroup grp_cpum The CPU Monitor / Manager API
37 * @ingroup grp_vmm
38 * @{
39 */
40
41/**
42 * CPUID feature to set or clear.
43 */
44typedef enum CPUMCPUIDFEATURE
45{
46 CPUMCPUIDFEATURE_INVALID = 0,
47 /** The APIC feature bit. (Std+Ext) */
48 CPUMCPUIDFEATURE_APIC,
49 /** The sysenter/sysexit feature bit. (Std) */
50 CPUMCPUIDFEATURE_SEP,
51 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
52 CPUMCPUIDFEATURE_SYSCALL,
53 /** The PAE feature bit. (Std+Ext) */
54 CPUMCPUIDFEATURE_PAE,
55 /** The NX feature bit. (Ext) */
56 CPUMCPUIDFEATURE_NX,
57 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
58 CPUMCPUIDFEATURE_LAHF,
59 /** The LONG MODE feature bit. (Ext) */
60 CPUMCPUIDFEATURE_LONG_MODE,
61 /** The PAT feature bit. (Std+Ext) */
62 CPUMCPUIDFEATURE_PAT,
63 /** The x2APIC feature bit. (Std) */
64 CPUMCPUIDFEATURE_X2APIC,
65 /** The RDTSCP feature bit. (Ext) */
66 CPUMCPUIDFEATURE_RDTSCP,
67 /** The Hypervisor Present bit. (Std) */
68 CPUMCPUIDFEATURE_HVP,
69 /** The MWait Extensions bits (Std) */
70 CPUMCPUIDFEATURE_MWAIT_EXTS,
71 /** The CR4.OSXSAVE bit CPUID mirroring, only use from CPUMSetGuestCR4. */
72 CPUMCPUIDFEATURE_OSXSAVE,
73 /** 32bit hackishness. */
74 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
75} CPUMCPUIDFEATURE;
76
77/**
78 * CPU Vendor.
79 */
80typedef enum CPUMCPUVENDOR
81{
82 CPUMCPUVENDOR_INVALID = 0,
83 CPUMCPUVENDOR_INTEL,
84 CPUMCPUVENDOR_AMD,
85 CPUMCPUVENDOR_VIA,
86 CPUMCPUVENDOR_CYRIX,
87 CPUMCPUVENDOR_UNKNOWN,
88 /** 32bit hackishness. */
89 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
90} CPUMCPUVENDOR;
91
92
93/**
94 * X86 and AMD64 CPU microarchitectures and in processor generations.
95 *
96 * @remarks The separation here is sometimes a little bit too finely grained,
97 * and the differences is more like processor generation than micro
98 * arch. This can be useful, so we'll provide functions for getting at
99 * more coarse grained info.
100 */
101typedef enum CPUMMICROARCH
102{
103 kCpumMicroarch_Invalid = 0,
104
105 kCpumMicroarch_Intel_First,
106
107 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
108 kCpumMicroarch_Intel_80186,
109 kCpumMicroarch_Intel_80286,
110 kCpumMicroarch_Intel_80386,
111 kCpumMicroarch_Intel_80486,
112 kCpumMicroarch_Intel_P5,
113
114 kCpumMicroarch_Intel_P6_Core_Atom_First,
115 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
116 kCpumMicroarch_Intel_P6_II,
117 kCpumMicroarch_Intel_P6_III,
118
119 kCpumMicroarch_Intel_P6_M_Banias,
120 kCpumMicroarch_Intel_P6_M_Dothan,
121 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
122
123 kCpumMicroarch_Intel_Core2_First,
124 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
125 kCpumMicroarch_Intel_Core2_Penryn,
126
127 kCpumMicroarch_Intel_Core7_First,
128 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
129 kCpumMicroarch_Intel_Core7_Westmere,
130 kCpumMicroarch_Intel_Core7_SandyBridge,
131 kCpumMicroarch_Intel_Core7_IvyBridge,
132 kCpumMicroarch_Intel_Core7_Haswell,
133 kCpumMicroarch_Intel_Core7_Broadwell,
134 kCpumMicroarch_Intel_Core7_Skylake,
135 kCpumMicroarch_Intel_Core7_Cannonlake,
136 kCpumMicroarch_Intel_Core7_End,
137
138 kCpumMicroarch_Intel_Atom_First,
139 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
140 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
141 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
142 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
143 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
144 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
145 kCpumMicroarch_Intel_Atom_Unknown,
146 kCpumMicroarch_Intel_Atom_End,
147
148 kCpumMicroarch_Intel_P6_Core_Atom_End,
149
150 kCpumMicroarch_Intel_NB_First,
151 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
152 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
153 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
154 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
155 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
156 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
157 kCpumMicroarch_Intel_NB_Unknown,
158 kCpumMicroarch_Intel_NB_End,
159
160 kCpumMicroarch_Intel_Unknown,
161 kCpumMicroarch_Intel_End,
162
163 kCpumMicroarch_AMD_First,
164 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
165 kCpumMicroarch_AMD_Am386,
166 kCpumMicroarch_AMD_Am486,
167 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
168 kCpumMicroarch_AMD_K5,
169 kCpumMicroarch_AMD_K6,
170
171 kCpumMicroarch_AMD_K7_First,
172 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
173 kCpumMicroarch_AMD_K7_Spitfire,
174 kCpumMicroarch_AMD_K7_Thunderbird,
175 kCpumMicroarch_AMD_K7_Morgan,
176 kCpumMicroarch_AMD_K7_Thoroughbred,
177 kCpumMicroarch_AMD_K7_Barton,
178 kCpumMicroarch_AMD_K7_Unknown,
179 kCpumMicroarch_AMD_K7_End,
180
181 kCpumMicroarch_AMD_K8_First,
182 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
183 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
184 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
185 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
186 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
187 kCpumMicroarch_AMD_K8_End,
188
189 kCpumMicroarch_AMD_K10,
190 kCpumMicroarch_AMD_K10_Lion,
191 kCpumMicroarch_AMD_K10_Llano,
192 kCpumMicroarch_AMD_Bobcat,
193 kCpumMicroarch_AMD_Jaguar,
194
195 kCpumMicroarch_AMD_15h_First,
196 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
197 kCpumMicroarch_AMD_15h_Piledriver,
198 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
199 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
200 kCpumMicroarch_AMD_15h_Unknown,
201 kCpumMicroarch_AMD_15h_End,
202
203 kCpumMicroarch_AMD_16h_First,
204 kCpumMicroarch_AMD_16h_End,
205
206 kCpumMicroarch_AMD_Unknown,
207 kCpumMicroarch_AMD_End,
208
209 kCpumMicroarch_VIA_First,
210 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
211 kCpumMicroarch_Centaur_C2,
212 kCpumMicroarch_Centaur_C3,
213 kCpumMicroarch_VIA_C3_M2,
214 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
215 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
216 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
217 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
218 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
219 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
220 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
221 kCpumMicroarch_VIA_Isaiah,
222 kCpumMicroarch_VIA_Unknown,
223 kCpumMicroarch_VIA_End,
224
225 kCpumMicroarch_Cyrix_First,
226 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
227 kCpumMicroarch_Cyrix_M1,
228 kCpumMicroarch_Cyrix_MediaGX,
229 kCpumMicroarch_Cyrix_MediaGXm,
230 kCpumMicroarch_Cyrix_M2,
231 kCpumMicroarch_Cyrix_Unknown,
232 kCpumMicroarch_Cyrix_End,
233
234 kCpumMicroarch_Unknown,
235
236 kCpumMicroarch_32BitHack = 0x7fffffff
237} CPUMMICROARCH;
238
239
240/** Predicate macro for catching netburst CPUs. */
241#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
242 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
243
244/** Predicate macro for catching Core7 CPUs. */
245#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
246 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
247
248/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
249#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
250 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
251
252/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
253#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
254
255/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
256#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
257
258/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
259#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
260
261/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
262#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
263
264/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
265 * decendants). */
266#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
267 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
268
269/** Predicate macro for catching AMD Family 16H CPUs. */
270#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
271 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
272
273
274
275/**
276 * CPUID leaf.
277 *
278 * @remarks This structure is used by the patch manager and is therefore
279 * more or less set in stone.
280 */
281typedef struct CPUMCPUIDLEAF
282{
283 /** The leaf number. */
284 uint32_t uLeaf;
285 /** The sub-leaf number. */
286 uint32_t uSubLeaf;
287 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
288 uint32_t fSubLeafMask;
289
290 /** The EAX value. */
291 uint32_t uEax;
292 /** The EBX value. */
293 uint32_t uEbx;
294 /** The ECX value. */
295 uint32_t uEcx;
296 /** The EDX value. */
297 uint32_t uEdx;
298
299 /** Flags. */
300 uint32_t fFlags;
301} CPUMCPUIDLEAF;
302#ifndef VBOX_FOR_DTRACE_LIB
303AssertCompileSize(CPUMCPUIDLEAF, 32);
304#endif
305/** Pointer to a CPUID leaf. */
306typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
307/** Pointer to a const CPUID leaf. */
308typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
309
310/** @name CPUMCPUIDLEAF::fFlags
311 * @{ */
312/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
313 * and EDX containing the extended APIC ID. */
314#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
315/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
316#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
317/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
318#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
319/** Mask of the valid flags. */
320#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0x7)
321/** @} */
322
323/**
324 * Method used to deal with unknown CPUID leaves.
325 * @remarks Used in patch code.
326 */
327typedef enum CPUMUNKNOWNCPUID
328{
329 /** Invalid zero value. */
330 CPUMUNKNOWNCPUID_INVALID = 0,
331 /** Use given default values (DefCpuId). */
332 CPUMUNKNOWNCPUID_DEFAULTS,
333 /** Return the last standard leaf.
334 * Intel Sandy Bridge has been observed doing this. */
335 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
336 /** Return the last standard leaf, with ecx observed.
337 * Intel Sandy Bridge has been observed doing this. */
338 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
339 /** The register values are passed thru unmodified. */
340 CPUMUNKNOWNCPUID_PASSTHRU,
341 /** End of valid value. */
342 CPUMUNKNOWNCPUID_END,
343 /** Ensure 32-bit type. */
344 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
345} CPUMUNKNOWNCPUID;
346/** Pointer to unknown CPUID leaf method. */
347typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
348
349
350/**
351 * MSR read functions.
352 */
353typedef enum CPUMMSRRDFN
354{
355 /** Invalid zero value. */
356 kCpumMsrRdFn_Invalid = 0,
357 /** Return the CPUMMSRRANGE::uValue. */
358 kCpumMsrRdFn_FixedValue,
359 /** Alias to the MSR range starting at the MSR given by
360 * CPUMMSRRANGE::uValue. Must be used in pair with
361 * kCpumMsrWrFn_MsrAlias. */
362 kCpumMsrRdFn_MsrAlias,
363 /** Write only register, GP all read attempts. */
364 kCpumMsrRdFn_WriteOnly,
365
366 kCpumMsrRdFn_Ia32P5McAddr,
367 kCpumMsrRdFn_Ia32P5McType,
368 kCpumMsrRdFn_Ia32TimestampCounter,
369 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
370 kCpumMsrRdFn_Ia32ApicBase,
371 kCpumMsrRdFn_Ia32FeatureControl,
372 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
373 kCpumMsrRdFn_Ia32SmmMonitorCtl,
374 kCpumMsrRdFn_Ia32PmcN,
375 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
376 kCpumMsrRdFn_Ia32MPerf,
377 kCpumMsrRdFn_Ia32APerf,
378 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
379 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
380 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
381 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
382 kCpumMsrRdFn_Ia32MtrrDefType,
383 kCpumMsrRdFn_Ia32Pat,
384 kCpumMsrRdFn_Ia32SysEnterCs,
385 kCpumMsrRdFn_Ia32SysEnterEsp,
386 kCpumMsrRdFn_Ia32SysEnterEip,
387 kCpumMsrRdFn_Ia32McgCap,
388 kCpumMsrRdFn_Ia32McgStatus,
389 kCpumMsrRdFn_Ia32McgCtl,
390 kCpumMsrRdFn_Ia32DebugCtl,
391 kCpumMsrRdFn_Ia32SmrrPhysBase,
392 kCpumMsrRdFn_Ia32SmrrPhysMask,
393 kCpumMsrRdFn_Ia32PlatformDcaCap,
394 kCpumMsrRdFn_Ia32CpuDcaCap,
395 kCpumMsrRdFn_Ia32Dca0Cap,
396 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
397 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
398 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
399 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
400 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
401 kCpumMsrRdFn_Ia32FixedCtrCtrl,
402 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
403 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
404 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
405 kCpumMsrRdFn_Ia32PebsEnable,
406 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
407 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
408 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
409 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
410 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
411 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
412 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
413 kCpumMsrRdFn_Ia32DsArea,
414 kCpumMsrRdFn_Ia32TscDeadline,
415 kCpumMsrRdFn_Ia32X2ApicN,
416 kCpumMsrRdFn_Ia32DebugInterface,
417 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
418 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
419 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
420 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
421 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
422 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
423 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
424 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
425 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
426 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
427 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
428 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
429 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
430 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
431 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
432 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
433 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
434
435 kCpumMsrRdFn_Amd64Efer,
436 kCpumMsrRdFn_Amd64SyscallTarget,
437 kCpumMsrRdFn_Amd64LongSyscallTarget,
438 kCpumMsrRdFn_Amd64CompSyscallTarget,
439 kCpumMsrRdFn_Amd64SyscallFlagMask,
440 kCpumMsrRdFn_Amd64FsBase,
441 kCpumMsrRdFn_Amd64GsBase,
442 kCpumMsrRdFn_Amd64KernelGsBase,
443 kCpumMsrRdFn_Amd64TscAux,
444
445 kCpumMsrRdFn_IntelEblCrPowerOn,
446 kCpumMsrRdFn_IntelI7CoreThreadCount,
447 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
448 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
449 kCpumMsrRdFn_IntelP4EbcFrequencyId,
450 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
451 kCpumMsrRdFn_IntelPlatformInfo,
452 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
453 kCpumMsrRdFn_IntelPkgCStConfigControl,
454 kCpumMsrRdFn_IntelPmgIoCaptureBase,
455 kCpumMsrRdFn_IntelLastBranchFromToN,
456 kCpumMsrRdFn_IntelLastBranchFromN,
457 kCpumMsrRdFn_IntelLastBranchToN,
458 kCpumMsrRdFn_IntelLastBranchTos,
459 kCpumMsrRdFn_IntelBblCrCtl,
460 kCpumMsrRdFn_IntelBblCrCtl3,
461 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
462 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
463 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
464 kCpumMsrRdFn_IntelP6CrN,
465 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
466 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
467 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
468 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
469 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
470 kCpumMsrRdFn_IntelI7LbrSelect,
471 kCpumMsrRdFn_IntelI7SandyErrorControl,
472 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
473 kCpumMsrRdFn_IntelI7PowerCtl,
474 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
475 kCpumMsrRdFn_IntelI7PebsLdLat,
476 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
477 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
478 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
479 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
480 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
481 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
482 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
483 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
484 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
485 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
486 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
487 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
488 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
489 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
490 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
491 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
492 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
493 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
494 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
495 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
496 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
497 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
498 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
499 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
500 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
501 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
502 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
503 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
504 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
505 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
506 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
507 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
508 kCpumMsrRdFn_IntelI7UncCBoxConfig,
509 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
510 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
511 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
512 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
513 kCpumMsrRdFn_IntelCore1ExtConfig,
514 kCpumMsrRdFn_IntelCore1DtsCalControl,
515 kCpumMsrRdFn_IntelCore2PeciControl,
516
517 kCpumMsrRdFn_P6LastBranchFromIp,
518 kCpumMsrRdFn_P6LastBranchToIp,
519 kCpumMsrRdFn_P6LastIntFromIp,
520 kCpumMsrRdFn_P6LastIntToIp,
521
522 kCpumMsrRdFn_AmdFam15hTscRate,
523 kCpumMsrRdFn_AmdFam15hLwpCfg,
524 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
525 kCpumMsrRdFn_AmdFam10hMc4MiscN,
526 kCpumMsrRdFn_AmdK8PerfCtlN,
527 kCpumMsrRdFn_AmdK8PerfCtrN,
528 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
529 kCpumMsrRdFn_AmdK8HwCr,
530 kCpumMsrRdFn_AmdK8IorrBaseN,
531 kCpumMsrRdFn_AmdK8IorrMaskN,
532 kCpumMsrRdFn_AmdK8TopOfMemN,
533 kCpumMsrRdFn_AmdK8NbCfg1,
534 kCpumMsrRdFn_AmdK8McXcptRedir,
535 kCpumMsrRdFn_AmdK8CpuNameN,
536 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
537 kCpumMsrRdFn_AmdK8SwThermalCtrl,
538 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
539 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
540 kCpumMsrRdFn_AmdK8McCtlMaskN,
541 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
542 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
543 kCpumMsrRdFn_AmdK8IntPendingMessage,
544 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
545 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
546 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
547 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
548 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
549 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
550 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
551 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
552 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
553 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
554 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
555 kCpumMsrRdFn_AmdK8SmmBase,
556 kCpumMsrRdFn_AmdK8SmmAddr,
557 kCpumMsrRdFn_AmdK8SmmMask,
558 kCpumMsrRdFn_AmdK8VmCr,
559 kCpumMsrRdFn_AmdK8IgnNe,
560 kCpumMsrRdFn_AmdK8SmmCtl,
561 kCpumMsrRdFn_AmdK8VmHSavePa,
562 kCpumMsrRdFn_AmdFam10hVmLockKey,
563 kCpumMsrRdFn_AmdFam10hSmmLockKey,
564 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
565 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
566 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
567 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
568 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
569 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
570 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
571 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
572 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
573 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
574 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
575 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
576 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
577 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
578 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
579 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
580 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
581 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
582 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
583 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
584 kCpumMsrRdFn_AmdK7NodeId,
585 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
586 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
587 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
588 kCpumMsrRdFn_AmdK7LoadStoreCfg,
589 kCpumMsrRdFn_AmdK7InstrCacheCfg,
590 kCpumMsrRdFn_AmdK7DataCacheCfg,
591 kCpumMsrRdFn_AmdK7BusUnitCfg,
592 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
593 kCpumMsrRdFn_AmdFam15hFpuCfg,
594 kCpumMsrRdFn_AmdFam15hDecoderCfg,
595 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
596 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
597 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
598 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
599 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
600 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
601 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
602 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
603 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
604 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
605 kCpumMsrRdFn_AmdFam10hIbsOpRip,
606 kCpumMsrRdFn_AmdFam10hIbsOpData,
607 kCpumMsrRdFn_AmdFam10hIbsOpData2,
608 kCpumMsrRdFn_AmdFam10hIbsOpData3,
609 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
610 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
611 kCpumMsrRdFn_AmdFam10hIbsCtl,
612 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
613
614 kCpumMsrRdFn_Gim,
615
616 /** End of valid MSR read function indexes. */
617 kCpumMsrRdFn_End
618} CPUMMSRRDFN;
619
620/**
621 * MSR write functions.
622 */
623typedef enum CPUMMSRWRFN
624{
625 /** Invalid zero value. */
626 kCpumMsrWrFn_Invalid = 0,
627 /** Writes are ignored, the fWrGpMask is observed though. */
628 kCpumMsrWrFn_IgnoreWrite,
629 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
630 kCpumMsrWrFn_ReadOnly,
631 /** Alias to the MSR range starting at the MSR given by
632 * CPUMMSRRANGE::uValue. Must be used in pair with
633 * kCpumMsrRdFn_MsrAlias. */
634 kCpumMsrWrFn_MsrAlias,
635
636 kCpumMsrWrFn_Ia32P5McAddr,
637 kCpumMsrWrFn_Ia32P5McType,
638 kCpumMsrWrFn_Ia32TimestampCounter,
639 kCpumMsrWrFn_Ia32ApicBase,
640 kCpumMsrWrFn_Ia32FeatureControl,
641 kCpumMsrWrFn_Ia32BiosSignId,
642 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
643 kCpumMsrWrFn_Ia32SmmMonitorCtl,
644 kCpumMsrWrFn_Ia32PmcN,
645 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
646 kCpumMsrWrFn_Ia32MPerf,
647 kCpumMsrWrFn_Ia32APerf,
648 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
649 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
650 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
651 kCpumMsrWrFn_Ia32MtrrDefType,
652 kCpumMsrWrFn_Ia32Pat,
653 kCpumMsrWrFn_Ia32SysEnterCs,
654 kCpumMsrWrFn_Ia32SysEnterEsp,
655 kCpumMsrWrFn_Ia32SysEnterEip,
656 kCpumMsrWrFn_Ia32McgStatus,
657 kCpumMsrWrFn_Ia32McgCtl,
658 kCpumMsrWrFn_Ia32DebugCtl,
659 kCpumMsrWrFn_Ia32SmrrPhysBase,
660 kCpumMsrWrFn_Ia32SmrrPhysMask,
661 kCpumMsrWrFn_Ia32PlatformDcaCap,
662 kCpumMsrWrFn_Ia32Dca0Cap,
663 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
664 kCpumMsrWrFn_Ia32PerfStatus,
665 kCpumMsrWrFn_Ia32PerfCtl,
666 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
667 kCpumMsrWrFn_Ia32PerfCapabilities,
668 kCpumMsrWrFn_Ia32FixedCtrCtrl,
669 kCpumMsrWrFn_Ia32PerfGlobalStatus,
670 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
671 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
672 kCpumMsrWrFn_Ia32PebsEnable,
673 kCpumMsrWrFn_Ia32ClockModulation,
674 kCpumMsrWrFn_Ia32ThermInterrupt,
675 kCpumMsrWrFn_Ia32ThermStatus,
676 kCpumMsrWrFn_Ia32Therm2Ctl,
677 kCpumMsrWrFn_Ia32MiscEnable,
678 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
679 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
680 kCpumMsrWrFn_Ia32DsArea,
681 kCpumMsrWrFn_Ia32TscDeadline,
682 kCpumMsrWrFn_Ia32X2ApicN,
683 kCpumMsrWrFn_Ia32DebugInterface,
684
685 kCpumMsrWrFn_Amd64Efer,
686 kCpumMsrWrFn_Amd64SyscallTarget,
687 kCpumMsrWrFn_Amd64LongSyscallTarget,
688 kCpumMsrWrFn_Amd64CompSyscallTarget,
689 kCpumMsrWrFn_Amd64SyscallFlagMask,
690 kCpumMsrWrFn_Amd64FsBase,
691 kCpumMsrWrFn_Amd64GsBase,
692 kCpumMsrWrFn_Amd64KernelGsBase,
693 kCpumMsrWrFn_Amd64TscAux,
694 kCpumMsrWrFn_IntelEblCrPowerOn,
695 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
696 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
697 kCpumMsrWrFn_IntelP4EbcFrequencyId,
698 kCpumMsrWrFn_IntelFlexRatio,
699 kCpumMsrWrFn_IntelPkgCStConfigControl,
700 kCpumMsrWrFn_IntelPmgIoCaptureBase,
701 kCpumMsrWrFn_IntelLastBranchFromToN,
702 kCpumMsrWrFn_IntelLastBranchFromN,
703 kCpumMsrWrFn_IntelLastBranchToN,
704 kCpumMsrWrFn_IntelLastBranchTos,
705 kCpumMsrWrFn_IntelBblCrCtl,
706 kCpumMsrWrFn_IntelBblCrCtl3,
707 kCpumMsrWrFn_IntelI7TemperatureTarget,
708 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
709 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
710 kCpumMsrWrFn_IntelP6CrN,
711 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
712 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
713 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
714 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
715 kCpumMsrWrFn_IntelI7TurboRatioLimit,
716 kCpumMsrWrFn_IntelI7LbrSelect,
717 kCpumMsrWrFn_IntelI7SandyErrorControl,
718 kCpumMsrWrFn_IntelI7PowerCtl,
719 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
720 kCpumMsrWrFn_IntelI7PebsLdLat,
721 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
722 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
723 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
724 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
725 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
726 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
727 kCpumMsrWrFn_IntelI7RaplPp0Policy,
728 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
729 kCpumMsrWrFn_IntelI7RaplPp1Policy,
730 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
731 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
732 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
733 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
734 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
735 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
736 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
737 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
738 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
739 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
740 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
741 kCpumMsrWrFn_IntelCore1ExtConfig,
742 kCpumMsrWrFn_IntelCore1DtsCalControl,
743 kCpumMsrWrFn_IntelCore2PeciControl,
744
745 kCpumMsrWrFn_P6LastIntFromIp,
746 kCpumMsrWrFn_P6LastIntToIp,
747
748 kCpumMsrWrFn_AmdFam15hTscRate,
749 kCpumMsrWrFn_AmdFam15hLwpCfg,
750 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
751 kCpumMsrWrFn_AmdFam10hMc4MiscN,
752 kCpumMsrWrFn_AmdK8PerfCtlN,
753 kCpumMsrWrFn_AmdK8PerfCtrN,
754 kCpumMsrWrFn_AmdK8SysCfg,
755 kCpumMsrWrFn_AmdK8HwCr,
756 kCpumMsrWrFn_AmdK8IorrBaseN,
757 kCpumMsrWrFn_AmdK8IorrMaskN,
758 kCpumMsrWrFn_AmdK8TopOfMemN,
759 kCpumMsrWrFn_AmdK8NbCfg1,
760 kCpumMsrWrFn_AmdK8McXcptRedir,
761 kCpumMsrWrFn_AmdK8CpuNameN,
762 kCpumMsrWrFn_AmdK8HwThermalCtrl,
763 kCpumMsrWrFn_AmdK8SwThermalCtrl,
764 kCpumMsrWrFn_AmdK8FidVidControl,
765 kCpumMsrWrFn_AmdK8McCtlMaskN,
766 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
767 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
768 kCpumMsrWrFn_AmdK8IntPendingMessage,
769 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
770 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
771 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
772 kCpumMsrWrFn_AmdFam10hPStateControl,
773 kCpumMsrWrFn_AmdFam10hPStateStatus,
774 kCpumMsrWrFn_AmdFam10hPStateN,
775 kCpumMsrWrFn_AmdFam10hCofVidControl,
776 kCpumMsrWrFn_AmdFam10hCofVidStatus,
777 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
778 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
779 kCpumMsrWrFn_AmdK8SmmBase,
780 kCpumMsrWrFn_AmdK8SmmAddr,
781 kCpumMsrWrFn_AmdK8SmmMask,
782 kCpumMsrWrFn_AmdK8VmCr,
783 kCpumMsrWrFn_AmdK8IgnNe,
784 kCpumMsrWrFn_AmdK8SmmCtl,
785 kCpumMsrWrFn_AmdK8VmHSavePa,
786 kCpumMsrWrFn_AmdFam10hVmLockKey,
787 kCpumMsrWrFn_AmdFam10hSmmLockKey,
788 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
789 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
790 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
791 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
792 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
793 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
794 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
795 kCpumMsrWrFn_AmdK7MicrocodeCtl,
796 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
797 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
798 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
799 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
800 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
801 kCpumMsrWrFn_AmdK8PatchLoader,
802 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
803 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
804 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
805 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
806 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
807 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
808 kCpumMsrWrFn_AmdK7NodeId,
809 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
810 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
811 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
812 kCpumMsrWrFn_AmdK7LoadStoreCfg,
813 kCpumMsrWrFn_AmdK7InstrCacheCfg,
814 kCpumMsrWrFn_AmdK7DataCacheCfg,
815 kCpumMsrWrFn_AmdK7BusUnitCfg,
816 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
817 kCpumMsrWrFn_AmdFam15hFpuCfg,
818 kCpumMsrWrFn_AmdFam15hDecoderCfg,
819 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
820 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
821 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
822 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
823 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
824 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
825 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
826 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
827 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
828 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
829 kCpumMsrWrFn_AmdFam10hIbsOpRip,
830 kCpumMsrWrFn_AmdFam10hIbsOpData,
831 kCpumMsrWrFn_AmdFam10hIbsOpData2,
832 kCpumMsrWrFn_AmdFam10hIbsOpData3,
833 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
834 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
835 kCpumMsrWrFn_AmdFam10hIbsCtl,
836 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
837
838 kCpumMsrWrFn_Gim,
839
840 /** End of valid MSR write function indexes. */
841 kCpumMsrWrFn_End
842} CPUMMSRWRFN;
843
844/**
845 * MSR range.
846 */
847typedef struct CPUMMSRRANGE
848{
849 /** The first MSR. [0] */
850 uint32_t uFirst;
851 /** The last MSR. [4] */
852 uint32_t uLast;
853 /** The read function (CPUMMSRRDFN). [8] */
854 uint16_t enmRdFn;
855 /** The write function (CPUMMSRWRFN). [10] */
856 uint16_t enmWrFn;
857 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
858 * UINT16_MAX if not used by the read and write functions. [12] */
859 uint16_t offCpumCpu;
860 /** Reserved for future hacks. [14] */
861 uint16_t fReserved;
862 /** The init/read value. [16]
863 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
864 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
865 * offset into CPUM. */
866 uint64_t uValue;
867 /** The bits to ignore when writing. [24] */
868 uint64_t fWrIgnMask;
869 /** The bits that will cause a GP(0) when writing. [32]
870 * This is always checked prior to calling the write function. Using
871 * UINT64_MAX effectively marks the MSR as read-only. */
872 uint64_t fWrGpMask;
873 /** The register name, if applicable. [40] */
874 char szName[56];
875
876#ifdef VBOX_WITH_STATISTICS
877 /** The number of reads. */
878 STAMCOUNTER cReads;
879 /** The number of writes. */
880 STAMCOUNTER cWrites;
881 /** The number of times ignored bits were written. */
882 STAMCOUNTER cIgnoredBits;
883 /** The number of GPs generated. */
884 STAMCOUNTER cGps;
885#endif
886} CPUMMSRRANGE;
887#ifndef VBOX_FOR_DTRACE_LIB
888# ifdef VBOX_WITH_STATISTICS
889AssertCompileSize(CPUMMSRRANGE, 128);
890# else
891AssertCompileSize(CPUMMSRRANGE, 96);
892# endif
893#endif
894/** Pointer to an MSR range. */
895typedef CPUMMSRRANGE *PCPUMMSRRANGE;
896/** Pointer to a const MSR range. */
897typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
898
899
900/**
901 * CPU features and quirks.
902 * This is mostly exploded CPUID info.
903 */
904typedef struct CPUMFEATURES
905{
906 /** The CPU vendor (CPUMCPUVENDOR). */
907 uint8_t enmCpuVendor;
908 /** The CPU family. */
909 uint8_t uFamily;
910 /** The CPU model. */
911 uint8_t uModel;
912 /** The CPU stepping. */
913 uint8_t uStepping;
914 /** The microarchitecture. */
915#ifndef VBOX_FOR_DTRACE_LIB
916 CPUMMICROARCH enmMicroarch;
917#else
918 uint32_t enmMicroarch;
919#endif
920 /** The maximum physical address with of the CPU. */
921 uint8_t cMaxPhysAddrWidth;
922 /** Alignment padding. */
923 uint8_t abPadding[1];
924 /** Max size of the extended state (or FPU state if no XSAVE). */
925 uint16_t cbMaxExtendedState;
926
927 /** Supports MSRs. */
928 uint32_t fMsr : 1;
929 /** Supports the page size extension (4/2 MB pages). */
930 uint32_t fPse : 1;
931 /** Supports 36-bit page size extension (4 MB pages can map memory above
932 * 4GB). */
933 uint32_t fPse36 : 1;
934 /** Supports physical address extension (PAE). */
935 uint32_t fPae : 1;
936 /** Page attribute table (PAT) support (page level cache control). */
937 uint32_t fPat : 1;
938 /** Supports the FXSAVE and FXRSTOR instructions. */
939 uint32_t fFxSaveRstor : 1;
940 /** Supports the XSAVE and XRSTOR instructions. */
941 uint32_t fXSaveRstor : 1;
942 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
943 uint32_t fOpSysXSaveRstor : 1;
944 /** Supports MMX. */
945 uint32_t fMmx : 1;
946 /** Supports AMD extensions to MMX instructions. */
947 uint32_t fAmdMmxExts : 1;
948 /** Supports SSE. */
949 uint32_t fSse : 1;
950 /** Supports SSE2. */
951 uint32_t fSse2 : 1;
952 /** Supports SSE3. */
953 uint32_t fSse3 : 1;
954 /** Supports SSSE3. */
955 uint32_t fSsse3 : 1;
956 /** Supports SSE4.1. */
957 uint32_t fSse41 : 1;
958 /** Supports SSE4.2. */
959 uint32_t fSse42 : 1;
960 /** Supports AVX. */
961 uint32_t fAvx : 1;
962 /** Supports AVX2. */
963 uint32_t fAvx2 : 1;
964 /** Supports AVX512 foundation. */
965 uint32_t fAvx512Foundation : 1;
966 /** Supports RDTSC. */
967 uint32_t fTsc : 1;
968 /** Intel SYSENTER/SYSEXIT support */
969 uint32_t fSysEnter : 1;
970 /** First generation APIC. */
971 uint32_t fApic : 1;
972 /** Second generation APIC. */
973 uint32_t fX2Apic : 1;
974 /** Hypervisor present. */
975 uint32_t fHypervisorPresent : 1;
976 /** MWAIT & MONITOR instructions supported. */
977 uint32_t fMonitorMWait : 1;
978 /** MWAIT Extensions present. */
979 uint32_t fMWaitExtensions : 1;
980
981 /** Supports AMD 3DNow instructions. */
982 uint32_t f3DNow : 1;
983 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
984 uint32_t f3DNowPrefetch : 1;
985
986 /** AMD64: Supports long mode. */
987 uint32_t fLongMode : 1;
988 /** AMD64: SYSCALL/SYSRET support. */
989 uint32_t fSysCall : 1;
990 /** AMD64: No-execute page table bit. */
991 uint32_t fNoExecute : 1;
992 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
993 uint32_t fLahfSahf : 1;
994 /** AMD64: Supports RDTSCP. */
995 uint32_t fRdTscP : 1;
996 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
997 uint32_t fMovCr8In32Bit : 1;
998
999 /** Indicates that FPU instruction and data pointers may leak.
1000 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1001 * is only saved and restored if an exception is pending. */
1002 uint32_t fLeakyFxSR : 1;
1003
1004 /** Alignment padding / reserved for future use. */
1005 uint32_t fPadding : 29;
1006 uint32_t auPadding[3];
1007} CPUMFEATURES;
1008#ifndef VBOX_FOR_DTRACE_LIB
1009AssertCompileSize(CPUMFEATURES, 32);
1010#endif
1011/** Pointer to a CPU feature structure. */
1012typedef CPUMFEATURES *PCPUMFEATURES;
1013/** Pointer to a const CPU feature structure. */
1014typedef CPUMFEATURES const *PCCPUMFEATURES;
1015
1016
1017#ifndef VBOX_FOR_DTRACE_LIB
1018
1019/** @name Guest Register Getters.
1020 * @{ */
1021VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1022VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1023VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1024VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1025VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1026VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1027VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1028VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1029VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1030VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1031VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1032VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1033VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1034VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1035VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1036VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1037VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1038VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1039VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1040VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1041VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1042VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1043VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1044VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1045VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1046VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1047VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1048VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1049VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1050VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1051VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1052VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1053VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1054VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1055VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1056VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1057 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1058VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1059VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1060VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1061VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1062VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1063/** @} */
1064
1065/** @name Guest Register Setters.
1066 * @{ */
1067VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1068VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1069VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1070VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1071VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1072VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1073VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1074VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1075VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1076VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1077VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1078VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1079VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1080VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1081VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1082VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue);
1083VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1084VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1085VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1086VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1087VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1088VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1089VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1090VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1091VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1092VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1093VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1094VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1095VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1096VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1097VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1098VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1099VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1100VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1101VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1102VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1103VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1104VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1105VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1106VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1107VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
1108/** @} */
1109
1110
1111/** @name Misc Guest Predicate Functions.
1112 * @{ */
1113
1114VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1115VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1116VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1117VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1118VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1119VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1120VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1121VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1122VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1123VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1124VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1125VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1126VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1127VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1128
1129#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
1130
1131/**
1132 * Tests if the guest is running in real mode or not.
1133 *
1134 * @returns true if in real mode, otherwise false.
1135 * @param pCtx Current CPU context
1136 */
1137DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1138{
1139 return !(pCtx->cr0 & X86_CR0_PE);
1140}
1141
1142/**
1143 * Tests if the guest is running in real or virtual 8086 mode.
1144 *
1145 * @returns @c true if it is, @c false if not.
1146 * @param pCtx Current CPU context
1147 */
1148DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1149{
1150 return !(pCtx->cr0 & X86_CR0_PE)
1151 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1152}
1153
1154/**
1155 * Tests if the guest is running in virtual 8086 mode.
1156 *
1157 * @returns @c true if it is, @c false if not.
1158 * @param pCtx Current CPU context
1159 */
1160DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1161{
1162 return (pCtx->eflags.Bits.u1VM == 1);
1163}
1164
1165/**
1166 * Tests if the guest is running in paged protected or not.
1167 *
1168 * @returns true if in paged protected mode, otherwise false.
1169 * @param pCtx Current CPU context
1170 */
1171DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1172{
1173 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1174}
1175
1176/**
1177 * Tests if the guest is running in long mode or not.
1178 *
1179 * @returns true if in long mode, otherwise false.
1180 * @param pCtx Current CPU context
1181 */
1182DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1183{
1184 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1185}
1186
1187VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1188
1189/**
1190 * Tests if the guest is running in 64 bits mode or not.
1191 *
1192 * @returns true if in 64 bits protected mode, otherwise false.
1193 * @param pCtx Current CPU context
1194 */
1195DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1196{
1197 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1198 return false;
1199 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1200 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1201 return pCtx->cs.Attr.n.u1Long;
1202}
1203
1204/**
1205 * Tests if the guest has paging enabled or not.
1206 *
1207 * @returns true if paging is enabled, otherwise false.
1208 * @param pCtx Current CPU context
1209 */
1210DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1211{
1212 return !!(pCtx->cr0 & X86_CR0_PG);
1213}
1214
1215/**
1216 * Tests if the guest is running in PAE mode or not.
1217 *
1218 * @returns true if in PAE mode, otherwise false.
1219 * @param pCtx Current CPU context
1220 */
1221DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1222{
1223 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1224 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1225 return ( (pCtx->cr4 & X86_CR4_PAE)
1226 && CPUMIsGuestPagingEnabledEx(pCtx)
1227 && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1228}
1229
1230#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
1231
1232/** @} */
1233
1234
1235/** @name Hypervisor Register Getters.
1236 * @{ */
1237VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1238VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1239VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1240VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1241VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1242VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1243#if 0 /* these are not correct. */
1244VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1245VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1246VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1247VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1248#endif
1249/** This register is only saved on fatal traps. */
1250VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1251VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1252/** This register is only saved on fatal traps. */
1253VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1254/** This register is only saved on fatal traps. */
1255VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1256VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1257VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1258VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1259VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1260VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1261VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1262VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1263VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1264VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1265VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1266VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1267VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1268VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1269VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1270VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1271VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1272VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1273VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1274/** @} */
1275
1276/** @name Hypervisor Register Setters.
1277 * @{ */
1278VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1279VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1280VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1281VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1282VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1283VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1284VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1285VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1286VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1287VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1288VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1289VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1290VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1291VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1292VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1293VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1294VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1295VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1296VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1297VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1298VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1299VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1300VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1301/** @} */
1302
1303VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1304VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1305VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1306VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1307VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1308VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1309VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1310VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1311VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1312VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1313
1314/** @name Changed flags.
1315 * These flags are used to keep track of which important register that
1316 * have been changed since last they were reset. The only one allowed
1317 * to clear them is REM!
1318 * @{
1319 */
1320#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1321#define CPUM_CHANGED_CR0 RT_BIT(1)
1322#define CPUM_CHANGED_CR4 RT_BIT(2)
1323#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1324#define CPUM_CHANGED_CR3 RT_BIT(4)
1325#define CPUM_CHANGED_GDTR RT_BIT(5)
1326#define CPUM_CHANGED_IDTR RT_BIT(6)
1327#define CPUM_CHANGED_LDTR RT_BIT(7)
1328#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
1329#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1330#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
1331#define CPUM_CHANGED_CPUID RT_BIT(11)
1332#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1333 | CPUM_CHANGED_CR0 \
1334 | CPUM_CHANGED_CR4 \
1335 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1336 | CPUM_CHANGED_CR3 \
1337 | CPUM_CHANGED_GDTR \
1338 | CPUM_CHANGED_IDTR \
1339 | CPUM_CHANGED_LDTR \
1340 | CPUM_CHANGED_TR \
1341 | CPUM_CHANGED_SYSENTER_MSR \
1342 | CPUM_CHANGED_HIDDEN_SEL_REGS \
1343 | CPUM_CHANGED_CPUID )
1344/** @} */
1345
1346VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1347VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1348VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1349VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
1350VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1351VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1352VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1353VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1354VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1355VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1356VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1357VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1358VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1359VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1360VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1361VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1362VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1363
1364/** @name Typical scalable bus frequency values.
1365 * @{ */
1366/** Special internal value indicating that we don't know the frequency.
1367 * @internal */
1368#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1369#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1370#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1371#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1372#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1373#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1374#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1375#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1376/** @} */
1377
1378
1379#ifdef IN_RING3
1380/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1381 * @{
1382 */
1383
1384VMMR3DECL(int) CPUMR3Init(PVM pVM);
1385VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM);
1386VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1387VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1388VMMR3DECL(int) CPUMR3Term(PVM pVM);
1389VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1390VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1391VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1392VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1393VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1394
1395VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1396VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1397VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1398 uint8_t bModel, uint8_t bStepping);
1399VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1400VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
1401VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1402VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1403VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1404VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1405
1406VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1407
1408# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
1409/** @name APIs for the CPUID raw-mode patch (legacy).
1410 * @{ */
1411VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1412VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1413VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1414VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1415VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1416VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1417VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1418/** @} */
1419# endif
1420
1421/** @} */
1422#endif /* IN_RING3 */
1423
1424#ifdef IN_RC
1425/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1426 * @{
1427 */
1428
1429/**
1430 * Calls a guest trap/interrupt handler directly
1431 *
1432 * Assumes a trap stack frame has already been setup on the guest's stack!
1433 * This function does not return!
1434 *
1435 * @param pRegFrame Original trap/interrupt context
1436 * @param selCS Code selector of handler
1437 * @param pHandler GC virtual address of handler
1438 * @param eflags Callee's EFLAGS
1439 * @param selSS Stack selector for handler
1440 * @param pEsp Stack address for handler
1441 */
1442DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1443 uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1444
1445/**
1446 * Call guest V86 code directly.
1447 *
1448 * This function does not return!
1449 *
1450 * @param pRegFrame Original trap/interrupt context
1451 */
1452DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1453
1454VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1455VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1456#ifdef VBOX_WITH_RAW_RING1
1457VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1458#endif
1459
1460/** @} */
1461#endif /* IN_RC */
1462
1463#ifdef IN_RING0
1464/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1465 * @{
1466 */
1467VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1468VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1469VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1470VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1471VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1472VMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1473VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1474VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1475VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1476
1477VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1478VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1479#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1480VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1481#endif
1482
1483/** @} */
1484#endif /* IN_RING0 */
1485
1486#endif /* !VBOX_FOR_DTRACE_LIB */
1487/** @} */
1488RT_C_DECLS_END
1489
1490
1491#endif
1492
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