VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 61352

Last change on this file since 61352 was 61348, checked in by vboxsync, 9 years ago

CPUM,VMM: Touch the FPU state before doing HM on all platforms which allows us do (VMM_R0_TOUCH_FPU, see Makefile.kmk). No special treatment of win.amd64 (could save a CR0 read, maybe). Cleaned up the fix from this morning.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 62.5 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2015 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpum_h
27#define ___VBox_vmm_cpum_h
28
29#include <iprt/x86.h>
30#include <VBox/types.h>
31#include <VBox/vmm/cpumctx.h>
32#include <VBox/vmm/stam.h>
33#include <VBox/vmm/vmapi.h>
34
35RT_C_DECLS_BEGIN
36
37/** @defgroup grp_cpum The CPU Monitor / Manager API
38 * @ingroup grp_vmm
39 * @{
40 */
41
42/**
43 * CPUID feature to set or clear.
44 */
45typedef enum CPUMCPUIDFEATURE
46{
47 CPUMCPUIDFEATURE_INVALID = 0,
48 /** The APIC feature bit. (Std+Ext) */
49 CPUMCPUIDFEATURE_APIC,
50 /** The sysenter/sysexit feature bit. (Std) */
51 CPUMCPUIDFEATURE_SEP,
52 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
53 CPUMCPUIDFEATURE_SYSCALL,
54 /** The PAE feature bit. (Std+Ext) */
55 CPUMCPUIDFEATURE_PAE,
56 /** The NX feature bit. (Ext) */
57 CPUMCPUIDFEATURE_NX,
58 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
59 CPUMCPUIDFEATURE_LAHF,
60 /** The LONG MODE feature bit. (Ext) */
61 CPUMCPUIDFEATURE_LONG_MODE,
62 /** The PAT feature bit. (Std+Ext) */
63 CPUMCPUIDFEATURE_PAT,
64 /** The x2APIC feature bit. (Std) */
65 CPUMCPUIDFEATURE_X2APIC,
66 /** The RDTSCP feature bit. (Ext) */
67 CPUMCPUIDFEATURE_RDTSCP,
68 /** The Hypervisor Present bit. (Std) */
69 CPUMCPUIDFEATURE_HVP,
70 /** The MWait Extensions bits (Std) */
71 CPUMCPUIDFEATURE_MWAIT_EXTS,
72 /** The CR4.OSXSAVE bit CPUID mirroring, only use from CPUMSetGuestCR4. */
73 CPUMCPUIDFEATURE_OSXSAVE,
74 /** 32bit hackishness. */
75 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
76} CPUMCPUIDFEATURE;
77
78/**
79 * CPU Vendor.
80 */
81typedef enum CPUMCPUVENDOR
82{
83 CPUMCPUVENDOR_INVALID = 0,
84 CPUMCPUVENDOR_INTEL,
85 CPUMCPUVENDOR_AMD,
86 CPUMCPUVENDOR_VIA,
87 CPUMCPUVENDOR_CYRIX,
88 CPUMCPUVENDOR_UNKNOWN,
89 /** 32bit hackishness. */
90 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
91} CPUMCPUVENDOR;
92
93
94/**
95 * X86 and AMD64 CPU microarchitectures and in processor generations.
96 *
97 * @remarks The separation here is sometimes a little bit too finely grained,
98 * and the differences is more like processor generation than micro
99 * arch. This can be useful, so we'll provide functions for getting at
100 * more coarse grained info.
101 */
102typedef enum CPUMMICROARCH
103{
104 kCpumMicroarch_Invalid = 0,
105
106 kCpumMicroarch_Intel_First,
107
108 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
109 kCpumMicroarch_Intel_80186,
110 kCpumMicroarch_Intel_80286,
111 kCpumMicroarch_Intel_80386,
112 kCpumMicroarch_Intel_80486,
113 kCpumMicroarch_Intel_P5,
114
115 kCpumMicroarch_Intel_P6_Core_Atom_First,
116 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
117 kCpumMicroarch_Intel_P6_II,
118 kCpumMicroarch_Intel_P6_III,
119
120 kCpumMicroarch_Intel_P6_M_Banias,
121 kCpumMicroarch_Intel_P6_M_Dothan,
122 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
123
124 kCpumMicroarch_Intel_Core2_First,
125 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
126 kCpumMicroarch_Intel_Core2_Penryn,
127
128 kCpumMicroarch_Intel_Core7_First,
129 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
130 kCpumMicroarch_Intel_Core7_Westmere,
131 kCpumMicroarch_Intel_Core7_SandyBridge,
132 kCpumMicroarch_Intel_Core7_IvyBridge,
133 kCpumMicroarch_Intel_Core7_Haswell,
134 kCpumMicroarch_Intel_Core7_Broadwell,
135 kCpumMicroarch_Intel_Core7_Skylake,
136 kCpumMicroarch_Intel_Core7_Cannonlake,
137 kCpumMicroarch_Intel_Core7_End,
138
139 kCpumMicroarch_Intel_Atom_First,
140 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
141 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
142 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
143 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
144 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
145 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
146 kCpumMicroarch_Intel_Atom_Unknown,
147 kCpumMicroarch_Intel_Atom_End,
148
149 kCpumMicroarch_Intel_P6_Core_Atom_End,
150
151 kCpumMicroarch_Intel_NB_First,
152 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
153 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
154 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
155 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
156 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
157 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
158 kCpumMicroarch_Intel_NB_Unknown,
159 kCpumMicroarch_Intel_NB_End,
160
161 kCpumMicroarch_Intel_Unknown,
162 kCpumMicroarch_Intel_End,
163
164 kCpumMicroarch_AMD_First,
165 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
166 kCpumMicroarch_AMD_Am386,
167 kCpumMicroarch_AMD_Am486,
168 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
169 kCpumMicroarch_AMD_K5,
170 kCpumMicroarch_AMD_K6,
171
172 kCpumMicroarch_AMD_K7_First,
173 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
174 kCpumMicroarch_AMD_K7_Spitfire,
175 kCpumMicroarch_AMD_K7_Thunderbird,
176 kCpumMicroarch_AMD_K7_Morgan,
177 kCpumMicroarch_AMD_K7_Thoroughbred,
178 kCpumMicroarch_AMD_K7_Barton,
179 kCpumMicroarch_AMD_K7_Unknown,
180 kCpumMicroarch_AMD_K7_End,
181
182 kCpumMicroarch_AMD_K8_First,
183 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
184 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
185 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
186 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
187 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
188 kCpumMicroarch_AMD_K8_End,
189
190 kCpumMicroarch_AMD_K10,
191 kCpumMicroarch_AMD_K10_Lion,
192 kCpumMicroarch_AMD_K10_Llano,
193 kCpumMicroarch_AMD_Bobcat,
194 kCpumMicroarch_AMD_Jaguar,
195
196 kCpumMicroarch_AMD_15h_First,
197 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
198 kCpumMicroarch_AMD_15h_Piledriver,
199 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
200 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
201 kCpumMicroarch_AMD_15h_Unknown,
202 kCpumMicroarch_AMD_15h_End,
203
204 kCpumMicroarch_AMD_16h_First,
205 kCpumMicroarch_AMD_16h_End,
206
207 kCpumMicroarch_AMD_Unknown,
208 kCpumMicroarch_AMD_End,
209
210 kCpumMicroarch_VIA_First,
211 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
212 kCpumMicroarch_Centaur_C2,
213 kCpumMicroarch_Centaur_C3,
214 kCpumMicroarch_VIA_C3_M2,
215 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
216 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
217 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
218 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
219 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
220 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
221 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
222 kCpumMicroarch_VIA_Isaiah,
223 kCpumMicroarch_VIA_Unknown,
224 kCpumMicroarch_VIA_End,
225
226 kCpumMicroarch_Cyrix_First,
227 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
228 kCpumMicroarch_Cyrix_M1,
229 kCpumMicroarch_Cyrix_MediaGX,
230 kCpumMicroarch_Cyrix_MediaGXm,
231 kCpumMicroarch_Cyrix_M2,
232 kCpumMicroarch_Cyrix_Unknown,
233 kCpumMicroarch_Cyrix_End,
234
235 kCpumMicroarch_NEC_First,
236 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
237 kCpumMicroarch_NEC_V30,
238 kCpumMicroarch_NEC_End,
239
240 kCpumMicroarch_Unknown,
241
242 kCpumMicroarch_32BitHack = 0x7fffffff
243} CPUMMICROARCH;
244
245
246/** Predicate macro for catching netburst CPUs. */
247#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
248 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
249
250/** Predicate macro for catching Core7 CPUs. */
251#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
252 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
253
254/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
255#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
256 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
257
258/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
259#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
260 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
261
262/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
263#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
264
265/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
266#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
267
268/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
269#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
270
271/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
272#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
273
274/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
275 * decendants). */
276#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
277 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
278
279/** Predicate macro for catching AMD Family 16H CPUs. */
280#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
281 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
282
283
284
285/**
286 * CPUID leaf.
287 *
288 * @remarks This structure is used by the patch manager and is therefore
289 * more or less set in stone.
290 */
291typedef struct CPUMCPUIDLEAF
292{
293 /** The leaf number. */
294 uint32_t uLeaf;
295 /** The sub-leaf number. */
296 uint32_t uSubLeaf;
297 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
298 uint32_t fSubLeafMask;
299
300 /** The EAX value. */
301 uint32_t uEax;
302 /** The EBX value. */
303 uint32_t uEbx;
304 /** The ECX value. */
305 uint32_t uEcx;
306 /** The EDX value. */
307 uint32_t uEdx;
308
309 /** Flags. */
310 uint32_t fFlags;
311} CPUMCPUIDLEAF;
312#ifndef VBOX_FOR_DTRACE_LIB
313AssertCompileSize(CPUMCPUIDLEAF, 32);
314#endif
315/** Pointer to a CPUID leaf. */
316typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
317/** Pointer to a const CPUID leaf. */
318typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
319
320/** @name CPUMCPUIDLEAF::fFlags
321 * @{ */
322/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
323 * and EDX containing the extended APIC ID. */
324#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
325/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
326#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
327/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
328#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
329/** Mask of the valid flags. */
330#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0x7)
331/** @} */
332
333/**
334 * Method used to deal with unknown CPUID leaves.
335 * @remarks Used in patch code.
336 */
337typedef enum CPUMUNKNOWNCPUID
338{
339 /** Invalid zero value. */
340 CPUMUNKNOWNCPUID_INVALID = 0,
341 /** Use given default values (DefCpuId). */
342 CPUMUNKNOWNCPUID_DEFAULTS,
343 /** Return the last standard leaf.
344 * Intel Sandy Bridge has been observed doing this. */
345 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
346 /** Return the last standard leaf, with ecx observed.
347 * Intel Sandy Bridge has been observed doing this. */
348 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
349 /** The register values are passed thru unmodified. */
350 CPUMUNKNOWNCPUID_PASSTHRU,
351 /** End of valid value. */
352 CPUMUNKNOWNCPUID_END,
353 /** Ensure 32-bit type. */
354 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
355} CPUMUNKNOWNCPUID;
356/** Pointer to unknown CPUID leaf method. */
357typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
358
359
360/**
361 * MSR read functions.
362 */
363typedef enum CPUMMSRRDFN
364{
365 /** Invalid zero value. */
366 kCpumMsrRdFn_Invalid = 0,
367 /** Return the CPUMMSRRANGE::uValue. */
368 kCpumMsrRdFn_FixedValue,
369 /** Alias to the MSR range starting at the MSR given by
370 * CPUMMSRRANGE::uValue. Must be used in pair with
371 * kCpumMsrWrFn_MsrAlias. */
372 kCpumMsrRdFn_MsrAlias,
373 /** Write only register, GP all read attempts. */
374 kCpumMsrRdFn_WriteOnly,
375
376 kCpumMsrRdFn_Ia32P5McAddr,
377 kCpumMsrRdFn_Ia32P5McType,
378 kCpumMsrRdFn_Ia32TimestampCounter,
379 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
380 kCpumMsrRdFn_Ia32ApicBase,
381 kCpumMsrRdFn_Ia32FeatureControl,
382 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
383 kCpumMsrRdFn_Ia32SmmMonitorCtl,
384 kCpumMsrRdFn_Ia32PmcN,
385 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
386 kCpumMsrRdFn_Ia32MPerf,
387 kCpumMsrRdFn_Ia32APerf,
388 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
389 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
390 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
391 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
392 kCpumMsrRdFn_Ia32MtrrDefType,
393 kCpumMsrRdFn_Ia32Pat,
394 kCpumMsrRdFn_Ia32SysEnterCs,
395 kCpumMsrRdFn_Ia32SysEnterEsp,
396 kCpumMsrRdFn_Ia32SysEnterEip,
397 kCpumMsrRdFn_Ia32McgCap,
398 kCpumMsrRdFn_Ia32McgStatus,
399 kCpumMsrRdFn_Ia32McgCtl,
400 kCpumMsrRdFn_Ia32DebugCtl,
401 kCpumMsrRdFn_Ia32SmrrPhysBase,
402 kCpumMsrRdFn_Ia32SmrrPhysMask,
403 kCpumMsrRdFn_Ia32PlatformDcaCap,
404 kCpumMsrRdFn_Ia32CpuDcaCap,
405 kCpumMsrRdFn_Ia32Dca0Cap,
406 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
407 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
408 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
409 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
410 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
411 kCpumMsrRdFn_Ia32FixedCtrCtrl,
412 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
413 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
414 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
415 kCpumMsrRdFn_Ia32PebsEnable,
416 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
417 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
418 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
419 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
420 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
421 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
422 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
423 kCpumMsrRdFn_Ia32DsArea,
424 kCpumMsrRdFn_Ia32TscDeadline,
425 kCpumMsrRdFn_Ia32X2ApicN,
426 kCpumMsrRdFn_Ia32DebugInterface,
427 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
428 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
429 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
430 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
431 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
432 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
433 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
434 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
435 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
436 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
437 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
438 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
439 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
440 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
441 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
442 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
443 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
444 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
445
446 kCpumMsrRdFn_Amd64Efer,
447 kCpumMsrRdFn_Amd64SyscallTarget,
448 kCpumMsrRdFn_Amd64LongSyscallTarget,
449 kCpumMsrRdFn_Amd64CompSyscallTarget,
450 kCpumMsrRdFn_Amd64SyscallFlagMask,
451 kCpumMsrRdFn_Amd64FsBase,
452 kCpumMsrRdFn_Amd64GsBase,
453 kCpumMsrRdFn_Amd64KernelGsBase,
454 kCpumMsrRdFn_Amd64TscAux,
455
456 kCpumMsrRdFn_IntelEblCrPowerOn,
457 kCpumMsrRdFn_IntelI7CoreThreadCount,
458 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
459 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
460 kCpumMsrRdFn_IntelP4EbcFrequencyId,
461 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
462 kCpumMsrRdFn_IntelPlatformInfo,
463 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
464 kCpumMsrRdFn_IntelPkgCStConfigControl,
465 kCpumMsrRdFn_IntelPmgIoCaptureBase,
466 kCpumMsrRdFn_IntelLastBranchFromToN,
467 kCpumMsrRdFn_IntelLastBranchFromN,
468 kCpumMsrRdFn_IntelLastBranchToN,
469 kCpumMsrRdFn_IntelLastBranchTos,
470 kCpumMsrRdFn_IntelBblCrCtl,
471 kCpumMsrRdFn_IntelBblCrCtl3,
472 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
473 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
474 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
475 kCpumMsrRdFn_IntelP6CrN,
476 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
477 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
478 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
479 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
480 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
481 kCpumMsrRdFn_IntelI7LbrSelect,
482 kCpumMsrRdFn_IntelI7SandyErrorControl,
483 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
484 kCpumMsrRdFn_IntelI7PowerCtl,
485 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
486 kCpumMsrRdFn_IntelI7PebsLdLat,
487 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
488 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
489 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
490 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
491 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
492 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
493 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
494 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
495 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
496 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
497 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
498 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
499 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
500 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
501 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
502 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
503 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
504 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
505 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
506 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
507 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
508 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
509 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
510 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
511 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
512 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
513 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
514 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
515 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
516 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
517 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
518 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
519 kCpumMsrRdFn_IntelI7UncCBoxConfig,
520 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
521 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
522 kCpumMsrRdFn_IntelI7SmiCount,
523 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
524 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
525 kCpumMsrRdFn_IntelCore1ExtConfig,
526 kCpumMsrRdFn_IntelCore1DtsCalControl,
527 kCpumMsrRdFn_IntelCore2PeciControl,
528 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
529
530 kCpumMsrRdFn_P6LastBranchFromIp,
531 kCpumMsrRdFn_P6LastBranchToIp,
532 kCpumMsrRdFn_P6LastIntFromIp,
533 kCpumMsrRdFn_P6LastIntToIp,
534
535 kCpumMsrRdFn_AmdFam15hTscRate,
536 kCpumMsrRdFn_AmdFam15hLwpCfg,
537 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
538 kCpumMsrRdFn_AmdFam10hMc4MiscN,
539 kCpumMsrRdFn_AmdK8PerfCtlN,
540 kCpumMsrRdFn_AmdK8PerfCtrN,
541 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
542 kCpumMsrRdFn_AmdK8HwCr,
543 kCpumMsrRdFn_AmdK8IorrBaseN,
544 kCpumMsrRdFn_AmdK8IorrMaskN,
545 kCpumMsrRdFn_AmdK8TopOfMemN,
546 kCpumMsrRdFn_AmdK8NbCfg1,
547 kCpumMsrRdFn_AmdK8McXcptRedir,
548 kCpumMsrRdFn_AmdK8CpuNameN,
549 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
550 kCpumMsrRdFn_AmdK8SwThermalCtrl,
551 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
552 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
553 kCpumMsrRdFn_AmdK8McCtlMaskN,
554 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
555 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
556 kCpumMsrRdFn_AmdK8IntPendingMessage,
557 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
558 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
559 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
560 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
561 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
562 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
563 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
564 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
565 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
566 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
567 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
568 kCpumMsrRdFn_AmdK8SmmBase,
569 kCpumMsrRdFn_AmdK8SmmAddr,
570 kCpumMsrRdFn_AmdK8SmmMask,
571 kCpumMsrRdFn_AmdK8VmCr,
572 kCpumMsrRdFn_AmdK8IgnNe,
573 kCpumMsrRdFn_AmdK8SmmCtl,
574 kCpumMsrRdFn_AmdK8VmHSavePa,
575 kCpumMsrRdFn_AmdFam10hVmLockKey,
576 kCpumMsrRdFn_AmdFam10hSmmLockKey,
577 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
578 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
579 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
580 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
581 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
582 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
583 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
584 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
585 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
586 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
587 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
588 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
589 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
590 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
591 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
592 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
593 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
594 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
595 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
596 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
597 kCpumMsrRdFn_AmdK7NodeId,
598 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
599 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
600 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
601 kCpumMsrRdFn_AmdK7LoadStoreCfg,
602 kCpumMsrRdFn_AmdK7InstrCacheCfg,
603 kCpumMsrRdFn_AmdK7DataCacheCfg,
604 kCpumMsrRdFn_AmdK7BusUnitCfg,
605 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
606 kCpumMsrRdFn_AmdFam15hFpuCfg,
607 kCpumMsrRdFn_AmdFam15hDecoderCfg,
608 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
609 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
610 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
611 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
612 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
613 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
614 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
615 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
616 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
617 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
618 kCpumMsrRdFn_AmdFam10hIbsOpRip,
619 kCpumMsrRdFn_AmdFam10hIbsOpData,
620 kCpumMsrRdFn_AmdFam10hIbsOpData2,
621 kCpumMsrRdFn_AmdFam10hIbsOpData3,
622 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
623 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
624 kCpumMsrRdFn_AmdFam10hIbsCtl,
625 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
626
627 kCpumMsrRdFn_Gim,
628
629 /** End of valid MSR read function indexes. */
630 kCpumMsrRdFn_End
631} CPUMMSRRDFN;
632
633/**
634 * MSR write functions.
635 */
636typedef enum CPUMMSRWRFN
637{
638 /** Invalid zero value. */
639 kCpumMsrWrFn_Invalid = 0,
640 /** Writes are ignored, the fWrGpMask is observed though. */
641 kCpumMsrWrFn_IgnoreWrite,
642 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
643 kCpumMsrWrFn_ReadOnly,
644 /** Alias to the MSR range starting at the MSR given by
645 * CPUMMSRRANGE::uValue. Must be used in pair with
646 * kCpumMsrRdFn_MsrAlias. */
647 kCpumMsrWrFn_MsrAlias,
648
649 kCpumMsrWrFn_Ia32P5McAddr,
650 kCpumMsrWrFn_Ia32P5McType,
651 kCpumMsrWrFn_Ia32TimestampCounter,
652 kCpumMsrWrFn_Ia32ApicBase,
653 kCpumMsrWrFn_Ia32FeatureControl,
654 kCpumMsrWrFn_Ia32BiosSignId,
655 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
656 kCpumMsrWrFn_Ia32SmmMonitorCtl,
657 kCpumMsrWrFn_Ia32PmcN,
658 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
659 kCpumMsrWrFn_Ia32MPerf,
660 kCpumMsrWrFn_Ia32APerf,
661 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
662 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
663 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
664 kCpumMsrWrFn_Ia32MtrrDefType,
665 kCpumMsrWrFn_Ia32Pat,
666 kCpumMsrWrFn_Ia32SysEnterCs,
667 kCpumMsrWrFn_Ia32SysEnterEsp,
668 kCpumMsrWrFn_Ia32SysEnterEip,
669 kCpumMsrWrFn_Ia32McgStatus,
670 kCpumMsrWrFn_Ia32McgCtl,
671 kCpumMsrWrFn_Ia32DebugCtl,
672 kCpumMsrWrFn_Ia32SmrrPhysBase,
673 kCpumMsrWrFn_Ia32SmrrPhysMask,
674 kCpumMsrWrFn_Ia32PlatformDcaCap,
675 kCpumMsrWrFn_Ia32Dca0Cap,
676 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
677 kCpumMsrWrFn_Ia32PerfStatus,
678 kCpumMsrWrFn_Ia32PerfCtl,
679 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
680 kCpumMsrWrFn_Ia32PerfCapabilities,
681 kCpumMsrWrFn_Ia32FixedCtrCtrl,
682 kCpumMsrWrFn_Ia32PerfGlobalStatus,
683 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
684 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
685 kCpumMsrWrFn_Ia32PebsEnable,
686 kCpumMsrWrFn_Ia32ClockModulation,
687 kCpumMsrWrFn_Ia32ThermInterrupt,
688 kCpumMsrWrFn_Ia32ThermStatus,
689 kCpumMsrWrFn_Ia32Therm2Ctl,
690 kCpumMsrWrFn_Ia32MiscEnable,
691 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
692 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
693 kCpumMsrWrFn_Ia32DsArea,
694 kCpumMsrWrFn_Ia32TscDeadline,
695 kCpumMsrWrFn_Ia32X2ApicN,
696 kCpumMsrWrFn_Ia32DebugInterface,
697
698 kCpumMsrWrFn_Amd64Efer,
699 kCpumMsrWrFn_Amd64SyscallTarget,
700 kCpumMsrWrFn_Amd64LongSyscallTarget,
701 kCpumMsrWrFn_Amd64CompSyscallTarget,
702 kCpumMsrWrFn_Amd64SyscallFlagMask,
703 kCpumMsrWrFn_Amd64FsBase,
704 kCpumMsrWrFn_Amd64GsBase,
705 kCpumMsrWrFn_Amd64KernelGsBase,
706 kCpumMsrWrFn_Amd64TscAux,
707 kCpumMsrWrFn_IntelEblCrPowerOn,
708 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
709 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
710 kCpumMsrWrFn_IntelP4EbcFrequencyId,
711 kCpumMsrWrFn_IntelFlexRatio,
712 kCpumMsrWrFn_IntelPkgCStConfigControl,
713 kCpumMsrWrFn_IntelPmgIoCaptureBase,
714 kCpumMsrWrFn_IntelLastBranchFromToN,
715 kCpumMsrWrFn_IntelLastBranchFromN,
716 kCpumMsrWrFn_IntelLastBranchToN,
717 kCpumMsrWrFn_IntelLastBranchTos,
718 kCpumMsrWrFn_IntelBblCrCtl,
719 kCpumMsrWrFn_IntelBblCrCtl3,
720 kCpumMsrWrFn_IntelI7TemperatureTarget,
721 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
722 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
723 kCpumMsrWrFn_IntelP6CrN,
724 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
725 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
726 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
727 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
728 kCpumMsrWrFn_IntelI7TurboRatioLimit,
729 kCpumMsrWrFn_IntelI7LbrSelect,
730 kCpumMsrWrFn_IntelI7SandyErrorControl,
731 kCpumMsrWrFn_IntelI7PowerCtl,
732 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
733 kCpumMsrWrFn_IntelI7PebsLdLat,
734 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
735 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
736 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
737 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
738 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
739 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
740 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
741 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
742 kCpumMsrWrFn_IntelI7RaplPp0Policy,
743 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
744 kCpumMsrWrFn_IntelI7RaplPp1Policy,
745 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
746 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
747 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
748 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
749 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
750 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
751 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
752 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
753 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
754 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
755 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
756 kCpumMsrWrFn_IntelCore1ExtConfig,
757 kCpumMsrWrFn_IntelCore1DtsCalControl,
758 kCpumMsrWrFn_IntelCore2PeciControl,
759
760 kCpumMsrWrFn_P6LastIntFromIp,
761 kCpumMsrWrFn_P6LastIntToIp,
762
763 kCpumMsrWrFn_AmdFam15hTscRate,
764 kCpumMsrWrFn_AmdFam15hLwpCfg,
765 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
766 kCpumMsrWrFn_AmdFam10hMc4MiscN,
767 kCpumMsrWrFn_AmdK8PerfCtlN,
768 kCpumMsrWrFn_AmdK8PerfCtrN,
769 kCpumMsrWrFn_AmdK8SysCfg,
770 kCpumMsrWrFn_AmdK8HwCr,
771 kCpumMsrWrFn_AmdK8IorrBaseN,
772 kCpumMsrWrFn_AmdK8IorrMaskN,
773 kCpumMsrWrFn_AmdK8TopOfMemN,
774 kCpumMsrWrFn_AmdK8NbCfg1,
775 kCpumMsrWrFn_AmdK8McXcptRedir,
776 kCpumMsrWrFn_AmdK8CpuNameN,
777 kCpumMsrWrFn_AmdK8HwThermalCtrl,
778 kCpumMsrWrFn_AmdK8SwThermalCtrl,
779 kCpumMsrWrFn_AmdK8FidVidControl,
780 kCpumMsrWrFn_AmdK8McCtlMaskN,
781 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
782 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
783 kCpumMsrWrFn_AmdK8IntPendingMessage,
784 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
785 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
786 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
787 kCpumMsrWrFn_AmdFam10hPStateControl,
788 kCpumMsrWrFn_AmdFam10hPStateStatus,
789 kCpumMsrWrFn_AmdFam10hPStateN,
790 kCpumMsrWrFn_AmdFam10hCofVidControl,
791 kCpumMsrWrFn_AmdFam10hCofVidStatus,
792 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
793 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
794 kCpumMsrWrFn_AmdK8SmmBase,
795 kCpumMsrWrFn_AmdK8SmmAddr,
796 kCpumMsrWrFn_AmdK8SmmMask,
797 kCpumMsrWrFn_AmdK8VmCr,
798 kCpumMsrWrFn_AmdK8IgnNe,
799 kCpumMsrWrFn_AmdK8SmmCtl,
800 kCpumMsrWrFn_AmdK8VmHSavePa,
801 kCpumMsrWrFn_AmdFam10hVmLockKey,
802 kCpumMsrWrFn_AmdFam10hSmmLockKey,
803 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
804 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
805 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
806 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
807 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
808 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
809 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
810 kCpumMsrWrFn_AmdK7MicrocodeCtl,
811 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
812 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
813 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
814 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
815 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
816 kCpumMsrWrFn_AmdK8PatchLoader,
817 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
818 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
819 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
820 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
821 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
822 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
823 kCpumMsrWrFn_AmdK7NodeId,
824 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
825 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
826 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
827 kCpumMsrWrFn_AmdK7LoadStoreCfg,
828 kCpumMsrWrFn_AmdK7InstrCacheCfg,
829 kCpumMsrWrFn_AmdK7DataCacheCfg,
830 kCpumMsrWrFn_AmdK7BusUnitCfg,
831 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
832 kCpumMsrWrFn_AmdFam15hFpuCfg,
833 kCpumMsrWrFn_AmdFam15hDecoderCfg,
834 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
835 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
836 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
837 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
838 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
839 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
840 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
841 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
842 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
843 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
844 kCpumMsrWrFn_AmdFam10hIbsOpRip,
845 kCpumMsrWrFn_AmdFam10hIbsOpData,
846 kCpumMsrWrFn_AmdFam10hIbsOpData2,
847 kCpumMsrWrFn_AmdFam10hIbsOpData3,
848 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
849 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
850 kCpumMsrWrFn_AmdFam10hIbsCtl,
851 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
852
853 kCpumMsrWrFn_Gim,
854
855 /** End of valid MSR write function indexes. */
856 kCpumMsrWrFn_End
857} CPUMMSRWRFN;
858
859/**
860 * MSR range.
861 */
862typedef struct CPUMMSRRANGE
863{
864 /** The first MSR. [0] */
865 uint32_t uFirst;
866 /** The last MSR. [4] */
867 uint32_t uLast;
868 /** The read function (CPUMMSRRDFN). [8] */
869 uint16_t enmRdFn;
870 /** The write function (CPUMMSRWRFN). [10] */
871 uint16_t enmWrFn;
872 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
873 * UINT16_MAX if not used by the read and write functions. [12] */
874 uint16_t offCpumCpu;
875 /** Reserved for future hacks. [14] */
876 uint16_t fReserved;
877 /** The init/read value. [16]
878 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
879 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
880 * offset into CPUM. */
881 uint64_t uValue;
882 /** The bits to ignore when writing. [24] */
883 uint64_t fWrIgnMask;
884 /** The bits that will cause a GP(0) when writing. [32]
885 * This is always checked prior to calling the write function. Using
886 * UINT64_MAX effectively marks the MSR as read-only. */
887 uint64_t fWrGpMask;
888 /** The register name, if applicable. [40] */
889 char szName[56];
890
891#ifdef VBOX_WITH_STATISTICS
892 /** The number of reads. */
893 STAMCOUNTER cReads;
894 /** The number of writes. */
895 STAMCOUNTER cWrites;
896 /** The number of times ignored bits were written. */
897 STAMCOUNTER cIgnoredBits;
898 /** The number of GPs generated. */
899 STAMCOUNTER cGps;
900#endif
901} CPUMMSRRANGE;
902#ifndef VBOX_FOR_DTRACE_LIB
903# ifdef VBOX_WITH_STATISTICS
904AssertCompileSize(CPUMMSRRANGE, 128);
905# else
906AssertCompileSize(CPUMMSRRANGE, 96);
907# endif
908#endif
909/** Pointer to an MSR range. */
910typedef CPUMMSRRANGE *PCPUMMSRRANGE;
911/** Pointer to a const MSR range. */
912typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
913
914
915/**
916 * CPU features and quirks.
917 * This is mostly exploded CPUID info.
918 */
919typedef struct CPUMFEATURES
920{
921 /** The CPU vendor (CPUMCPUVENDOR). */
922 uint8_t enmCpuVendor;
923 /** The CPU family. */
924 uint8_t uFamily;
925 /** The CPU model. */
926 uint8_t uModel;
927 /** The CPU stepping. */
928 uint8_t uStepping;
929 /** The microarchitecture. */
930#ifndef VBOX_FOR_DTRACE_LIB
931 CPUMMICROARCH enmMicroarch;
932#else
933 uint32_t enmMicroarch;
934#endif
935 /** The maximum physical address with of the CPU. */
936 uint8_t cMaxPhysAddrWidth;
937 /** Alignment padding. */
938 uint8_t abPadding[1];
939 /** Max size of the extended state (or FPU state if no XSAVE). */
940 uint16_t cbMaxExtendedState;
941
942 /** Supports MSRs. */
943 uint32_t fMsr : 1;
944 /** Supports the page size extension (4/2 MB pages). */
945 uint32_t fPse : 1;
946 /** Supports 36-bit page size extension (4 MB pages can map memory above
947 * 4GB). */
948 uint32_t fPse36 : 1;
949 /** Supports physical address extension (PAE). */
950 uint32_t fPae : 1;
951 /** Page attribute table (PAT) support (page level cache control). */
952 uint32_t fPat : 1;
953 /** Supports the FXSAVE and FXRSTOR instructions. */
954 uint32_t fFxSaveRstor : 1;
955 /** Supports the XSAVE and XRSTOR instructions. */
956 uint32_t fXSaveRstor : 1;
957 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
958 uint32_t fOpSysXSaveRstor : 1;
959 /** Supports MMX. */
960 uint32_t fMmx : 1;
961 /** Supports AMD extensions to MMX instructions. */
962 uint32_t fAmdMmxExts : 1;
963 /** Supports SSE. */
964 uint32_t fSse : 1;
965 /** Supports SSE2. */
966 uint32_t fSse2 : 1;
967 /** Supports SSE3. */
968 uint32_t fSse3 : 1;
969 /** Supports SSSE3. */
970 uint32_t fSsse3 : 1;
971 /** Supports SSE4.1. */
972 uint32_t fSse41 : 1;
973 /** Supports SSE4.2. */
974 uint32_t fSse42 : 1;
975 /** Supports AVX. */
976 uint32_t fAvx : 1;
977 /** Supports AVX2. */
978 uint32_t fAvx2 : 1;
979 /** Supports AVX512 foundation. */
980 uint32_t fAvx512Foundation : 1;
981 /** Supports RDTSC. */
982 uint32_t fTsc : 1;
983 /** Intel SYSENTER/SYSEXIT support */
984 uint32_t fSysEnter : 1;
985 /** First generation APIC. */
986 uint32_t fApic : 1;
987 /** Second generation APIC. */
988 uint32_t fX2Apic : 1;
989 /** Hypervisor present. */
990 uint32_t fHypervisorPresent : 1;
991 /** MWAIT & MONITOR instructions supported. */
992 uint32_t fMonitorMWait : 1;
993 /** MWAIT Extensions present. */
994 uint32_t fMWaitExtensions : 1;
995
996 /** Supports AMD 3DNow instructions. */
997 uint32_t f3DNow : 1;
998 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
999 uint32_t f3DNowPrefetch : 1;
1000
1001 /** AMD64: Supports long mode. */
1002 uint32_t fLongMode : 1;
1003 /** AMD64: SYSCALL/SYSRET support. */
1004 uint32_t fSysCall : 1;
1005 /** AMD64: No-execute page table bit. */
1006 uint32_t fNoExecute : 1;
1007 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1008 uint32_t fLahfSahf : 1;
1009 /** AMD64: Supports RDTSCP. */
1010 uint32_t fRdTscP : 1;
1011 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1012 uint32_t fMovCr8In32Bit : 1;
1013
1014 /** Indicates that FPU instruction and data pointers may leak.
1015 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1016 * is only saved and restored if an exception is pending. */
1017 uint32_t fLeakyFxSR : 1;
1018
1019 /** Alignment padding / reserved for future use. */
1020 uint32_t fPadding : 29;
1021 uint32_t auPadding[3];
1022} CPUMFEATURES;
1023#ifndef VBOX_FOR_DTRACE_LIB
1024AssertCompileSize(CPUMFEATURES, 32);
1025#endif
1026/** Pointer to a CPU feature structure. */
1027typedef CPUMFEATURES *PCPUMFEATURES;
1028/** Pointer to a const CPU feature structure. */
1029typedef CPUMFEATURES const *PCCPUMFEATURES;
1030
1031
1032#ifndef VBOX_FOR_DTRACE_LIB
1033
1034/** @name Guest Register Getters.
1035 * @{ */
1036VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1037VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1038VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1039VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1040VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1041VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1042VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1043VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1044VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1045VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1046VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1047VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1048VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1049VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1050VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1051VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1052VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1053VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1054VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1055VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1056VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1057VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1058VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1059VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1060VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1061VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1062VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1063VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1064VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1065VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1066VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1067VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1068VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1069VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1070VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1071VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1072 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1073VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1074VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1075VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1076VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1077VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1078/** @} */
1079
1080/** @name Guest Register Setters.
1081 * @{ */
1082VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1083VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1084VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1085VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1086VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1087VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1088VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1089VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1090VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1091VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1092VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1093VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1094VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1095VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1096VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1097VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue);
1098VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1099VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1100VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1101VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1102VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1103VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1104VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1105VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1106VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1107VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1108VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1109VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1110VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1111VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1112VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1113VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1114VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1115VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1116VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1117VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1118VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1119VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1120VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1121VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1122VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
1123/** @} */
1124
1125
1126/** @name Misc Guest Predicate Functions.
1127 * @{ */
1128
1129VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1130VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1131VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1132VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1133VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1134VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1135VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1136VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1137VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1138VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1139VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1140VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1141VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1142VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1143
1144#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
1145
1146/**
1147 * Tests if the guest is running in real mode or not.
1148 *
1149 * @returns true if in real mode, otherwise false.
1150 * @param pCtx Current CPU context
1151 */
1152DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1153{
1154 return !(pCtx->cr0 & X86_CR0_PE);
1155}
1156
1157/**
1158 * Tests if the guest is running in real or virtual 8086 mode.
1159 *
1160 * @returns @c true if it is, @c false if not.
1161 * @param pCtx Current CPU context
1162 */
1163DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1164{
1165 return !(pCtx->cr0 & X86_CR0_PE)
1166 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1167}
1168
1169/**
1170 * Tests if the guest is running in virtual 8086 mode.
1171 *
1172 * @returns @c true if it is, @c false if not.
1173 * @param pCtx Current CPU context
1174 */
1175DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1176{
1177 return (pCtx->eflags.Bits.u1VM == 1);
1178}
1179
1180/**
1181 * Tests if the guest is running in paged protected or not.
1182 *
1183 * @returns true if in paged protected mode, otherwise false.
1184 * @param pCtx Current CPU context
1185 */
1186DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1187{
1188 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1189}
1190
1191/**
1192 * Tests if the guest is running in long mode or not.
1193 *
1194 * @returns true if in long mode, otherwise false.
1195 * @param pCtx Current CPU context
1196 */
1197DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1198{
1199 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1200}
1201
1202VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1203
1204/**
1205 * Tests if the guest is running in 64 bits mode or not.
1206 *
1207 * @returns true if in 64 bits protected mode, otherwise false.
1208 * @param pCtx Current CPU context
1209 */
1210DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1211{
1212 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1213 return false;
1214 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1215 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1216 return pCtx->cs.Attr.n.u1Long;
1217}
1218
1219/**
1220 * Tests if the guest has paging enabled or not.
1221 *
1222 * @returns true if paging is enabled, otherwise false.
1223 * @param pCtx Current CPU context
1224 */
1225DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1226{
1227 return !!(pCtx->cr0 & X86_CR0_PG);
1228}
1229
1230/**
1231 * Tests if the guest is running in PAE mode or not.
1232 *
1233 * @returns true if in PAE mode, otherwise false.
1234 * @param pCtx Current CPU context
1235 */
1236DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1237{
1238 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1239 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1240 return ( (pCtx->cr4 & X86_CR4_PAE)
1241 && CPUMIsGuestPagingEnabledEx(pCtx)
1242 && !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1243}
1244
1245#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
1246
1247/** @} */
1248
1249
1250/** @name Hypervisor Register Getters.
1251 * @{ */
1252VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1253VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1254VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1255VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1256VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1257VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1258#if 0 /* these are not correct. */
1259VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1260VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1261VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1262VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1263#endif
1264/** This register is only saved on fatal traps. */
1265VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1266VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1267/** This register is only saved on fatal traps. */
1268VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1269/** This register is only saved on fatal traps. */
1270VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1271VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1272VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1273VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1274VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1275VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1276VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1277VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1278VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1279VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1280VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1281VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1282VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1283VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1284VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1285VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1286VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1287VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1288VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1289/** @} */
1290
1291/** @name Hypervisor Register Setters.
1292 * @{ */
1293VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1294VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1295VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1296VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1297VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1298VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1299VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1300VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1301VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1302VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1303VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1304VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1305VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1306VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1307VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1308VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1309VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1310VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1311VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1312VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1313VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1314VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1315VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1316/** @} */
1317
1318VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1319VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1320VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1321VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1322VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1323VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1324VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1325VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1326VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1327VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1328
1329/** @name Changed flags.
1330 * These flags are used to keep track of which important register that
1331 * have been changed since last they were reset. The only one allowed
1332 * to clear them is REM!
1333 * @{
1334 */
1335#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1336#define CPUM_CHANGED_CR0 RT_BIT(1)
1337#define CPUM_CHANGED_CR4 RT_BIT(2)
1338#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1339#define CPUM_CHANGED_CR3 RT_BIT(4)
1340#define CPUM_CHANGED_GDTR RT_BIT(5)
1341#define CPUM_CHANGED_IDTR RT_BIT(6)
1342#define CPUM_CHANGED_LDTR RT_BIT(7)
1343#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
1344#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1345#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
1346#define CPUM_CHANGED_CPUID RT_BIT(11)
1347#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1348 | CPUM_CHANGED_CR0 \
1349 | CPUM_CHANGED_CR4 \
1350 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1351 | CPUM_CHANGED_CR3 \
1352 | CPUM_CHANGED_GDTR \
1353 | CPUM_CHANGED_IDTR \
1354 | CPUM_CHANGED_LDTR \
1355 | CPUM_CHANGED_TR \
1356 | CPUM_CHANGED_SYSENTER_MSR \
1357 | CPUM_CHANGED_HIDDEN_SEL_REGS \
1358 | CPUM_CHANGED_CPUID )
1359/** @} */
1360
1361VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1362VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1363VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1364VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
1365VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1366VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1367VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1368VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
1369VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
1370VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1371VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1372VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1373VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1374VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1375VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1376VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1377VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1378VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1379VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1380
1381/** @name Typical scalable bus frequency values.
1382 * @{ */
1383/** Special internal value indicating that we don't know the frequency.
1384 * @internal */
1385#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1386#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1387#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1388#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1389#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1390#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1391#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1392#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1393/** @} */
1394
1395
1396#ifdef IN_RING3
1397/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1398 * @{
1399 */
1400
1401VMMR3DECL(int) CPUMR3Init(PVM pVM);
1402VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1403VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1404VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1405VMMR3DECL(int) CPUMR3Term(PVM pVM);
1406VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1407VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1408VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1409VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1410VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1411
1412VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1413VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1414VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1415 uint8_t bModel, uint8_t bStepping);
1416VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1417VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
1418VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1419VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1420VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1421VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1422
1423VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1424
1425# if defined(VBOX_WITH_RAW_MODE) || defined(DOXYGEN_RUNNING)
1426/** @name APIs for the CPUID raw-mode patch (legacy).
1427 * @{ */
1428VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1429VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1430VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1431VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1432VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1433VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1434VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1435/** @} */
1436# endif
1437
1438/** @} */
1439#endif /* IN_RING3 */
1440
1441#ifdef IN_RC
1442/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1443 * @{
1444 */
1445
1446/**
1447 * Calls a guest trap/interrupt handler directly
1448 *
1449 * Assumes a trap stack frame has already been setup on the guest's stack!
1450 * This function does not return!
1451 *
1452 * @param pRegFrame Original trap/interrupt context
1453 * @param selCS Code selector of handler
1454 * @param pHandler GC virtual address of handler
1455 * @param eflags Callee's EFLAGS
1456 * @param selSS Stack selector for handler
1457 * @param pEsp Stack address for handler
1458 */
1459DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1460 uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1461
1462/**
1463 * Call guest V86 code directly.
1464 *
1465 * This function does not return!
1466 *
1467 * @param pRegFrame Original trap/interrupt context
1468 */
1469DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1470
1471VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1472VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1473#ifdef VBOX_WITH_RAW_RING1
1474VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1475#endif
1476VMMRCDECL(void) CPUMRCProcessForceFlag(PVMCPU pVCpu);
1477
1478/** @} */
1479#endif /* IN_RC */
1480
1481#ifdef IN_RING0
1482/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1483 * @{
1484 */
1485VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1486VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1487VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1488DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPU pVCpu);
1489DECLASM(void) CPUMR0TouchHostFpu(void);
1490VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu);
1491VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu);
1492VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu);
1493VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1494VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1495VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1496
1497VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1498VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1499#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1500VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1501#endif
1502
1503/** @} */
1504#endif /* IN_RING0 */
1505
1506/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
1507 * @{
1508 */
1509VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPU pVCpu);
1510VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPU pVCpu);
1511VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPU pVCpu);
1512VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPU pVCpu);
1513/** @} */
1514
1515
1516#endif /* !VBOX_FOR_DTRACE_LIB */
1517/** @} */
1518RT_C_DECLS_END
1519
1520
1521#endif
1522
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