cpum.h@ 70266

Last change on this file since 70266 was 70254, checked in by vboxsync, 7 years ago
VMM: Match the AMD specs exactly whenever possible for SVM specific feature, renamed to plural "Decode assists".
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpum_h
27	#define ___VBox_vmm_cpum_h
28
29	#include <iprt/x86.h>
30	#include <VBox/types.h>
31	#include <VBox/vmm/cpumctx.h>
32	#include <VBox/vmm/stam.h>
33	#include <VBox/vmm/vmapi.h>
34
35	RT_C_DECLS_BEGIN
36
37	/** @defgroup grp_cpum The CPU Monitor / Manager API
38	* @ingroup grp_vmm
39	* @{
40	*/
41
42	/**
43	* CPUID feature to set or clear.
44	*/
45	typedef enum CPUMCPUIDFEATURE
46	{
47	CPUMCPUIDFEATURE_INVALID = 0,
48	/** The APIC feature bit. (Std+Ext)
49	* Note! There is a per-cpu flag for masking this CPUID feature bit when the
50	* APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
51	* at VM construction time like all the others. This didn't used to be
52	* that way, this is new with 5.1. */
53	CPUMCPUIDFEATURE_APIC,
54	/** The sysenter/sysexit feature bit. (Std) */
55	CPUMCPUIDFEATURE_SEP,
56	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
57	CPUMCPUIDFEATURE_SYSCALL,
58	/** The PAE feature bit. (Std+Ext) */
59	CPUMCPUIDFEATURE_PAE,
60	/** The NX feature bit. (Ext) */
61	CPUMCPUIDFEATURE_NX,
62	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
63	CPUMCPUIDFEATURE_LAHF,
64	/** The LONG MODE feature bit. (Ext) */
65	CPUMCPUIDFEATURE_LONG_MODE,
66	/** The PAT feature bit. (Std+Ext) */
67	CPUMCPUIDFEATURE_PAT,
68	/** The x2APIC feature bit. (Std) */
69	CPUMCPUIDFEATURE_X2APIC,
70	/** The RDTSCP feature bit. (Ext) */
71	CPUMCPUIDFEATURE_RDTSCP,
72	/** The Hypervisor Present bit. (Std) */
73	CPUMCPUIDFEATURE_HVP,
74	/** The MWait Extensions bits (Std) */
75	CPUMCPUIDFEATURE_MWAIT_EXTS,
76	/** 32bit hackishness. */
77	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
78	} CPUMCPUIDFEATURE;
79
80	/**
81	* CPU Vendor.
82	*/
83	typedef enum CPUMCPUVENDOR
84	{
85	CPUMCPUVENDOR_INVALID = 0,
86	CPUMCPUVENDOR_INTEL,
87	CPUMCPUVENDOR_AMD,
88	CPUMCPUVENDOR_VIA,
89	CPUMCPUVENDOR_CYRIX,
90	CPUMCPUVENDOR_UNKNOWN,
91	/** 32bit hackishness. */
92	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
93	} CPUMCPUVENDOR;
94
95
96	/**
97	* X86 and AMD64 CPU microarchitectures and in processor generations.
98	*
99	* @remarks The separation here is sometimes a little bit too finely grained,
100	* and the differences is more like processor generation than micro
101	* arch. This can be useful, so we'll provide functions for getting at
102	* more coarse grained info.
103	*/
104	typedef enum CPUMMICROARCH
105	{
106	kCpumMicroarch_Invalid = 0,
107
108	kCpumMicroarch_Intel_First,
109
110	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
111	kCpumMicroarch_Intel_80186,
112	kCpumMicroarch_Intel_80286,
113	kCpumMicroarch_Intel_80386,
114	kCpumMicroarch_Intel_80486,
115	kCpumMicroarch_Intel_P5,
116
117	kCpumMicroarch_Intel_P6_Core_Atom_First,
118	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
119	kCpumMicroarch_Intel_P6_II,
120	kCpumMicroarch_Intel_P6_III,
121
122	kCpumMicroarch_Intel_P6_M_Banias,
123	kCpumMicroarch_Intel_P6_M_Dothan,
124	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
125
126	kCpumMicroarch_Intel_Core2_First,
127	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /*< 65nm, Merom/Conroe/Kentsfield/Tigerton /
128	kCpumMicroarch_Intel_Core2_Penryn, /*< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown /
129	kCpumMicroarch_Intel_Core2_End,
130
131	kCpumMicroarch_Intel_Core7_First,
132	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
133	kCpumMicroarch_Intel_Core7_Westmere,
134	kCpumMicroarch_Intel_Core7_SandyBridge,
135	kCpumMicroarch_Intel_Core7_IvyBridge,
136	kCpumMicroarch_Intel_Core7_Haswell,
137	kCpumMicroarch_Intel_Core7_Broadwell,
138	kCpumMicroarch_Intel_Core7_Skylake,
139	kCpumMicroarch_Intel_Core7_Cannonlake,
140	kCpumMicroarch_Intel_Core7_End,
141
142	kCpumMicroarch_Intel_Atom_First,
143	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
144	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
145	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
146	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
147	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
148	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
149	kCpumMicroarch_Intel_Atom_Unknown,
150	kCpumMicroarch_Intel_Atom_End,
151
152	kCpumMicroarch_Intel_P6_Core_Atom_End,
153
154	kCpumMicroarch_Intel_NB_First,
155	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
156	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
157	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
158	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
159	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
160	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
161	kCpumMicroarch_Intel_NB_Unknown,
162	kCpumMicroarch_Intel_NB_End,
163
164	kCpumMicroarch_Intel_Unknown,
165	kCpumMicroarch_Intel_End,
166
167	kCpumMicroarch_AMD_First,
168	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
169	kCpumMicroarch_AMD_Am386,
170	kCpumMicroarch_AMD_Am486,
171	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
172	kCpumMicroarch_AMD_K5,
173	kCpumMicroarch_AMD_K6,
174
175	kCpumMicroarch_AMD_K7_First,
176	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
177	kCpumMicroarch_AMD_K7_Spitfire,
178	kCpumMicroarch_AMD_K7_Thunderbird,
179	kCpumMicroarch_AMD_K7_Morgan,
180	kCpumMicroarch_AMD_K7_Thoroughbred,
181	kCpumMicroarch_AMD_K7_Barton,
182	kCpumMicroarch_AMD_K7_Unknown,
183	kCpumMicroarch_AMD_K7_End,
184
185	kCpumMicroarch_AMD_K8_First,
186	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
187	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
188	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
189	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
190	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
191	kCpumMicroarch_AMD_K8_End,
192
193	kCpumMicroarch_AMD_K10,
194	kCpumMicroarch_AMD_K10_Lion,
195	kCpumMicroarch_AMD_K10_Llano,
196	kCpumMicroarch_AMD_Bobcat,
197	kCpumMicroarch_AMD_Jaguar,
198
199	kCpumMicroarch_AMD_15h_First,
200	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
201	kCpumMicroarch_AMD_15h_Piledriver,
202	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
203	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
204	kCpumMicroarch_AMD_15h_Unknown,
205	kCpumMicroarch_AMD_15h_End,
206
207	kCpumMicroarch_AMD_16h_First,
208	kCpumMicroarch_AMD_16h_End,
209
210	kCpumMicroarch_AMD_Zen_First,
211	kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
212	kCpumMicroarch_AMD_Zen_End,
213
214	kCpumMicroarch_AMD_Unknown,
215	kCpumMicroarch_AMD_End,
216
217	kCpumMicroarch_VIA_First,
218	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
219	kCpumMicroarch_Centaur_C2,
220	kCpumMicroarch_Centaur_C3,
221	kCpumMicroarch_VIA_C3_M2,
222	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
223	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
224	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
225	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
226	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
227	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
228	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
229	kCpumMicroarch_VIA_Isaiah,
230	kCpumMicroarch_VIA_Unknown,
231	kCpumMicroarch_VIA_End,
232
233	kCpumMicroarch_Cyrix_First,
234	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
235	kCpumMicroarch_Cyrix_M1,
236	kCpumMicroarch_Cyrix_MediaGX,
237	kCpumMicroarch_Cyrix_MediaGXm,
238	kCpumMicroarch_Cyrix_M2,
239	kCpumMicroarch_Cyrix_Unknown,
240	kCpumMicroarch_Cyrix_End,
241
242	kCpumMicroarch_NEC_First,
243	kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
244	kCpumMicroarch_NEC_V30,
245	kCpumMicroarch_NEC_End,
246
247	kCpumMicroarch_Unknown,
248
249	kCpumMicroarch_32BitHack = 0x7fffffff
250	} CPUMMICROARCH;
251
252
253	/** Predicate macro for catching netburst CPUs. */
254	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
255	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
256
257	/** Predicate macro for catching Core7 CPUs. */
258	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
259	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
260
261	/** Predicate macro for catching Core 2 CPUs. */
262	#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
263	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
264
265	/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
266	#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
267	((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
268
269	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
270	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
271	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
272
273	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
274	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
275
276	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
277	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
278
279	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
280	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
281
282	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
283	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
284
285	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
286	* decendants). */
287	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
288	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
289
290	/** Predicate macro for catching AMD Family 16H CPUs. */
291	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
292	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
293
294
295
296	/**
297	* CPUID leaf.
298	*
299	* @remarks This structure is used by the patch manager and is therefore
300	* more or less set in stone.
301	*/
302	typedef struct CPUMCPUIDLEAF
303	{
304	/** The leaf number. */
305	uint32_t uLeaf;
306	/** The sub-leaf number. */
307	uint32_t uSubLeaf;
308	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
309	uint32_t fSubLeafMask;
310
311	/** The EAX value. */
312	uint32_t uEax;
313	/** The EBX value. */
314	uint32_t uEbx;
315	/** The ECX value. */
316	uint32_t uEcx;
317	/** The EDX value. */
318	uint32_t uEdx;
319
320	/** Flags. */
321	uint32_t fFlags;
322	} CPUMCPUIDLEAF;
323	#ifndef VBOX_FOR_DTRACE_LIB
324	AssertCompileSize(CPUMCPUIDLEAF, 32);
325	#endif
326	/** Pointer to a CPUID leaf. */
327	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
328	/** Pointer to a const CPUID leaf. */
329	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
330
331	/** @name CPUMCPUIDLEAF::fFlags
332	* @{ */
333	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
334	* and EDX containing the extended APIC ID. */
335	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
336	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
337	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
338	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
339	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
340	/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
341	#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
342	/** Mask of the valid flags. */
343	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
344	/** @} */
345
346	/**
347	* Method used to deal with unknown CPUID leaves.
348	* @remarks Used in patch code.
349	*/
350	typedef enum CPUMUNKNOWNCPUID
351	{
352	/** Invalid zero value. */
353	CPUMUNKNOWNCPUID_INVALID = 0,
354	/** Use given default values (DefCpuId). */
355	CPUMUNKNOWNCPUID_DEFAULTS,
356	/** Return the last standard leaf.
357	* Intel Sandy Bridge has been observed doing this. */
358	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
359	/** Return the last standard leaf, with ecx observed.
360	* Intel Sandy Bridge has been observed doing this. */
361	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
362	/** The register values are passed thru unmodified. */
363	CPUMUNKNOWNCPUID_PASSTHRU,
364	/** End of valid value. */
365	CPUMUNKNOWNCPUID_END,
366	/** Ensure 32-bit type. */
367	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
368	} CPUMUNKNOWNCPUID;
369	/** Pointer to unknown CPUID leaf method. */
370	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
371
372
373	/**
374	* MSR read functions.
375	*/
376	typedef enum CPUMMSRRDFN
377	{
378	/** Invalid zero value. */
379	kCpumMsrRdFn_Invalid = 0,
380	/** Return the CPUMMSRRANGE::uValue. */
381	kCpumMsrRdFn_FixedValue,
382	/** Alias to the MSR range starting at the MSR given by
383	* CPUMMSRRANGE::uValue. Must be used in pair with
384	* kCpumMsrWrFn_MsrAlias. */
385	kCpumMsrRdFn_MsrAlias,
386	/** Write only register, GP all read attempts. */
387	kCpumMsrRdFn_WriteOnly,
388
389	kCpumMsrRdFn_Ia32P5McAddr,
390	kCpumMsrRdFn_Ia32P5McType,
391	kCpumMsrRdFn_Ia32TimestampCounter,
392	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
393	kCpumMsrRdFn_Ia32ApicBase,
394	kCpumMsrRdFn_Ia32FeatureControl,
395	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
396	kCpumMsrRdFn_Ia32SmmMonitorCtl,
397	kCpumMsrRdFn_Ia32PmcN,
398	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
399	kCpumMsrRdFn_Ia32MPerf,
400	kCpumMsrRdFn_Ia32APerf,
401	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
402	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
403	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
404	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
405	kCpumMsrRdFn_Ia32MtrrDefType,
406	kCpumMsrRdFn_Ia32Pat,
407	kCpumMsrRdFn_Ia32SysEnterCs,
408	kCpumMsrRdFn_Ia32SysEnterEsp,
409	kCpumMsrRdFn_Ia32SysEnterEip,
410	kCpumMsrRdFn_Ia32McgCap,
411	kCpumMsrRdFn_Ia32McgStatus,
412	kCpumMsrRdFn_Ia32McgCtl,
413	kCpumMsrRdFn_Ia32DebugCtl,
414	kCpumMsrRdFn_Ia32SmrrPhysBase,
415	kCpumMsrRdFn_Ia32SmrrPhysMask,
416	kCpumMsrRdFn_Ia32PlatformDcaCap,
417	kCpumMsrRdFn_Ia32CpuDcaCap,
418	kCpumMsrRdFn_Ia32Dca0Cap,
419	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
420	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
421	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
422	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
423	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
424	kCpumMsrRdFn_Ia32FixedCtrCtrl,
425	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
426	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
427	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
428	kCpumMsrRdFn_Ia32PebsEnable,
429	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
430	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
431	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
432	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
433	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
434	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
435	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
436	kCpumMsrRdFn_Ia32DsArea,
437	kCpumMsrRdFn_Ia32TscDeadline,
438	kCpumMsrRdFn_Ia32X2ApicN,
439	kCpumMsrRdFn_Ia32DebugInterface,
440	kCpumMsrRdFn_Ia32VmxBase, /*< Takes real value as reference. /
441	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
442	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
443	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
444	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
445	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
446	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
447	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
448	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
449	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
450	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
451	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
452	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
453	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
454	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
455	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
456	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
457	kCpumMsrRdFn_Ia32VmxVmFunc, /*< Takes real value as reference. /
458
459	kCpumMsrRdFn_Amd64Efer,
460	kCpumMsrRdFn_Amd64SyscallTarget,
461	kCpumMsrRdFn_Amd64LongSyscallTarget,
462	kCpumMsrRdFn_Amd64CompSyscallTarget,
463	kCpumMsrRdFn_Amd64SyscallFlagMask,
464	kCpumMsrRdFn_Amd64FsBase,
465	kCpumMsrRdFn_Amd64GsBase,
466	kCpumMsrRdFn_Amd64KernelGsBase,
467	kCpumMsrRdFn_Amd64TscAux,
468
469	kCpumMsrRdFn_IntelEblCrPowerOn,
470	kCpumMsrRdFn_IntelI7CoreThreadCount,
471	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
472	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
473	kCpumMsrRdFn_IntelP4EbcFrequencyId,
474	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
475	kCpumMsrRdFn_IntelPlatformInfo,
476	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
477	kCpumMsrRdFn_IntelPkgCStConfigControl,
478	kCpumMsrRdFn_IntelPmgIoCaptureBase,
479	kCpumMsrRdFn_IntelLastBranchFromToN,
480	kCpumMsrRdFn_IntelLastBranchFromN,
481	kCpumMsrRdFn_IntelLastBranchToN,
482	kCpumMsrRdFn_IntelLastBranchTos,
483	kCpumMsrRdFn_IntelBblCrCtl,
484	kCpumMsrRdFn_IntelBblCrCtl3,
485	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
486	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
487	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
488	kCpumMsrRdFn_IntelP6CrN,
489	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
490	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
491	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
492	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
493	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
494	kCpumMsrRdFn_IntelI7LbrSelect,
495	kCpumMsrRdFn_IntelI7SandyErrorControl,
496	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
497	kCpumMsrRdFn_IntelI7PowerCtl,
498	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
499	kCpumMsrRdFn_IntelI7PebsLdLat,
500	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
501	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
502	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
503	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
504	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
505	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
506	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
507	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
508	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
509	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
510	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
511	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
512	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
513	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
514	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
515	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
516	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
517	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
518	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
519	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
520	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
521	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
522	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
523	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
524	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
525	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
526	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
527	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
528	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
529	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
530	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
531	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
532	kCpumMsrRdFn_IntelI7UncCBoxConfig,
533	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
534	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
535	kCpumMsrRdFn_IntelI7SmiCount,
536	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
537	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
538	kCpumMsrRdFn_IntelCore1ExtConfig,
539	kCpumMsrRdFn_IntelCore1DtsCalControl,
540	kCpumMsrRdFn_IntelCore2PeciControl,
541	kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
542
543	kCpumMsrRdFn_P6LastBranchFromIp,
544	kCpumMsrRdFn_P6LastBranchToIp,
545	kCpumMsrRdFn_P6LastIntFromIp,
546	kCpumMsrRdFn_P6LastIntToIp,
547
548	kCpumMsrRdFn_AmdFam15hTscRate,
549	kCpumMsrRdFn_AmdFam15hLwpCfg,
550	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
551	kCpumMsrRdFn_AmdFam10hMc4MiscN,
552	kCpumMsrRdFn_AmdK8PerfCtlN,
553	kCpumMsrRdFn_AmdK8PerfCtrN,
554	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
555	kCpumMsrRdFn_AmdK8HwCr,
556	kCpumMsrRdFn_AmdK8IorrBaseN,
557	kCpumMsrRdFn_AmdK8IorrMaskN,
558	kCpumMsrRdFn_AmdK8TopOfMemN,
559	kCpumMsrRdFn_AmdK8NbCfg1,
560	kCpumMsrRdFn_AmdK8McXcptRedir,
561	kCpumMsrRdFn_AmdK8CpuNameN,
562	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
563	kCpumMsrRdFn_AmdK8SwThermalCtrl,
564	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
565	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
566	kCpumMsrRdFn_AmdK8McCtlMaskN,
567	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
568	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
569	kCpumMsrRdFn_AmdK8IntPendingMessage,
570	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
571	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
572	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
573	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
574	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
575	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
576	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
577	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
578	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
579	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
580	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
581	kCpumMsrRdFn_AmdK8SmmBase,
582	kCpumMsrRdFn_AmdK8SmmAddr,
583	kCpumMsrRdFn_AmdK8SmmMask,
584	kCpumMsrRdFn_AmdK8VmCr,
585	kCpumMsrRdFn_AmdK8IgnNe,
586	kCpumMsrRdFn_AmdK8SmmCtl,
587	kCpumMsrRdFn_AmdK8VmHSavePa,
588	kCpumMsrRdFn_AmdFam10hVmLockKey,
589	kCpumMsrRdFn_AmdFam10hSmmLockKey,
590	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
591	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
592	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
593	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
594	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
595	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
596	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
597	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
598	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
599	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
600	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
601	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
602	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
603	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
604	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
605	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
606	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
607	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
608	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
609	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
610	kCpumMsrRdFn_AmdK7NodeId,
611	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
612	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
613	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
614	kCpumMsrRdFn_AmdK7LoadStoreCfg,
615	kCpumMsrRdFn_AmdK7InstrCacheCfg,
616	kCpumMsrRdFn_AmdK7DataCacheCfg,
617	kCpumMsrRdFn_AmdK7BusUnitCfg,
618	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
619	kCpumMsrRdFn_AmdFam15hFpuCfg,
620	kCpumMsrRdFn_AmdFam15hDecoderCfg,
621	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
622	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
623	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
624	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
625	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
626	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
627	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
628	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
629	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
630	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
631	kCpumMsrRdFn_AmdFam10hIbsOpRip,
632	kCpumMsrRdFn_AmdFam10hIbsOpData,
633	kCpumMsrRdFn_AmdFam10hIbsOpData2,
634	kCpumMsrRdFn_AmdFam10hIbsOpData3,
635	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
636	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
637	kCpumMsrRdFn_AmdFam10hIbsCtl,
638	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
639
640	kCpumMsrRdFn_Gim,
641
642	/** End of valid MSR read function indexes. */
643	kCpumMsrRdFn_End
644	} CPUMMSRRDFN;
645
646	/**
647	* MSR write functions.
648	*/
649	typedef enum CPUMMSRWRFN
650	{
651	/** Invalid zero value. */
652	kCpumMsrWrFn_Invalid = 0,
653	/** Writes are ignored, the fWrGpMask is observed though. */
654	kCpumMsrWrFn_IgnoreWrite,
655	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
656	kCpumMsrWrFn_ReadOnly,
657	/** Alias to the MSR range starting at the MSR given by
658	* CPUMMSRRANGE::uValue. Must be used in pair with
659	* kCpumMsrRdFn_MsrAlias. */
660	kCpumMsrWrFn_MsrAlias,
661
662	kCpumMsrWrFn_Ia32P5McAddr,
663	kCpumMsrWrFn_Ia32P5McType,
664	kCpumMsrWrFn_Ia32TimestampCounter,
665	kCpumMsrWrFn_Ia32ApicBase,
666	kCpumMsrWrFn_Ia32FeatureControl,
667	kCpumMsrWrFn_Ia32BiosSignId,
668	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
669	kCpumMsrWrFn_Ia32SmmMonitorCtl,
670	kCpumMsrWrFn_Ia32PmcN,
671	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
672	kCpumMsrWrFn_Ia32MPerf,
673	kCpumMsrWrFn_Ia32APerf,
674	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
675	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
676	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
677	kCpumMsrWrFn_Ia32MtrrDefType,
678	kCpumMsrWrFn_Ia32Pat,
679	kCpumMsrWrFn_Ia32SysEnterCs,
680	kCpumMsrWrFn_Ia32SysEnterEsp,
681	kCpumMsrWrFn_Ia32SysEnterEip,
682	kCpumMsrWrFn_Ia32McgStatus,
683	kCpumMsrWrFn_Ia32McgCtl,
684	kCpumMsrWrFn_Ia32DebugCtl,
685	kCpumMsrWrFn_Ia32SmrrPhysBase,
686	kCpumMsrWrFn_Ia32SmrrPhysMask,
687	kCpumMsrWrFn_Ia32PlatformDcaCap,
688	kCpumMsrWrFn_Ia32Dca0Cap,
689	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
690	kCpumMsrWrFn_Ia32PerfStatus,
691	kCpumMsrWrFn_Ia32PerfCtl,
692	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
693	kCpumMsrWrFn_Ia32PerfCapabilities,
694	kCpumMsrWrFn_Ia32FixedCtrCtrl,
695	kCpumMsrWrFn_Ia32PerfGlobalStatus,
696	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
697	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
698	kCpumMsrWrFn_Ia32PebsEnable,
699	kCpumMsrWrFn_Ia32ClockModulation,
700	kCpumMsrWrFn_Ia32ThermInterrupt,
701	kCpumMsrWrFn_Ia32ThermStatus,
702	kCpumMsrWrFn_Ia32Therm2Ctl,
703	kCpumMsrWrFn_Ia32MiscEnable,
704	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
705	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
706	kCpumMsrWrFn_Ia32DsArea,
707	kCpumMsrWrFn_Ia32TscDeadline,
708	kCpumMsrWrFn_Ia32X2ApicN,
709	kCpumMsrWrFn_Ia32DebugInterface,
710
711	kCpumMsrWrFn_Amd64Efer,
712	kCpumMsrWrFn_Amd64SyscallTarget,
713	kCpumMsrWrFn_Amd64LongSyscallTarget,
714	kCpumMsrWrFn_Amd64CompSyscallTarget,
715	kCpumMsrWrFn_Amd64SyscallFlagMask,
716	kCpumMsrWrFn_Amd64FsBase,
717	kCpumMsrWrFn_Amd64GsBase,
718	kCpumMsrWrFn_Amd64KernelGsBase,
719	kCpumMsrWrFn_Amd64TscAux,
720	kCpumMsrWrFn_IntelEblCrPowerOn,
721	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
722	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
723	kCpumMsrWrFn_IntelP4EbcFrequencyId,
724	kCpumMsrWrFn_IntelFlexRatio,
725	kCpumMsrWrFn_IntelPkgCStConfigControl,
726	kCpumMsrWrFn_IntelPmgIoCaptureBase,
727	kCpumMsrWrFn_IntelLastBranchFromToN,
728	kCpumMsrWrFn_IntelLastBranchFromN,
729	kCpumMsrWrFn_IntelLastBranchToN,
730	kCpumMsrWrFn_IntelLastBranchTos,
731	kCpumMsrWrFn_IntelBblCrCtl,
732	kCpumMsrWrFn_IntelBblCrCtl3,
733	kCpumMsrWrFn_IntelI7TemperatureTarget,
734	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
735	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
736	kCpumMsrWrFn_IntelP6CrN,
737	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
738	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
739	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
740	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
741	kCpumMsrWrFn_IntelI7TurboRatioLimit,
742	kCpumMsrWrFn_IntelI7LbrSelect,
743	kCpumMsrWrFn_IntelI7SandyErrorControl,
744	kCpumMsrWrFn_IntelI7PowerCtl,
745	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
746	kCpumMsrWrFn_IntelI7PebsLdLat,
747	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
748	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
749	kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /*< R/O but found writable bits on a Silvermont CPU here. /
750	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
751	kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /*< R/O but found writable bits on a Silvermont CPU here. /
752	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
753	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
754	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
755	kCpumMsrWrFn_IntelI7RaplPp0Policy,
756	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
757	kCpumMsrWrFn_IntelI7RaplPp1Policy,
758	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
759	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
760	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
761	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
762	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
763	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
764	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
765	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
766	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
767	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
768	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
769	kCpumMsrWrFn_IntelCore1ExtConfig,
770	kCpumMsrWrFn_IntelCore1DtsCalControl,
771	kCpumMsrWrFn_IntelCore2PeciControl,
772
773	kCpumMsrWrFn_P6LastIntFromIp,
774	kCpumMsrWrFn_P6LastIntToIp,
775
776	kCpumMsrWrFn_AmdFam15hTscRate,
777	kCpumMsrWrFn_AmdFam15hLwpCfg,
778	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
779	kCpumMsrWrFn_AmdFam10hMc4MiscN,
780	kCpumMsrWrFn_AmdK8PerfCtlN,
781	kCpumMsrWrFn_AmdK8PerfCtrN,
782	kCpumMsrWrFn_AmdK8SysCfg,
783	kCpumMsrWrFn_AmdK8HwCr,
784	kCpumMsrWrFn_AmdK8IorrBaseN,
785	kCpumMsrWrFn_AmdK8IorrMaskN,
786	kCpumMsrWrFn_AmdK8TopOfMemN,
787	kCpumMsrWrFn_AmdK8NbCfg1,
788	kCpumMsrWrFn_AmdK8McXcptRedir,
789	kCpumMsrWrFn_AmdK8CpuNameN,
790	kCpumMsrWrFn_AmdK8HwThermalCtrl,
791	kCpumMsrWrFn_AmdK8SwThermalCtrl,
792	kCpumMsrWrFn_AmdK8FidVidControl,
793	kCpumMsrWrFn_AmdK8McCtlMaskN,
794	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
795	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
796	kCpumMsrWrFn_AmdK8IntPendingMessage,
797	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
798	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
799	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
800	kCpumMsrWrFn_AmdFam10hPStateControl,
801	kCpumMsrWrFn_AmdFam10hPStateStatus,
802	kCpumMsrWrFn_AmdFam10hPStateN,
803	kCpumMsrWrFn_AmdFam10hCofVidControl,
804	kCpumMsrWrFn_AmdFam10hCofVidStatus,
805	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
806	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
807	kCpumMsrWrFn_AmdK8SmmBase,
808	kCpumMsrWrFn_AmdK8SmmAddr,
809	kCpumMsrWrFn_AmdK8SmmMask,
810	kCpumMsrWrFn_AmdK8VmCr,
811	kCpumMsrWrFn_AmdK8IgnNe,
812	kCpumMsrWrFn_AmdK8SmmCtl,
813	kCpumMsrWrFn_AmdK8VmHSavePa,
814	kCpumMsrWrFn_AmdFam10hVmLockKey,
815	kCpumMsrWrFn_AmdFam10hSmmLockKey,
816	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
817	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
818	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
819	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
820	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
821	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
822	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
823	kCpumMsrWrFn_AmdK7MicrocodeCtl,
824	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
825	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
826	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
827	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
828	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
829	kCpumMsrWrFn_AmdK8PatchLoader,
830	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
831	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
832	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
833	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
834	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
835	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
836	kCpumMsrWrFn_AmdK7NodeId,
837	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
838	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
839	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
840	kCpumMsrWrFn_AmdK7LoadStoreCfg,
841	kCpumMsrWrFn_AmdK7InstrCacheCfg,
842	kCpumMsrWrFn_AmdK7DataCacheCfg,
843	kCpumMsrWrFn_AmdK7BusUnitCfg,
844	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
845	kCpumMsrWrFn_AmdFam15hFpuCfg,
846	kCpumMsrWrFn_AmdFam15hDecoderCfg,
847	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
848	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
849	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
850	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
851	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
852	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
853	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
854	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
855	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
856	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
857	kCpumMsrWrFn_AmdFam10hIbsOpRip,
858	kCpumMsrWrFn_AmdFam10hIbsOpData,
859	kCpumMsrWrFn_AmdFam10hIbsOpData2,
860	kCpumMsrWrFn_AmdFam10hIbsOpData3,
861	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
862	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
863	kCpumMsrWrFn_AmdFam10hIbsCtl,
864	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
865
866	kCpumMsrWrFn_Gim,
867
868	/** End of valid MSR write function indexes. */
869	kCpumMsrWrFn_End
870	} CPUMMSRWRFN;
871
872	/**
873	* MSR range.
874	*/
875	typedef struct CPUMMSRRANGE
876	{
877	/** The first MSR. [0] */
878	uint32_t uFirst;
879	/** The last MSR. [4] */
880	uint32_t uLast;
881	/** The read function (CPUMMSRRDFN). [8] */
882	uint16_t enmRdFn;
883	/** The write function (CPUMMSRWRFN). [10] */
884	uint16_t enmWrFn;
885	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
886	* UINT16_MAX if not used by the read and write functions. [12] */
887	uint16_t offCpumCpu;
888	/** Reserved for future hacks. [14] */
889	uint16_t fReserved;
890	/** The init/read value. [16]
891	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
892	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
893	* offset into CPUM. */
894	uint64_t uValue;
895	/** The bits to ignore when writing. [24] */
896	uint64_t fWrIgnMask;
897	/** The bits that will cause a GP(0) when writing. [32]
898	* This is always checked prior to calling the write function. Using
899	* UINT64_MAX effectively marks the MSR as read-only. */
900	uint64_t fWrGpMask;
901	/** The register name, if applicable. [40] */
902	char szName[56];
903
904	#ifdef VBOX_WITH_STATISTICS
905	/** The number of reads. */
906	STAMCOUNTER cReads;
907	/** The number of writes. */
908	STAMCOUNTER cWrites;
909	/** The number of times ignored bits were written. */
910	STAMCOUNTER cIgnoredBits;
911	/** The number of GPs generated. */
912	STAMCOUNTER cGps;
913	#endif
914	} CPUMMSRRANGE;
915	#ifndef VBOX_FOR_DTRACE_LIB
916	# ifdef VBOX_WITH_STATISTICS
917	AssertCompileSize(CPUMMSRRANGE, 128);
918	# else
919	AssertCompileSize(CPUMMSRRANGE, 96);
920	# endif
921	#endif
922	/** Pointer to an MSR range. */
923	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
924	/** Pointer to a const MSR range. */
925	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
926
927
928	/**
929	* CPU features and quirks.
930	* This is mostly exploded CPUID info.
931	*/
932	typedef struct CPUMFEATURES
933	{
934	/** The CPU vendor (CPUMCPUVENDOR). */
935	uint8_t enmCpuVendor;
936	/** The CPU family. */
937	uint8_t uFamily;
938	/** The CPU model. */
939	uint8_t uModel;
940	/** The CPU stepping. */
941	uint8_t uStepping;
942	/** The microarchitecture. */
943	#ifndef VBOX_FOR_DTRACE_LIB
944	CPUMMICROARCH enmMicroarch;
945	#else
946	uint32_t enmMicroarch;
947	#endif
948	/** The maximum physical address with of the CPU. */
949	uint8_t cMaxPhysAddrWidth;
950	/** Alignment padding. */
951	uint8_t abPadding[1];
952	/** Max size of the extended state (or FPU state if no XSAVE). */
953	uint16_t cbMaxExtendedState;
954
955	/** Supports MSRs. */
956	uint32_t fMsr : 1;
957	/** Supports the page size extension (4/2 MB pages). */
958	uint32_t fPse : 1;
959	/** Supports 36-bit page size extension (4 MB pages can map memory above
960	* 4GB). */
961	uint32_t fPse36 : 1;
962	/** Supports physical address extension (PAE). */
963	uint32_t fPae : 1;
964	/** Page attribute table (PAT) support (page level cache control). */
965	uint32_t fPat : 1;
966	/** Supports the FXSAVE and FXRSTOR instructions. */
967	uint32_t fFxSaveRstor : 1;
968	/** Supports the XSAVE and XRSTOR instructions. */
969	uint32_t fXSaveRstor : 1;
970	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
971	uint32_t fOpSysXSaveRstor : 1;
972	/** Supports MMX. */
973	uint32_t fMmx : 1;
974	/** Supports AMD extensions to MMX instructions. */
975	uint32_t fAmdMmxExts : 1;
976	/** Supports SSE. */
977	uint32_t fSse : 1;
978	/** Supports SSE2. */
979	uint32_t fSse2 : 1;
980	/** Supports SSE3. */
981	uint32_t fSse3 : 1;
982	/** Supports SSSE3. */
983	uint32_t fSsse3 : 1;
984	/** Supports SSE4.1. */
985	uint32_t fSse41 : 1;
986	/** Supports SSE4.2. */
987	uint32_t fSse42 : 1;
988	/** Supports AVX. */
989	uint32_t fAvx : 1;
990	/** Supports AVX2. */
991	uint32_t fAvx2 : 1;
992	/** Supports AVX512 foundation. */
993	uint32_t fAvx512Foundation : 1;
994	/** Supports RDTSC. */
995	uint32_t fTsc : 1;
996	/** Intel SYSENTER/SYSEXIT support */
997	uint32_t fSysEnter : 1;
998	/** First generation APIC. */
999	uint32_t fApic : 1;
1000	/** Second generation APIC. */
1001	uint32_t fX2Apic : 1;
1002	/** Hypervisor present. */
1003	uint32_t fHypervisorPresent : 1;
1004	/** MWAIT & MONITOR instructions supported. */
1005	uint32_t fMonitorMWait : 1;
1006	/** MWAIT Extensions present. */
1007	uint32_t fMWaitExtensions : 1;
1008	/** Supports CMPXCHG16B in 64-bit mode. */
1009	uint32_t fMovCmpXchg16b : 1;
1010	/** Supports CLFLUSH. */
1011	uint32_t fClFlush : 1;
1012	/** Supports CLFLUSHOPT. */
1013	uint32_t fClFlushOpt : 1;
1014
1015	/** Supports AMD 3DNow instructions. */
1016	uint32_t f3DNow : 1;
1017	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1018	uint32_t f3DNowPrefetch : 1;
1019
1020	/** AMD64: Supports long mode. */
1021	uint32_t fLongMode : 1;
1022	/** AMD64: SYSCALL/SYSRET support. */
1023	uint32_t fSysCall : 1;
1024	/** AMD64: No-execute page table bit. */
1025	uint32_t fNoExecute : 1;
1026	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1027	uint32_t fLahfSahf : 1;
1028	/** AMD64: Supports RDTSCP. */
1029	uint32_t fRdTscP : 1;
1030	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1031	uint32_t fMovCr8In32Bit : 1;
1032	/** AMD64: Supports XOP (similar to VEX3/AVX). */
1033	uint32_t fXop : 1;
1034
1035	/** Indicates that FPU instruction and data pointers may leak.
1036	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1037	* is only saved and restored if an exception is pending. */
1038	uint32_t fLeakyFxSR : 1;
1039
1040	/** AMD64: Supports AMD SVM. */
1041	uint32_t fSvm : 1;
1042
1043	/** Support for Intel VMX. */
1044	uint32_t fVmx : 1;
1045
1046	/** Alignment padding / reserved for future use. */
1047	uint32_t fPadding : 23;
1048
1049	/** SVM: Supports Nested-paging. */
1050	uint32_t fSvmNestedPaging : 1;
1051	/** SVM: Support LBR (Last Branch Record) virtualization. */
1052	uint32_t fSvmLbrVirt : 1;
1053	/** SVM: Supports SVM lock. */
1054	uint32_t fSvmSvmLock : 1;
1055	/** SVM: Supports Next RIP save. */
1056	uint32_t fSvmNextRipSave : 1;
1057	/** SVM: Supports TSC rate MSR. */
1058	uint32_t fSvmTscRateMsr : 1;
1059	/** SVM: Supports VMCB clean bits. */
1060	uint32_t fSvmVmcbClean : 1;
1061	/** SVM: Supports Flush-by-ASID. */
1062	uint32_t fSvmFlusbByAsid : 1;
1063	/** SVM: Supports decode assist. */
1064	uint32_t fSvmDecodeAssists : 1;
1065	/** SVM: Supports Pause filter. */
1066	uint32_t fSvmPauseFilter : 1;
1067	/** SVM: Supports Pause filter threshold. */
1068	uint32_t fSvmPauseFilterThreshold : 1;
1069	/** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1070	uint32_t fSvmAvic : 1;
1071	/** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1072	uint32_t fSvmVirtVmsaveVmload : 1;
1073	/** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1074	uint32_t fSvmVGif : 1;
1075	/** SVM: Padding / reserved for future features. */
1076	uint32_t fSvmPadding0 : 19;
1077	/** SVM: Maximum supported ASID. */
1078	uint32_t uSvmMaxAsid;
1079
1080	/** @todo VMX features. */
1081	uint32_t auPadding[1];
1082	} CPUMFEATURES;
1083	#ifndef VBOX_FOR_DTRACE_LIB
1084	AssertCompileSize(CPUMFEATURES, 32);
1085	#endif
1086	/** Pointer to a CPU feature structure. */
1087	typedef CPUMFEATURES *PCPUMFEATURES;
1088	/** Pointer to a const CPU feature structure. */
1089	typedef CPUMFEATURES const *PCCPUMFEATURES;
1090
1091
1092	#ifndef VBOX_FOR_DTRACE_LIB
1093
1094	/** @name Guest Register Getters.
1095	* @{ */
1096	VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1097	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1098	VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1099	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1100	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
1101	VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1102	VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1103	VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1104	VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1105	VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1106	VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1107	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1108	VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1109	VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1110	VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1111	VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1112	VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1113	VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1114	VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1115	VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1116	VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1117	VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1118	VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1119	VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1120	VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1121	VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1122	VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1123	VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1124	VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1125	VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1126	VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1127	VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1128	VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1129	VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1130	VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1131	VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1132	VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1133	VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1134	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
1135	VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1136	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1137	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1138	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1139	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1140	/** @} */
1141
1142	/** @name Guest Register Setters.
1143	* @{ */
1144	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1145	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1146	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1147	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1148	VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1149	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1150	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1151	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1152	VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1153	VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1154	VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1155	VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1156	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1157	VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1158	VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1159	VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue);
1160	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1161	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1162	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1163	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1164	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1165	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1166	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1167	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1168	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1169	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1170	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1171	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1172	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1173	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1174	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1175	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1176	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1177	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1178	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1179	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1180	VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1181	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1182	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1183	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1184	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1185	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
1186	/** @} */
1187
1188
1189	/** @name Misc Guest Predicate Functions.
1190	* @{ */
1191	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1192	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1193	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1194	VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1195	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1196	VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1197	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1198	VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1199	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1200	VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1201	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1202	VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1203	VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1204	VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1205	/** @} */
1206
1207	/** @name Nested Hardware-Virtualization Helpers.
1208	* @{ */
1209	VMM_INT_DECL(bool) CPUMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
1210	VMM_INT_DECL(bool) CPUMCanSvmNstGstTakeVirtIntr(PCCPUMCTX pCtx);
1211	VMM_INT_DECL(uint8_t) CPUMGetSvmNstGstInterrupt(PCCPUMCTX pCtx);
1212	VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPU pVCpu, PCPUMCTX pCtx);
1213	VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1214	VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PVMCPU pVCpu, uint64_t uTicks);
1215	/** @} */
1216
1217	#ifndef IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS
1218
1219	/**
1220	* Tests if the guest is running in real mode or not.
1221	*
1222	* @returns true if in real mode, otherwise false.
1223	* @param pCtx Current CPU context.
1224	*/
1225	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1226	{
1227	return !(pCtx->cr0 & X86_CR0_PE);
1228	}
1229
1230	/**
1231	* Tests if the guest is running in real or virtual 8086 mode.
1232	*
1233	* @returns @c true if it is, @c false if not.
1234	* @param pCtx Current CPU context.
1235	*/
1236	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1237	{
1238	return !(pCtx->cr0 & X86_CR0_PE)
1239	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1240	}
1241
1242	/**
1243	* Tests if the guest is running in virtual 8086 mode.
1244	*
1245	* @returns @c true if it is, @c false if not.
1246	* @param pCtx Current CPU context.
1247	*/
1248	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1249	{
1250	return (pCtx->eflags.Bits.u1VM == 1);
1251	}
1252
1253	/**
1254	* Tests if the guest is running in paged protected or not.
1255	*
1256	* @returns true if in paged protected mode, otherwise false.
1257	* @param pCtx Current CPU context.
1258	*/
1259	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1260	{
1261	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1262	}
1263
1264	/**
1265	* Tests if the guest is running in long mode or not.
1266	*
1267	* @returns true if in long mode, otherwise false.
1268	* @param pCtx Current CPU context.
1269	*/
1270	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1271	{
1272	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1273	}
1274
1275	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1276
1277	/**
1278	* Tests if the guest is running in 64 bits mode or not.
1279	*
1280	* @returns true if in 64 bits protected mode, otherwise false.
1281	* @param pCtx Current CPU context.
1282	*/
1283	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1284	{
1285	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1286	return false;
1287	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1288	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1289	return pCtx->cs.Attr.n.u1Long;
1290	}
1291
1292	/**
1293	* Tests if the guest has paging enabled or not.
1294	*
1295	* @returns true if paging is enabled, otherwise false.
1296	* @param pCtx Current CPU context.
1297	*/
1298	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1299	{
1300	return !!(pCtx->cr0 & X86_CR0_PG);
1301	}
1302
1303	/**
1304	* Tests if the guest is running in PAE mode or not.
1305	*
1306	* @returns true if in PAE mode, otherwise false.
1307	* @param pCtx Current CPU context.
1308	*/
1309	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1310	{
1311	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1312	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1313	return ( (pCtx->cr4 & X86_CR4_PAE)
1314	&& CPUMIsGuestPagingEnabledEx(pCtx)
1315	&& !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1316	}
1317
1318	/**
1319	* Tests is if the guest has AMD SVM enabled or not.
1320	*
1321	* @returns true if SMV is enabled, otherwise false.
1322	* @param pCtx Current CPU context.
1323	*/
1324	DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1325	{
1326	return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1327	}
1328
1329	#ifndef IN_RC
1330	/**
1331	* Checks if the guest VMCB has the specified ctrl/instruction intercept active.
1332	*
1333	* @returns @c true if in intercept is set, @c false otherwise.
1334	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1335	* @param pCtx Pointer to the context.
1336	* @param fIntercept The SVM control/instruction intercept, see
1337	* SVM_CTRL_INTERCEPT_*.
1338	*/
1339	DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
1340	{
1341	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1342	if (!pVmcb)
1343	return false;
1344	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1345	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fIntercept);
1346	return HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, fIntercept);
1347	}
1348
1349	/**
1350	* Checks if the guest VMCB has the specified CR read intercept active.
1351	*
1352	* @returns @c true if in intercept is set, @c false otherwise.
1353	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1354	* @param pCtx Pointer to the context.
1355	* @param uCr The CR register number (0 to 15).
1356	*/
1357	DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1358	{
1359	Assert(uCr < 16);
1360	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1361	if (!pVmcb)
1362	return false;
1363	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1364	return RT_BOOL(pVmcb->ctrl.u16InterceptRdCRx & (UINT16_C(1) << uCr));
1365	return HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr);
1366	}
1367
1368	/**
1369	* Checks if the guest VMCB has the specified CR write intercept active.
1370	*
1371	* @returns @c true if in intercept is set, @c false otherwise.
1372	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1373	* @param pCtx Pointer to the context.
1374	* @param uCr The CR register number (0 to 15).
1375	*/
1376	DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1377	{
1378	Assert(uCr < 16);
1379	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1380	if (!pVmcb)
1381	return false;
1382	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1383	return RT_BOOL(pVmcb->ctrl.u16InterceptWrCRx & (UINT16_C(1) << uCr));
1384	return HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr);
1385	}
1386
1387	/**
1388	* Checks if the guest VMCB has the specified DR read intercept active.
1389	*
1390	* @returns @c true if in intercept is set, @c false otherwise.
1391	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1392	* @param pCtx Pointer to the context.
1393	* @param uDr The DR register number (0 to 15).
1394	*/
1395	DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1396	{
1397	Assert(uDr < 16);
1398	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1399	if (!pVmcb)
1400	return false;
1401	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1402	return RT_BOOL(pVmcb->ctrl.u16InterceptRdDRx & (UINT16_C(1) << uDr));
1403	return HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr);
1404	}
1405
1406	/**
1407	* Checks if the guest VMCB has the specified DR write intercept active.
1408	*
1409	* @returns @c true if in intercept is set, @c false otherwise.
1410	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1411	* @param pCtx Pointer to the context.
1412	* @param uDr The DR register number (0 to 15).
1413	*/
1414	DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1415	{
1416	Assert(uDr < 16);
1417	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1418	if (!pVmcb)
1419	return false;
1420	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1421	return RT_BOOL(pVmcb->ctrl.u16InterceptWrDRx & (UINT16_C(1) << uDr));
1422	return HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr);
1423	}
1424
1425	/**
1426	* Checks if the guest VMCB has the specified exception intercept active.
1427	*
1428	* @returns @c true if in intercept is active, @c false otherwise.
1429	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1430	* @param pCtx Pointer to the context.
1431	* @param uVector The exception / interrupt vector.
1432	*/
1433	DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1434	{
1435	Assert(uVector < 32);
1436	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1437	if (!pVmcb)
1438	return false;
1439	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1440	return RT_BOOL(pVmcb->ctrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
1441	return HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector);
1442	}
1443	#endif /* !IN_RC */
1444
1445	/**
1446	* Checks if we are executing inside an SVM nested hardware-virtualized guest.
1447	*
1448	* @returns @c true if in SVM nested-guest mode, @c false otherwise.
1449	* @param pCtx Pointer to the context.
1450	*/
1451	DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1452	{
1453	/*
1454	* With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1455	* See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1456	*/
1457	#ifndef IN_RC
1458	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1459	return pVmcb && (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
1460	#else
1461	NOREF(pCtx);
1462	return false;
1463	#endif
1464	}
1465
1466	/**
1467	* Checks if we are executing inside a VMX nested hardware-virtualized guest.
1468	*
1469	* @returns @c true if in VMX nested-guest mode, @c false otherwise.
1470	* @param pCtx Pointer to the context.
1471	*/
1472	DECLINLINE(bool) CPUMIsGuestInVmxNestedHwVirtMode(PCCPUMCTX pCtx)
1473	{
1474	/** @todo Intel. */
1475	NOREF(pCtx);
1476	return false;
1477	}
1478
1479	/**
1480	* Checks if we are executing inside a nested hardware-virtualized guest.
1481	*
1482	* @returns @c true if in SVM/VMX nested-guest mode, @c false otherwise.
1483	* @param pCtx Pointer to the context.
1484	*/
1485	DECLINLINE(bool) CPUMIsGuestInNestedHwVirtMode(PCCPUMCTX pCtx)
1486	{
1487	return CPUMIsGuestInSvmNestedHwVirtMode(pCtx) \|\| CPUMIsGuestInVmxNestedHwVirtMode(pCtx);
1488	}
1489	#endif /* IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS */
1490
1491	/** @} */
1492
1493
1494	/** @name Hypervisor Register Getters.
1495	* @{ */
1496	VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1497	VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1498	VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1499	VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1500	VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1501	VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1502	#if 0 /* these are not correct. */
1503	VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1504	VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1505	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1506	VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1507	#endif
1508	/** This register is only saved on fatal traps. */
1509	VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1510	VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1511	/** This register is only saved on fatal traps. */
1512	VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1513	/** This register is only saved on fatal traps. */
1514	VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1515	VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1516	VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1517	VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1518	VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1519	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1520	VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1521	VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1522	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1523	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1524	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1525	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1526	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1527	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1528	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1529	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1530	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1531	VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1532	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1533	/** @} */
1534
1535	/** @name Hypervisor Register Setters.
1536	* @{ */
1537	VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1538	VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1539	VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1540	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1541	VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1542	VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1543	VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1544	VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1545	VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1546	VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1547	VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1548	VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1549	VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1550	VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1551	VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1552	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1553	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1554	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1555	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1556	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1557	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1558	VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1559	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1560	/** @} */
1561
1562	VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1563	VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1564	VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1565	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1566	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1567	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1568	VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1569	VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1570	VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1571	VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1572
1573	/** @name Changed flags.
1574	* These flags are used to keep track of which important register that
1575	* have been changed since last they were reset. The only one allowed
1576	* to clear them is REM!
1577	* @{
1578	*/
1579	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1580	#define CPUM_CHANGED_CR0 RT_BIT(1)
1581	#define CPUM_CHANGED_CR4 RT_BIT(2)
1582	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1583	#define CPUM_CHANGED_CR3 RT_BIT(4)
1584	#define CPUM_CHANGED_GDTR RT_BIT(5)
1585	#define CPUM_CHANGED_IDTR RT_BIT(6)
1586	#define CPUM_CHANGED_LDTR RT_BIT(7)
1587	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
1588	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1589	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
1590	#define CPUM_CHANGED_CPUID RT_BIT(11)
1591	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1592	\| CPUM_CHANGED_CR0 \
1593	\| CPUM_CHANGED_CR4 \
1594	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1595	\| CPUM_CHANGED_CR3 \
1596	\| CPUM_CHANGED_GDTR \
1597	\| CPUM_CHANGED_IDTR \
1598	\| CPUM_CHANGED_LDTR \
1599	\| CPUM_CHANGED_TR \
1600	\| CPUM_CHANGED_SYSENTER_MSR \
1601	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
1602	\| CPUM_CHANGED_CPUID )
1603	/** @} */
1604
1605	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1606	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1607	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1608	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
1609	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1610	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1611	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1612	VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
1613	VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
1614	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1615	VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1616	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1617	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1618	VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1619	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1620	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1621	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1622	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1623	VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
1624	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1625	VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
1626	uint64_t *puValidEfer);
1627	VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
1628
1629
1630	/** @name Typical scalable bus frequency values.
1631	* @{ */
1632	/** Special internal value indicating that we don't know the frequency.
1633	* @internal */
1634	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1635	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1636	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1637	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1638	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1639	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1640	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1641	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1642	/** @} */
1643
1644
1645	#ifdef IN_RING3
1646	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1647	* @{
1648	*/
1649
1650	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1651	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1652	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1653	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1654	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1655	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1656	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1657	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1658	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1659	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1660
1661	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1662	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1663	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1664	uint8_t bModel, uint8_t bStepping);
1665	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1666	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1667	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1668	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1669	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1670	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1671	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
1672
1673	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1674
1675	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
1676	/** @name APIs for the CPUID raw-mode patch (legacy).
1677	* @{ */
1678	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1679	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1680	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1681	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1682	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1683	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1684	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1685	/** @} */
1686	# endif
1687
1688	/** @} */
1689	#endif /* IN_RING3 */
1690
1691	#ifdef IN_RC
1692	/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1693	* @{
1694	*/
1695
1696	/**
1697	* Calls a guest trap/interrupt handler directly
1698	*
1699	* Assumes a trap stack frame has already been setup on the guest's stack!
1700	* This function does not return!
1701	*
1702	* @param pRegFrame Original trap/interrupt context
1703	* @param selCS Code selector of handler
1704	* @param pHandler GC virtual address of handler
1705	* @param eflags Callee's EFLAGS
1706	* @param selSS Stack selector for handler
1707	* @param pEsp Stack address for handler
1708	*/
1709	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1710	uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1711
1712	/**
1713	* Call guest V86 code directly.
1714	*
1715	* This function does not return!
1716	*
1717	* @param pRegFrame Original trap/interrupt context
1718	*/
1719	DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1720
1721	VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1722	VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1723	#ifdef VBOX_WITH_RAW_RING1
1724	VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1725	#endif
1726	VMMRCDECL(void) CPUMRCProcessForceFlag(PVMCPU pVCpu);
1727
1728	/** @} */
1729	#endif /* IN_RC */
1730
1731	#ifdef IN_RING0
1732	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1733	* @{
1734	*/
1735	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1736	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1737	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1738	DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPU pVCpu);
1739	DECLASM(void) CPUMR0TouchHostFpu(void);
1740	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu);
1741	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu);
1742	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu);
1743	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1744	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1745	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1746
1747	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1748	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1749	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1750	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1751	#endif
1752
1753	/** @} */
1754	#endif /* IN_RING0 */
1755
1756	/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
1757	* @{
1758	*/
1759	VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPU pVCpu);
1760	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPU pVCpu);
1761	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPU pVCpu);
1762	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPU pVCpu);
1763	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPU pVCpu);
1764	/** @} */
1765
1766
1767	#endif /* !VBOX_FOR_DTRACE_LIB */
1768	/** @} */
1769	RT_C_DECLS_END
1770
1771
1772	#endif
1773

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 70266

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