cpum.h@ 70450

Last change on this file since 70450 was 70450, checked in by vboxsync, 7 years ago
VMM/CPUMR3CpuId.cpp: Some new intel model numbers.
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpum_h
27	#define ___VBox_vmm_cpum_h
28
29	#include <iprt/x86.h>
30	#include <VBox/types.h>
31	#include <VBox/vmm/cpumctx.h>
32	#include <VBox/vmm/stam.h>
33	#include <VBox/vmm/vmapi.h>
34
35	RT_C_DECLS_BEGIN
36
37	/** @defgroup grp_cpum The CPU Monitor / Manager API
38	* @ingroup grp_vmm
39	* @{
40	*/
41
42	/**
43	* CPUID feature to set or clear.
44	*/
45	typedef enum CPUMCPUIDFEATURE
46	{
47	CPUMCPUIDFEATURE_INVALID = 0,
48	/** The APIC feature bit. (Std+Ext)
49	* Note! There is a per-cpu flag for masking this CPUID feature bit when the
50	* APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
51	* at VM construction time like all the others. This didn't used to be
52	* that way, this is new with 5.1. */
53	CPUMCPUIDFEATURE_APIC,
54	/** The sysenter/sysexit feature bit. (Std) */
55	CPUMCPUIDFEATURE_SEP,
56	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
57	CPUMCPUIDFEATURE_SYSCALL,
58	/** The PAE feature bit. (Std+Ext) */
59	CPUMCPUIDFEATURE_PAE,
60	/** The NX feature bit. (Ext) */
61	CPUMCPUIDFEATURE_NX,
62	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
63	CPUMCPUIDFEATURE_LAHF,
64	/** The LONG MODE feature bit. (Ext) */
65	CPUMCPUIDFEATURE_LONG_MODE,
66	/** The PAT feature bit. (Std+Ext) */
67	CPUMCPUIDFEATURE_PAT,
68	/** The x2APIC feature bit. (Std) */
69	CPUMCPUIDFEATURE_X2APIC,
70	/** The RDTSCP feature bit. (Ext) */
71	CPUMCPUIDFEATURE_RDTSCP,
72	/** The Hypervisor Present bit. (Std) */
73	CPUMCPUIDFEATURE_HVP,
74	/** The MWait Extensions bits (Std) */
75	CPUMCPUIDFEATURE_MWAIT_EXTS,
76	/** 32bit hackishness. */
77	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
78	} CPUMCPUIDFEATURE;
79
80	/**
81	* CPU Vendor.
82	*/
83	typedef enum CPUMCPUVENDOR
84	{
85	CPUMCPUVENDOR_INVALID = 0,
86	CPUMCPUVENDOR_INTEL,
87	CPUMCPUVENDOR_AMD,
88	CPUMCPUVENDOR_VIA,
89	CPUMCPUVENDOR_CYRIX,
90	CPUMCPUVENDOR_UNKNOWN,
91	/** 32bit hackishness. */
92	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
93	} CPUMCPUVENDOR;
94
95
96	/**
97	* X86 and AMD64 CPU microarchitectures and in processor generations.
98	*
99	* @remarks The separation here is sometimes a little bit too finely grained,
100	* and the differences is more like processor generation than micro
101	* arch. This can be useful, so we'll provide functions for getting at
102	* more coarse grained info.
103	*/
104	typedef enum CPUMMICROARCH
105	{
106	kCpumMicroarch_Invalid = 0,
107
108	kCpumMicroarch_Intel_First,
109
110	kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
111	kCpumMicroarch_Intel_80186,
112	kCpumMicroarch_Intel_80286,
113	kCpumMicroarch_Intel_80386,
114	kCpumMicroarch_Intel_80486,
115	kCpumMicroarch_Intel_P5,
116
117	kCpumMicroarch_Intel_P6_Core_Atom_First,
118	kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
119	kCpumMicroarch_Intel_P6_II,
120	kCpumMicroarch_Intel_P6_III,
121
122	kCpumMicroarch_Intel_P6_M_Banias,
123	kCpumMicroarch_Intel_P6_M_Dothan,
124	kCpumMicroarch_Intel_Core_Yonah, /*< Core, also known as Enhanced Pentium M. /
125
126	kCpumMicroarch_Intel_Core2_First,
127	kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /*< 65nm, Merom/Conroe/Kentsfield/Tigerton /
128	kCpumMicroarch_Intel_Core2_Penryn, /*< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown /
129	kCpumMicroarch_Intel_Core2_End,
130
131	kCpumMicroarch_Intel_Core7_First,
132	kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
133	kCpumMicroarch_Intel_Core7_Westmere,
134	kCpumMicroarch_Intel_Core7_SandyBridge,
135	kCpumMicroarch_Intel_Core7_IvyBridge,
136	kCpumMicroarch_Intel_Core7_Haswell,
137	kCpumMicroarch_Intel_Core7_Broadwell,
138	kCpumMicroarch_Intel_Core7_Skylake,
139	kCpumMicroarch_Intel_Core7_KabyLake,
140	kCpumMicroarch_Intel_Core7_CoffeeLake,
141	kCpumMicroarch_Intel_Core7_Cannonlake,
142	kCpumMicroarch_Intel_Core7_End,
143
144	kCpumMicroarch_Intel_Atom_First,
145	kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
146	kCpumMicroarch_Intel_Atom_Lincroft, /*< Second generation bonnell (44nm). /
147	kCpumMicroarch_Intel_Atom_Saltwell, /*< 32nm shrink of Bonnell. /
148	kCpumMicroarch_Intel_Atom_Silvermont, /*< 22nm /
149	kCpumMicroarch_Intel_Atom_Airmount, /*< 14nm /
150	kCpumMicroarch_Intel_Atom_Goldmont, /*< 14nm /
151	kCpumMicroarch_Intel_Atom_Unknown,
152	kCpumMicroarch_Intel_Atom_End,
153
154
155	kCpumMicroarch_Intel_Phi_First,
156	kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
157	kCpumMicroarch_Intel_Phi_KnightsCorner,
158	kCpumMicroarch_Intel_Phi_KnightsLanding,
159	kCpumMicroarch_Intel_Phi_KnightsHill,
160	kCpumMicroarch_Intel_Phi_KnightsMill,
161	kCpumMicroarch_Intel_Phi_End,
162
163	kCpumMicroarch_Intel_P6_Core_Atom_End,
164
165	kCpumMicroarch_Intel_NB_First,
166	kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /*< 180nm /
167	kCpumMicroarch_Intel_NB_Northwood, /*< 130nm /
168	kCpumMicroarch_Intel_NB_Prescott, /*< 90nm /
169	kCpumMicroarch_Intel_NB_Prescott2M, /*< 90nm /
170	kCpumMicroarch_Intel_NB_CedarMill, /*< 65nm /
171	kCpumMicroarch_Intel_NB_Gallatin, /*< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). /
172	kCpumMicroarch_Intel_NB_Unknown,
173	kCpumMicroarch_Intel_NB_End,
174
175	kCpumMicroarch_Intel_Unknown,
176	kCpumMicroarch_Intel_End,
177
178	kCpumMicroarch_AMD_First,
179	kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
180	kCpumMicroarch_AMD_Am386,
181	kCpumMicroarch_AMD_Am486,
182	kCpumMicroarch_AMD_Am486Enh, /*< Covers Am5x86 as well. /
183	kCpumMicroarch_AMD_K5,
184	kCpumMicroarch_AMD_K6,
185
186	kCpumMicroarch_AMD_K7_First,
187	kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
188	kCpumMicroarch_AMD_K7_Spitfire,
189	kCpumMicroarch_AMD_K7_Thunderbird,
190	kCpumMicroarch_AMD_K7_Morgan,
191	kCpumMicroarch_AMD_K7_Thoroughbred,
192	kCpumMicroarch_AMD_K7_Barton,
193	kCpumMicroarch_AMD_K7_Unknown,
194	kCpumMicroarch_AMD_K7_End,
195
196	kCpumMicroarch_AMD_K8_First,
197	kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /*< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin /
198	kCpumMicroarch_AMD_K8_90nm, /*< 90nm shrink /
199	kCpumMicroarch_AMD_K8_90nm_DualCore, /*< 90nm with two cores. /
200	kCpumMicroarch_AMD_K8_90nm_AMDV, /*< 90nm with AMD-V (usually) and two cores (usually). /
201	kCpumMicroarch_AMD_K8_65nm, /*< 65nm shrink. /
202	kCpumMicroarch_AMD_K8_End,
203
204	kCpumMicroarch_AMD_K10,
205	kCpumMicroarch_AMD_K10_Lion,
206	kCpumMicroarch_AMD_K10_Llano,
207	kCpumMicroarch_AMD_Bobcat,
208	kCpumMicroarch_AMD_Jaguar,
209
210	kCpumMicroarch_AMD_15h_First,
211	kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
212	kCpumMicroarch_AMD_15h_Piledriver,
213	kCpumMicroarch_AMD_15h_Steamroller, /*< Yet to be released, might have different family. /
214	kCpumMicroarch_AMD_15h_Excavator, /*< Yet to be released, might have different family. /
215	kCpumMicroarch_AMD_15h_Unknown,
216	kCpumMicroarch_AMD_15h_End,
217
218	kCpumMicroarch_AMD_16h_First,
219	kCpumMicroarch_AMD_16h_End,
220
221	kCpumMicroarch_AMD_Zen_First,
222	kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
223	kCpumMicroarch_AMD_Zen_End,
224
225	kCpumMicroarch_AMD_Unknown,
226	kCpumMicroarch_AMD_End,
227
228	kCpumMicroarch_VIA_First,
229	kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
230	kCpumMicroarch_Centaur_C2,
231	kCpumMicroarch_Centaur_C3,
232	kCpumMicroarch_VIA_C3_M2,
233	kCpumMicroarch_VIA_C3_C5A, /*< 180nm Samuel - Cyrix III, C3, 1GigaPro. /
234	kCpumMicroarch_VIA_C3_C5B, /*< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. /
235	kCpumMicroarch_VIA_C3_C5C, /*< 130nm Ezra - C3, Eden ESP. /
236	kCpumMicroarch_VIA_C3_C5N, /*< 130nm Ezra-T - C3. /
237	kCpumMicroarch_VIA_C3_C5XL, /*< 130nm Nehemiah - C3, Eden ESP, Eden-N. /
238	kCpumMicroarch_VIA_C3_C5P, /*< 130nm Nehemiah+ - C3. /
239	kCpumMicroarch_VIA_C7_C5J, /*< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. /
240	kCpumMicroarch_VIA_Isaiah,
241	kCpumMicroarch_VIA_Unknown,
242	kCpumMicroarch_VIA_End,
243
244	kCpumMicroarch_Cyrix_First,
245	kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
246	kCpumMicroarch_Cyrix_M1,
247	kCpumMicroarch_Cyrix_MediaGX,
248	kCpumMicroarch_Cyrix_MediaGXm,
249	kCpumMicroarch_Cyrix_M2,
250	kCpumMicroarch_Cyrix_Unknown,
251	kCpumMicroarch_Cyrix_End,
252
253	kCpumMicroarch_NEC_First,
254	kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
255	kCpumMicroarch_NEC_V30,
256	kCpumMicroarch_NEC_End,
257
258	kCpumMicroarch_Unknown,
259
260	kCpumMicroarch_32BitHack = 0x7fffffff
261	} CPUMMICROARCH;
262
263
264	/** Predicate macro for catching netburst CPUs. */
265	#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
266	((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
267
268	/** Predicate macro for catching Core7 CPUs. */
269	#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
270	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
271
272	/** Predicate macro for catching Core 2 CPUs. */
273	#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
274	((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
275
276	/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
277	#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
278	((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
279
280	/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
281	#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
282	((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
283
284	/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
285	#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
286
287	/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
288	#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
289
290	/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
291	#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
292
293	/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
294	#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
295
296	/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
297	* decendants). */
298	#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
299	((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
300
301	/** Predicate macro for catching AMD Family 16H CPUs. */
302	#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
303	((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
304
305
306
307	/**
308	* CPUID leaf.
309	*
310	* @remarks This structure is used by the patch manager and is therefore
311	* more or less set in stone.
312	*/
313	typedef struct CPUMCPUIDLEAF
314	{
315	/** The leaf number. */
316	uint32_t uLeaf;
317	/** The sub-leaf number. */
318	uint32_t uSubLeaf;
319	/** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
320	uint32_t fSubLeafMask;
321
322	/** The EAX value. */
323	uint32_t uEax;
324	/** The EBX value. */
325	uint32_t uEbx;
326	/** The ECX value. */
327	uint32_t uEcx;
328	/** The EDX value. */
329	uint32_t uEdx;
330
331	/** Flags. */
332	uint32_t fFlags;
333	} CPUMCPUIDLEAF;
334	#ifndef VBOX_FOR_DTRACE_LIB
335	AssertCompileSize(CPUMCPUIDLEAF, 32);
336	#endif
337	/** Pointer to a CPUID leaf. */
338	typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
339	/** Pointer to a const CPUID leaf. */
340	typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
341
342	/** @name CPUMCPUIDLEAF::fFlags
343	* @{ */
344	/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
345	* and EDX containing the extended APIC ID. */
346	#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
347	/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
348	#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
349	/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
350	#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
351	/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
352	#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
353	/** Mask of the valid flags. */
354	#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
355	/** @} */
356
357	/**
358	* Method used to deal with unknown CPUID leaves.
359	* @remarks Used in patch code.
360	*/
361	typedef enum CPUMUNKNOWNCPUID
362	{
363	/** Invalid zero value. */
364	CPUMUNKNOWNCPUID_INVALID = 0,
365	/** Use given default values (DefCpuId). */
366	CPUMUNKNOWNCPUID_DEFAULTS,
367	/** Return the last standard leaf.
368	* Intel Sandy Bridge has been observed doing this. */
369	CPUMUNKNOWNCPUID_LAST_STD_LEAF,
370	/** Return the last standard leaf, with ecx observed.
371	* Intel Sandy Bridge has been observed doing this. */
372	CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
373	/** The register values are passed thru unmodified. */
374	CPUMUNKNOWNCPUID_PASSTHRU,
375	/** End of valid value. */
376	CPUMUNKNOWNCPUID_END,
377	/** Ensure 32-bit type. */
378	CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
379	} CPUMUNKNOWNCPUID;
380	/** Pointer to unknown CPUID leaf method. */
381	typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
382
383
384	/**
385	* MSR read functions.
386	*/
387	typedef enum CPUMMSRRDFN
388	{
389	/** Invalid zero value. */
390	kCpumMsrRdFn_Invalid = 0,
391	/** Return the CPUMMSRRANGE::uValue. */
392	kCpumMsrRdFn_FixedValue,
393	/** Alias to the MSR range starting at the MSR given by
394	* CPUMMSRRANGE::uValue. Must be used in pair with
395	* kCpumMsrWrFn_MsrAlias. */
396	kCpumMsrRdFn_MsrAlias,
397	/** Write only register, GP all read attempts. */
398	kCpumMsrRdFn_WriteOnly,
399
400	kCpumMsrRdFn_Ia32P5McAddr,
401	kCpumMsrRdFn_Ia32P5McType,
402	kCpumMsrRdFn_Ia32TimestampCounter,
403	kCpumMsrRdFn_Ia32PlatformId, /*< Takes real CPU value for reference. /
404	kCpumMsrRdFn_Ia32ApicBase,
405	kCpumMsrRdFn_Ia32FeatureControl,
406	kCpumMsrRdFn_Ia32BiosSignId, /*< Range value returned. /
407	kCpumMsrRdFn_Ia32SmmMonitorCtl,
408	kCpumMsrRdFn_Ia32PmcN,
409	kCpumMsrRdFn_Ia32MonitorFilterLineSize,
410	kCpumMsrRdFn_Ia32MPerf,
411	kCpumMsrRdFn_Ia32APerf,
412	kCpumMsrRdFn_Ia32MtrrCap, /*< Takes real CPU value for reference. /
413	kCpumMsrRdFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
414	kCpumMsrRdFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
415	kCpumMsrRdFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
416	kCpumMsrRdFn_Ia32MtrrDefType,
417	kCpumMsrRdFn_Ia32Pat,
418	kCpumMsrRdFn_Ia32SysEnterCs,
419	kCpumMsrRdFn_Ia32SysEnterEsp,
420	kCpumMsrRdFn_Ia32SysEnterEip,
421	kCpumMsrRdFn_Ia32McgCap,
422	kCpumMsrRdFn_Ia32McgStatus,
423	kCpumMsrRdFn_Ia32McgCtl,
424	kCpumMsrRdFn_Ia32DebugCtl,
425	kCpumMsrRdFn_Ia32SmrrPhysBase,
426	kCpumMsrRdFn_Ia32SmrrPhysMask,
427	kCpumMsrRdFn_Ia32PlatformDcaCap,
428	kCpumMsrRdFn_Ia32CpuDcaCap,
429	kCpumMsrRdFn_Ia32Dca0Cap,
430	kCpumMsrRdFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
431	kCpumMsrRdFn_Ia32PerfStatus, /*< Range value returned. /
432	kCpumMsrRdFn_Ia32PerfCtl, /*< Range value returned. /
433	kCpumMsrRdFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
434	kCpumMsrRdFn_Ia32PerfCapabilities, /*< Takes reference value. /
435	kCpumMsrRdFn_Ia32FixedCtrCtrl,
436	kCpumMsrRdFn_Ia32PerfGlobalStatus, /*< Takes reference value. /
437	kCpumMsrRdFn_Ia32PerfGlobalCtrl,
438	kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
439	kCpumMsrRdFn_Ia32PebsEnable,
440	kCpumMsrRdFn_Ia32ClockModulation, /*< Range value returned. /
441	kCpumMsrRdFn_Ia32ThermInterrupt, /*< Range value returned. /
442	kCpumMsrRdFn_Ia32ThermStatus, /*< Range value returned. /
443	kCpumMsrRdFn_Ia32Therm2Ctl, /*< Range value returned. /
444	kCpumMsrRdFn_Ia32MiscEnable, /*< Range value returned. /
445	kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
446	kCpumMsrRdFn_Ia32McNCtl2, /*< Takes register number of start of range. /
447	kCpumMsrRdFn_Ia32DsArea,
448	kCpumMsrRdFn_Ia32TscDeadline,
449	kCpumMsrRdFn_Ia32X2ApicN,
450	kCpumMsrRdFn_Ia32DebugInterface,
451	kCpumMsrRdFn_Ia32VmxBase, /*< Takes real value as reference. /
452	kCpumMsrRdFn_Ia32VmxPinbasedCtls, /*< Takes real value as reference. /
453	kCpumMsrRdFn_Ia32VmxProcbasedCtls, /*< Takes real value as reference. /
454	kCpumMsrRdFn_Ia32VmxExitCtls, /*< Takes real value as reference. /
455	kCpumMsrRdFn_Ia32VmxEntryCtls, /*< Takes real value as reference. /
456	kCpumMsrRdFn_Ia32VmxMisc, /*< Takes real value as reference. /
457	kCpumMsrRdFn_Ia32VmxCr0Fixed0, /*< Takes real value as reference. /
458	kCpumMsrRdFn_Ia32VmxCr0Fixed1, /*< Takes real value as reference. /
459	kCpumMsrRdFn_Ia32VmxCr4Fixed0, /*< Takes real value as reference. /
460	kCpumMsrRdFn_Ia32VmxCr4Fixed1, /*< Takes real value as reference. /
461	kCpumMsrRdFn_Ia32VmxVmcsEnum, /*< Takes real value as reference. /
462	kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /*< Takes real value as reference. /
463	kCpumMsrRdFn_Ia32VmxEptVpidCap, /*< Takes real value as reference. /
464	kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /*< Takes real value as reference. /
465	kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /*< Takes real value as reference. /
466	kCpumMsrRdFn_Ia32VmxTrueExitCtls, /*< Takes real value as reference. /
467	kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /*< Takes real value as reference. /
468	kCpumMsrRdFn_Ia32VmxVmFunc, /*< Takes real value as reference. /
469
470	kCpumMsrRdFn_Amd64Efer,
471	kCpumMsrRdFn_Amd64SyscallTarget,
472	kCpumMsrRdFn_Amd64LongSyscallTarget,
473	kCpumMsrRdFn_Amd64CompSyscallTarget,
474	kCpumMsrRdFn_Amd64SyscallFlagMask,
475	kCpumMsrRdFn_Amd64FsBase,
476	kCpumMsrRdFn_Amd64GsBase,
477	kCpumMsrRdFn_Amd64KernelGsBase,
478	kCpumMsrRdFn_Amd64TscAux,
479
480	kCpumMsrRdFn_IntelEblCrPowerOn,
481	kCpumMsrRdFn_IntelI7CoreThreadCount,
482	kCpumMsrRdFn_IntelP4EbcHardPowerOn,
483	kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
484	kCpumMsrRdFn_IntelP4EbcFrequencyId,
485	kCpumMsrRdFn_IntelP6FsbFrequency, /*< Takes real value as reference. /
486	kCpumMsrRdFn_IntelPlatformInfo,
487	kCpumMsrRdFn_IntelFlexRatio, /*< Takes real value as reference. /
488	kCpumMsrRdFn_IntelPkgCStConfigControl,
489	kCpumMsrRdFn_IntelPmgIoCaptureBase,
490	kCpumMsrRdFn_IntelLastBranchFromToN,
491	kCpumMsrRdFn_IntelLastBranchFromN,
492	kCpumMsrRdFn_IntelLastBranchToN,
493	kCpumMsrRdFn_IntelLastBranchTos,
494	kCpumMsrRdFn_IntelBblCrCtl,
495	kCpumMsrRdFn_IntelBblCrCtl3,
496	kCpumMsrRdFn_IntelI7TemperatureTarget, /*< Range value returned. /
497	kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/*< Takes register number. /
498	kCpumMsrRdFn_IntelI7MiscPwrMgmt,
499	kCpumMsrRdFn_IntelP6CrN,
500	kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
501	kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
502	kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
503	kCpumMsrRdFn_IntelI7SandyAesNiCtl,
504	kCpumMsrRdFn_IntelI7TurboRatioLimit, /*< Returns range value. /
505	kCpumMsrRdFn_IntelI7LbrSelect,
506	kCpumMsrRdFn_IntelI7SandyErrorControl,
507	kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/*< Returns range value. /
508	kCpumMsrRdFn_IntelI7PowerCtl,
509	kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
510	kCpumMsrRdFn_IntelI7PebsLdLat,
511	kCpumMsrRdFn_IntelI7PkgCnResidencyN, /*< Takes C-state number. /
512	kCpumMsrRdFn_IntelI7CoreCnResidencyN, /*< Takes C-state number. /
513	kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/*< Takes real value as reference. /
514	kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /*< Takes real value as reference. /
515	kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /*< Takes real value as reference. /
516	kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /*< Takes real value as reference. /
517	kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /*< Takes real value as reference. /
518	kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /*< Takes real value as reference. /
519	kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /*< Takes real value as reference. /
520	kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /*< Takes real value as reference. /
521	kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /*< Takes real value as reference. /
522	kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /*< Takes real value as reference. /
523	kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/*< Takes real value as reference. /
524	kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /*< Takes real value as reference. /
525	kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /*< Takes real value as reference. /
526	kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /*< Takes real value as reference. /
527	kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /*< Takes real value as reference. /
528	kCpumMsrRdFn_IntelI7RaplPp0Policy, /*< Takes real value as reference. /
529	kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /*< Takes real value as reference. /
530	kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /*< Takes real value as reference. /
531	kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /*< Takes real value as reference. /
532	kCpumMsrRdFn_IntelI7RaplPp1Policy, /*< Takes real value as reference. /
533	kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /*< Takes real value as reference. /
534	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /*< Takes real value as reference. /
535	kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /*< Takes real value as reference. /
536	kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
537	kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
538	kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
539	kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
540	kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
541	kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
542	kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
543	kCpumMsrRdFn_IntelI7UncCBoxConfig,
544	kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
545	kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
546	kCpumMsrRdFn_IntelI7SmiCount,
547	kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /*< Range value returned. /
548	kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
549	kCpumMsrRdFn_IntelCore1ExtConfig,
550	kCpumMsrRdFn_IntelCore1DtsCalControl,
551	kCpumMsrRdFn_IntelCore2PeciControl,
552	kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
553
554	kCpumMsrRdFn_P6LastBranchFromIp,
555	kCpumMsrRdFn_P6LastBranchToIp,
556	kCpumMsrRdFn_P6LastIntFromIp,
557	kCpumMsrRdFn_P6LastIntToIp,
558
559	kCpumMsrRdFn_AmdFam15hTscRate,
560	kCpumMsrRdFn_AmdFam15hLwpCfg,
561	kCpumMsrRdFn_AmdFam15hLwpCbAddr,
562	kCpumMsrRdFn_AmdFam10hMc4MiscN,
563	kCpumMsrRdFn_AmdK8PerfCtlN,
564	kCpumMsrRdFn_AmdK8PerfCtrN,
565	kCpumMsrRdFn_AmdK8SysCfg, /*< Range value returned. /
566	kCpumMsrRdFn_AmdK8HwCr,
567	kCpumMsrRdFn_AmdK8IorrBaseN,
568	kCpumMsrRdFn_AmdK8IorrMaskN,
569	kCpumMsrRdFn_AmdK8TopOfMemN,
570	kCpumMsrRdFn_AmdK8NbCfg1,
571	kCpumMsrRdFn_AmdK8McXcptRedir,
572	kCpumMsrRdFn_AmdK8CpuNameN,
573	kCpumMsrRdFn_AmdK8HwThermalCtrl, /*< Range value returned. /
574	kCpumMsrRdFn_AmdK8SwThermalCtrl,
575	kCpumMsrRdFn_AmdK8FidVidControl, /*< Range value returned. /
576	kCpumMsrRdFn_AmdK8FidVidStatus, /*< Range value returned. /
577	kCpumMsrRdFn_AmdK8McCtlMaskN,
578	kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
579	kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
580	kCpumMsrRdFn_AmdK8IntPendingMessage,
581	kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
582	kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
583	kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
584	kCpumMsrRdFn_AmdFam10hPStateCurLimit, /*< Returns range value. /
585	kCpumMsrRdFn_AmdFam10hPStateControl, /*< Returns range value. /
586	kCpumMsrRdFn_AmdFam10hPStateStatus, /*< Returns range value. /
587	kCpumMsrRdFn_AmdFam10hPStateN, /*< Returns range value. This isn't an register index! /
588	kCpumMsrRdFn_AmdFam10hCofVidControl, /*< Returns range value. /
589	kCpumMsrRdFn_AmdFam10hCofVidStatus, /*< Returns range value. /
590	kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
591	kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
592	kCpumMsrRdFn_AmdK8SmmBase,
593	kCpumMsrRdFn_AmdK8SmmAddr,
594	kCpumMsrRdFn_AmdK8SmmMask,
595	kCpumMsrRdFn_AmdK8VmCr,
596	kCpumMsrRdFn_AmdK8IgnNe,
597	kCpumMsrRdFn_AmdK8SmmCtl,
598	kCpumMsrRdFn_AmdK8VmHSavePa,
599	kCpumMsrRdFn_AmdFam10hVmLockKey,
600	kCpumMsrRdFn_AmdFam10hSmmLockKey,
601	kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
602	kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
603	kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
604	kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
605	kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
606	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
607	kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
608	kCpumMsrRdFn_AmdK7MicrocodeCtl, /*< Returns range value. /
609	kCpumMsrRdFn_AmdK7ClusterIdMaybe, /*< Returns range value. /
610	kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
611	kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
612	kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
613	kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
614	kCpumMsrRdFn_AmdK8PatchLevel, /*< Returns range value. /
615	kCpumMsrRdFn_AmdK7DebugStatusMaybe,
616	kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
617	kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
618	kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
619	kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
620	kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
621	kCpumMsrRdFn_AmdK7NodeId,
622	kCpumMsrRdFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
623	kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
624	kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
625	kCpumMsrRdFn_AmdK7LoadStoreCfg,
626	kCpumMsrRdFn_AmdK7InstrCacheCfg,
627	kCpumMsrRdFn_AmdK7DataCacheCfg,
628	kCpumMsrRdFn_AmdK7BusUnitCfg,
629	kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
630	kCpumMsrRdFn_AmdFam15hFpuCfg,
631	kCpumMsrRdFn_AmdFam15hDecoderCfg,
632	kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
633	kCpumMsrRdFn_AmdFam15hCombUnitCfg,
634	kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
635	kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
636	kCpumMsrRdFn_AmdFam15hExecUnitCfg,
637	kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
638	kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
639	kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
640	kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
641	kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
642	kCpumMsrRdFn_AmdFam10hIbsOpRip,
643	kCpumMsrRdFn_AmdFam10hIbsOpData,
644	kCpumMsrRdFn_AmdFam10hIbsOpData2,
645	kCpumMsrRdFn_AmdFam10hIbsOpData3,
646	kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
647	kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
648	kCpumMsrRdFn_AmdFam10hIbsCtl,
649	kCpumMsrRdFn_AmdFam14hIbsBrTarget,
650
651	kCpumMsrRdFn_Gim,
652
653	/** End of valid MSR read function indexes. */
654	kCpumMsrRdFn_End
655	} CPUMMSRRDFN;
656
657	/**
658	* MSR write functions.
659	*/
660	typedef enum CPUMMSRWRFN
661	{
662	/** Invalid zero value. */
663	kCpumMsrWrFn_Invalid = 0,
664	/** Writes are ignored, the fWrGpMask is observed though. */
665	kCpumMsrWrFn_IgnoreWrite,
666	/** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
667	kCpumMsrWrFn_ReadOnly,
668	/** Alias to the MSR range starting at the MSR given by
669	* CPUMMSRRANGE::uValue. Must be used in pair with
670	* kCpumMsrRdFn_MsrAlias. */
671	kCpumMsrWrFn_MsrAlias,
672
673	kCpumMsrWrFn_Ia32P5McAddr,
674	kCpumMsrWrFn_Ia32P5McType,
675	kCpumMsrWrFn_Ia32TimestampCounter,
676	kCpumMsrWrFn_Ia32ApicBase,
677	kCpumMsrWrFn_Ia32FeatureControl,
678	kCpumMsrWrFn_Ia32BiosSignId,
679	kCpumMsrWrFn_Ia32BiosUpdateTrigger,
680	kCpumMsrWrFn_Ia32SmmMonitorCtl,
681	kCpumMsrWrFn_Ia32PmcN,
682	kCpumMsrWrFn_Ia32MonitorFilterLineSize,
683	kCpumMsrWrFn_Ia32MPerf,
684	kCpumMsrWrFn_Ia32APerf,
685	kCpumMsrWrFn_Ia32MtrrPhysBaseN, /*< Takes register number. /
686	kCpumMsrWrFn_Ia32MtrrPhysMaskN, /*< Takes register number. /
687	kCpumMsrWrFn_Ia32MtrrFixed, /*< Takes CPUMCPU offset. /
688	kCpumMsrWrFn_Ia32MtrrDefType,
689	kCpumMsrWrFn_Ia32Pat,
690	kCpumMsrWrFn_Ia32SysEnterCs,
691	kCpumMsrWrFn_Ia32SysEnterEsp,
692	kCpumMsrWrFn_Ia32SysEnterEip,
693	kCpumMsrWrFn_Ia32McgStatus,
694	kCpumMsrWrFn_Ia32McgCtl,
695	kCpumMsrWrFn_Ia32DebugCtl,
696	kCpumMsrWrFn_Ia32SmrrPhysBase,
697	kCpumMsrWrFn_Ia32SmrrPhysMask,
698	kCpumMsrWrFn_Ia32PlatformDcaCap,
699	kCpumMsrWrFn_Ia32Dca0Cap,
700	kCpumMsrWrFn_Ia32PerfEvtSelN, /*< Range value indicates the register number. /
701	kCpumMsrWrFn_Ia32PerfStatus,
702	kCpumMsrWrFn_Ia32PerfCtl,
703	kCpumMsrWrFn_Ia32FixedCtrN, /*< Takes register number of start of range. /
704	kCpumMsrWrFn_Ia32PerfCapabilities,
705	kCpumMsrWrFn_Ia32FixedCtrCtrl,
706	kCpumMsrWrFn_Ia32PerfGlobalStatus,
707	kCpumMsrWrFn_Ia32PerfGlobalCtrl,
708	kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
709	kCpumMsrWrFn_Ia32PebsEnable,
710	kCpumMsrWrFn_Ia32ClockModulation,
711	kCpumMsrWrFn_Ia32ThermInterrupt,
712	kCpumMsrWrFn_Ia32ThermStatus,
713	kCpumMsrWrFn_Ia32Therm2Ctl,
714	kCpumMsrWrFn_Ia32MiscEnable,
715	kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /*< Takes bank number. /
716	kCpumMsrWrFn_Ia32McNCtl2, /*< Takes register number of start of range. /
717	kCpumMsrWrFn_Ia32DsArea,
718	kCpumMsrWrFn_Ia32TscDeadline,
719	kCpumMsrWrFn_Ia32X2ApicN,
720	kCpumMsrWrFn_Ia32DebugInterface,
721
722	kCpumMsrWrFn_Amd64Efer,
723	kCpumMsrWrFn_Amd64SyscallTarget,
724	kCpumMsrWrFn_Amd64LongSyscallTarget,
725	kCpumMsrWrFn_Amd64CompSyscallTarget,
726	kCpumMsrWrFn_Amd64SyscallFlagMask,
727	kCpumMsrWrFn_Amd64FsBase,
728	kCpumMsrWrFn_Amd64GsBase,
729	kCpumMsrWrFn_Amd64KernelGsBase,
730	kCpumMsrWrFn_Amd64TscAux,
731	kCpumMsrWrFn_IntelEblCrPowerOn,
732	kCpumMsrWrFn_IntelP4EbcHardPowerOn,
733	kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
734	kCpumMsrWrFn_IntelP4EbcFrequencyId,
735	kCpumMsrWrFn_IntelFlexRatio,
736	kCpumMsrWrFn_IntelPkgCStConfigControl,
737	kCpumMsrWrFn_IntelPmgIoCaptureBase,
738	kCpumMsrWrFn_IntelLastBranchFromToN,
739	kCpumMsrWrFn_IntelLastBranchFromN,
740	kCpumMsrWrFn_IntelLastBranchToN,
741	kCpumMsrWrFn_IntelLastBranchTos,
742	kCpumMsrWrFn_IntelBblCrCtl,
743	kCpumMsrWrFn_IntelBblCrCtl3,
744	kCpumMsrWrFn_IntelI7TemperatureTarget,
745	kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /*< Takes register number. /
746	kCpumMsrWrFn_IntelI7MiscPwrMgmt,
747	kCpumMsrWrFn_IntelP6CrN,
748	kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
749	kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
750	kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
751	kCpumMsrWrFn_IntelI7SandyAesNiCtl,
752	kCpumMsrWrFn_IntelI7TurboRatioLimit,
753	kCpumMsrWrFn_IntelI7LbrSelect,
754	kCpumMsrWrFn_IntelI7SandyErrorControl,
755	kCpumMsrWrFn_IntelI7PowerCtl,
756	kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
757	kCpumMsrWrFn_IntelI7PebsLdLat,
758	kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
759	kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
760	kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /*< R/O but found writable bits on a Silvermont CPU here. /
761	kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
762	kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /*< R/O but found writable bits on a Silvermont CPU here. /
763	kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
764	kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
765	kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
766	kCpumMsrWrFn_IntelI7RaplPp0Policy,
767	kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
768	kCpumMsrWrFn_IntelI7RaplPp1Policy,
769	kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
770	kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
771	kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
772	kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
773	kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
774	kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
775	kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
776	kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
777	kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
778	kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
779	kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
780	kCpumMsrWrFn_IntelCore1ExtConfig,
781	kCpumMsrWrFn_IntelCore1DtsCalControl,
782	kCpumMsrWrFn_IntelCore2PeciControl,
783
784	kCpumMsrWrFn_P6LastIntFromIp,
785	kCpumMsrWrFn_P6LastIntToIp,
786
787	kCpumMsrWrFn_AmdFam15hTscRate,
788	kCpumMsrWrFn_AmdFam15hLwpCfg,
789	kCpumMsrWrFn_AmdFam15hLwpCbAddr,
790	kCpumMsrWrFn_AmdFam10hMc4MiscN,
791	kCpumMsrWrFn_AmdK8PerfCtlN,
792	kCpumMsrWrFn_AmdK8PerfCtrN,
793	kCpumMsrWrFn_AmdK8SysCfg,
794	kCpumMsrWrFn_AmdK8HwCr,
795	kCpumMsrWrFn_AmdK8IorrBaseN,
796	kCpumMsrWrFn_AmdK8IorrMaskN,
797	kCpumMsrWrFn_AmdK8TopOfMemN,
798	kCpumMsrWrFn_AmdK8NbCfg1,
799	kCpumMsrWrFn_AmdK8McXcptRedir,
800	kCpumMsrWrFn_AmdK8CpuNameN,
801	kCpumMsrWrFn_AmdK8HwThermalCtrl,
802	kCpumMsrWrFn_AmdK8SwThermalCtrl,
803	kCpumMsrWrFn_AmdK8FidVidControl,
804	kCpumMsrWrFn_AmdK8McCtlMaskN,
805	kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
806	kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
807	kCpumMsrWrFn_AmdK8IntPendingMessage,
808	kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
809	kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
810	kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
811	kCpumMsrWrFn_AmdFam10hPStateControl,
812	kCpumMsrWrFn_AmdFam10hPStateStatus,
813	kCpumMsrWrFn_AmdFam10hPStateN,
814	kCpumMsrWrFn_AmdFam10hCofVidControl,
815	kCpumMsrWrFn_AmdFam10hCofVidStatus,
816	kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
817	kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
818	kCpumMsrWrFn_AmdK8SmmBase,
819	kCpumMsrWrFn_AmdK8SmmAddr,
820	kCpumMsrWrFn_AmdK8SmmMask,
821	kCpumMsrWrFn_AmdK8VmCr,
822	kCpumMsrWrFn_AmdK8IgnNe,
823	kCpumMsrWrFn_AmdK8SmmCtl,
824	kCpumMsrWrFn_AmdK8VmHSavePa,
825	kCpumMsrWrFn_AmdFam10hVmLockKey,
826	kCpumMsrWrFn_AmdFam10hSmmLockKey,
827	kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
828	kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
829	kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
830	kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
831	kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
832	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
833	kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
834	kCpumMsrWrFn_AmdK7MicrocodeCtl,
835	kCpumMsrWrFn_AmdK7ClusterIdMaybe,
836	kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
837	kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
838	kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
839	kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
840	kCpumMsrWrFn_AmdK8PatchLoader,
841	kCpumMsrWrFn_AmdK7DebugStatusMaybe,
842	kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
843	kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
844	kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
845	kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
846	kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
847	kCpumMsrWrFn_AmdK7NodeId,
848	kCpumMsrWrFn_AmdK7DrXAddrMaskN, /*< Takes register index. /
849	kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
850	kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
851	kCpumMsrWrFn_AmdK7LoadStoreCfg,
852	kCpumMsrWrFn_AmdK7InstrCacheCfg,
853	kCpumMsrWrFn_AmdK7DataCacheCfg,
854	kCpumMsrWrFn_AmdK7BusUnitCfg,
855	kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
856	kCpumMsrWrFn_AmdFam15hFpuCfg,
857	kCpumMsrWrFn_AmdFam15hDecoderCfg,
858	kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
859	kCpumMsrWrFn_AmdFam15hCombUnitCfg,
860	kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
861	kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
862	kCpumMsrWrFn_AmdFam15hExecUnitCfg,
863	kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
864	kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
865	kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
866	kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
867	kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
868	kCpumMsrWrFn_AmdFam10hIbsOpRip,
869	kCpumMsrWrFn_AmdFam10hIbsOpData,
870	kCpumMsrWrFn_AmdFam10hIbsOpData2,
871	kCpumMsrWrFn_AmdFam10hIbsOpData3,
872	kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
873	kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
874	kCpumMsrWrFn_AmdFam10hIbsCtl,
875	kCpumMsrWrFn_AmdFam14hIbsBrTarget,
876
877	kCpumMsrWrFn_Gim,
878
879	/** End of valid MSR write function indexes. */
880	kCpumMsrWrFn_End
881	} CPUMMSRWRFN;
882
883	/**
884	* MSR range.
885	*/
886	typedef struct CPUMMSRRANGE
887	{
888	/** The first MSR. [0] */
889	uint32_t uFirst;
890	/** The last MSR. [4] */
891	uint32_t uLast;
892	/** The read function (CPUMMSRRDFN). [8] */
893	uint16_t enmRdFn;
894	/** The write function (CPUMMSRWRFN). [10] */
895	uint16_t enmWrFn;
896	/** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
897	* UINT16_MAX if not used by the read and write functions. [12] */
898	uint16_t offCpumCpu;
899	/** Reserved for future hacks. [14] */
900	uint16_t fReserved;
901	/** The init/read value. [16]
902	* When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
903	* offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
904	* offset into CPUM. */
905	uint64_t uValue;
906	/** The bits to ignore when writing. [24] */
907	uint64_t fWrIgnMask;
908	/** The bits that will cause a GP(0) when writing. [32]
909	* This is always checked prior to calling the write function. Using
910	* UINT64_MAX effectively marks the MSR as read-only. */
911	uint64_t fWrGpMask;
912	/** The register name, if applicable. [40] */
913	char szName[56];
914
915	#ifdef VBOX_WITH_STATISTICS
916	/** The number of reads. */
917	STAMCOUNTER cReads;
918	/** The number of writes. */
919	STAMCOUNTER cWrites;
920	/** The number of times ignored bits were written. */
921	STAMCOUNTER cIgnoredBits;
922	/** The number of GPs generated. */
923	STAMCOUNTER cGps;
924	#endif
925	} CPUMMSRRANGE;
926	#ifndef VBOX_FOR_DTRACE_LIB
927	# ifdef VBOX_WITH_STATISTICS
928	AssertCompileSize(CPUMMSRRANGE, 128);
929	# else
930	AssertCompileSize(CPUMMSRRANGE, 96);
931	# endif
932	#endif
933	/** Pointer to an MSR range. */
934	typedef CPUMMSRRANGE *PCPUMMSRRANGE;
935	/** Pointer to a const MSR range. */
936	typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
937
938
939	/**
940	* CPU features and quirks.
941	* This is mostly exploded CPUID info.
942	*/
943	typedef struct CPUMFEATURES
944	{
945	/** The CPU vendor (CPUMCPUVENDOR). */
946	uint8_t enmCpuVendor;
947	/** The CPU family. */
948	uint8_t uFamily;
949	/** The CPU model. */
950	uint8_t uModel;
951	/** The CPU stepping. */
952	uint8_t uStepping;
953	/** The microarchitecture. */
954	#ifndef VBOX_FOR_DTRACE_LIB
955	CPUMMICROARCH enmMicroarch;
956	#else
957	uint32_t enmMicroarch;
958	#endif
959	/** The maximum physical address with of the CPU. */
960	uint8_t cMaxPhysAddrWidth;
961	/** Alignment padding. */
962	uint8_t abPadding[1];
963	/** Max size of the extended state (or FPU state if no XSAVE). */
964	uint16_t cbMaxExtendedState;
965
966	/** Supports MSRs. */
967	uint32_t fMsr : 1;
968	/** Supports the page size extension (4/2 MB pages). */
969	uint32_t fPse : 1;
970	/** Supports 36-bit page size extension (4 MB pages can map memory above
971	* 4GB). */
972	uint32_t fPse36 : 1;
973	/** Supports physical address extension (PAE). */
974	uint32_t fPae : 1;
975	/** Page attribute table (PAT) support (page level cache control). */
976	uint32_t fPat : 1;
977	/** Supports the FXSAVE and FXRSTOR instructions. */
978	uint32_t fFxSaveRstor : 1;
979	/** Supports the XSAVE and XRSTOR instructions. */
980	uint32_t fXSaveRstor : 1;
981	/** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
982	uint32_t fOpSysXSaveRstor : 1;
983	/** Supports MMX. */
984	uint32_t fMmx : 1;
985	/** Supports AMD extensions to MMX instructions. */
986	uint32_t fAmdMmxExts : 1;
987	/** Supports SSE. */
988	uint32_t fSse : 1;
989	/** Supports SSE2. */
990	uint32_t fSse2 : 1;
991	/** Supports SSE3. */
992	uint32_t fSse3 : 1;
993	/** Supports SSSE3. */
994	uint32_t fSsse3 : 1;
995	/** Supports SSE4.1. */
996	uint32_t fSse41 : 1;
997	/** Supports SSE4.2. */
998	uint32_t fSse42 : 1;
999	/** Supports AVX. */
1000	uint32_t fAvx : 1;
1001	/** Supports AVX2. */
1002	uint32_t fAvx2 : 1;
1003	/** Supports AVX512 foundation. */
1004	uint32_t fAvx512Foundation : 1;
1005	/** Supports RDTSC. */
1006	uint32_t fTsc : 1;
1007	/** Intel SYSENTER/SYSEXIT support */
1008	uint32_t fSysEnter : 1;
1009	/** First generation APIC. */
1010	uint32_t fApic : 1;
1011	/** Second generation APIC. */
1012	uint32_t fX2Apic : 1;
1013	/** Hypervisor present. */
1014	uint32_t fHypervisorPresent : 1;
1015	/** MWAIT & MONITOR instructions supported. */
1016	uint32_t fMonitorMWait : 1;
1017	/** MWAIT Extensions present. */
1018	uint32_t fMWaitExtensions : 1;
1019	/** Supports CMPXCHG16B in 64-bit mode. */
1020	uint32_t fMovCmpXchg16b : 1;
1021	/** Supports CLFLUSH. */
1022	uint32_t fClFlush : 1;
1023	/** Supports CLFLUSHOPT. */
1024	uint32_t fClFlushOpt : 1;
1025
1026	/** Supports AMD 3DNow instructions. */
1027	uint32_t f3DNow : 1;
1028	/** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1029	uint32_t f3DNowPrefetch : 1;
1030
1031	/** AMD64: Supports long mode. */
1032	uint32_t fLongMode : 1;
1033	/** AMD64: SYSCALL/SYSRET support. */
1034	uint32_t fSysCall : 1;
1035	/** AMD64: No-execute page table bit. */
1036	uint32_t fNoExecute : 1;
1037	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1038	uint32_t fLahfSahf : 1;
1039	/** AMD64: Supports RDTSCP. */
1040	uint32_t fRdTscP : 1;
1041	/** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1042	uint32_t fMovCr8In32Bit : 1;
1043	/** AMD64: Supports XOP (similar to VEX3/AVX). */
1044	uint32_t fXop : 1;
1045
1046	/** Indicates that FPU instruction and data pointers may leak.
1047	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1048	* is only saved and restored if an exception is pending. */
1049	uint32_t fLeakyFxSR : 1;
1050
1051	/** AMD64: Supports AMD SVM. */
1052	uint32_t fSvm : 1;
1053
1054	/** Support for Intel VMX. */
1055	uint32_t fVmx : 1;
1056
1057	/** Alignment padding / reserved for future use. */
1058	uint32_t fPadding : 23;
1059
1060	/** SVM: Supports Nested-paging. */
1061	uint32_t fSvmNestedPaging : 1;
1062	/** SVM: Support LBR (Last Branch Record) virtualization. */
1063	uint32_t fSvmLbrVirt : 1;
1064	/** SVM: Supports SVM lock. */
1065	uint32_t fSvmSvmLock : 1;
1066	/** SVM: Supports Next RIP save. */
1067	uint32_t fSvmNextRipSave : 1;
1068	/** SVM: Supports TSC rate MSR. */
1069	uint32_t fSvmTscRateMsr : 1;
1070	/** SVM: Supports VMCB clean bits. */
1071	uint32_t fSvmVmcbClean : 1;
1072	/** SVM: Supports Flush-by-ASID. */
1073	uint32_t fSvmFlusbByAsid : 1;
1074	/** SVM: Supports decode assist. */
1075	uint32_t fSvmDecodeAssists : 1;
1076	/** SVM: Supports Pause filter. */
1077	uint32_t fSvmPauseFilter : 1;
1078	/** SVM: Supports Pause filter threshold. */
1079	uint32_t fSvmPauseFilterThreshold : 1;
1080	/** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1081	uint32_t fSvmAvic : 1;
1082	/** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1083	uint32_t fSvmVirtVmsaveVmload : 1;
1084	/** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1085	uint32_t fSvmVGif : 1;
1086	/** SVM: Padding / reserved for future features. */
1087	uint32_t fSvmPadding0 : 19;
1088	/** SVM: Maximum supported ASID. */
1089	uint32_t uSvmMaxAsid;
1090
1091	/** @todo VMX features. */
1092	uint32_t auPadding[1];
1093	} CPUMFEATURES;
1094	#ifndef VBOX_FOR_DTRACE_LIB
1095	AssertCompileSize(CPUMFEATURES, 32);
1096	#endif
1097	/** Pointer to a CPU feature structure. */
1098	typedef CPUMFEATURES *PCPUMFEATURES;
1099	/** Pointer to a const CPU feature structure. */
1100	typedef CPUMFEATURES const *PCCPUMFEATURES;
1101
1102
1103	#ifndef VBOX_FOR_DTRACE_LIB
1104
1105	/** @name Guest Register Getters.
1106	* @{ */
1107	VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
1108	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1109	VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
1110	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu);
1111	VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t pGCPtrBase, uint32_t pcbLimit);
1112	VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu);
1113	VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu);
1114	VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu);
1115	VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu);
1116	VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu);
1117	VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
1118	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu);
1119	VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu);
1120	VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu);
1121	VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu);
1122	VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu);
1123	VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu);
1124	VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu);
1125	VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu);
1126	VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu);
1127	VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu);
1128	VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu);
1129	VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu);
1130	VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu);
1131	VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu);
1132	VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu);
1133	VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu);
1134	VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu);
1135	VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1136	VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1137	VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu);
1138	VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu);
1139	VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu);
1140	VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu);
1141	VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu);
1142	VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu);
1143	VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1144	VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t iSubLeaf,
1145	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
1146	VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu);
1147	VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
1148	VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
1149	VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1150	VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1151	/** @} */
1152
1153	/** @name Guest Register Setters.
1154	* @{ */
1155	VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1156	VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1157	VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1158	VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1159	VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
1160	VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1161	VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1162	VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1163	VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
1164	VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
1165	VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
1166	VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
1167	VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1168	VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
1169	VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
1170	VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPU pVCpu, uint64_t uNewValue);
1171	VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1172	VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1173	VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1174	VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1175	VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1176	VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1177	VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1178	VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1179	VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1180	VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1181	VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1182	VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1183	VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1184	VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1185	VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1186	VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1187	VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1188	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1189	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1190	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1191	VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1192	VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1193	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
1194	VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
1195	VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
1196	VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
1197	/** @} */
1198
1199
1200	/** @name Misc Guest Predicate Functions.
1201	* @{ */
1202	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVMCPU pVCpu);
1203	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVMCPU pVCpu);
1204	VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1205	VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu);
1206	VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
1207	VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
1208	VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
1209	VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu);
1210	VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
1211	VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
1212	VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
1213	VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu);
1214	VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu);
1215	VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
1216	/** @} */
1217
1218	/** @name Nested Hardware-Virtualization Helpers.
1219	* @{ */
1220	VMM_INT_DECL(bool) CPUMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx);
1221	VMM_INT_DECL(bool) CPUMCanSvmNstGstTakeVirtIntr(PCCPUMCTX pCtx);
1222	VMM_INT_DECL(uint8_t) CPUMGetSvmNstGstInterrupt(PCCPUMCTX pCtx);
1223	VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPU pVCpu, PCPUMCTX pCtx);
1224	VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1225	VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PVMCPU pVCpu, uint64_t uTicks);
1226	/** @} */
1227
1228	#ifndef IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS
1229
1230	/**
1231	* Tests if the guest is running in real mode or not.
1232	*
1233	* @returns true if in real mode, otherwise false.
1234	* @param pCtx Current CPU context.
1235	*/
1236	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
1237	{
1238	return !(pCtx->cr0 & X86_CR0_PE);
1239	}
1240
1241	/**
1242	* Tests if the guest is running in real or virtual 8086 mode.
1243	*
1244	* @returns @c true if it is, @c false if not.
1245	* @param pCtx Current CPU context.
1246	*/
1247	DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
1248	{
1249	return !(pCtx->cr0 & X86_CR0_PE)
1250	\|\| pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1251	}
1252
1253	/**
1254	* Tests if the guest is running in virtual 8086 mode.
1255	*
1256	* @returns @c true if it is, @c false if not.
1257	* @param pCtx Current CPU context.
1258	*/
1259	DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
1260	{
1261	return (pCtx->eflags.Bits.u1VM == 1);
1262	}
1263
1264	/**
1265	* Tests if the guest is running in paged protected or not.
1266	*
1267	* @returns true if in paged protected mode, otherwise false.
1268	* @param pCtx Current CPU context.
1269	*/
1270	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1271	{
1272	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
1273	}
1274
1275	/**
1276	* Tests if the guest is running in long mode or not.
1277	*
1278	* @returns true if in long mode, otherwise false.
1279	* @param pCtx Current CPU context.
1280	*/
1281	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
1282	{
1283	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1284	}
1285
1286	VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1287
1288	/**
1289	* Tests if the guest is running in 64 bits mode or not.
1290	*
1291	* @returns true if in 64 bits protected mode, otherwise false.
1292	* @param pCtx Current CPU context.
1293	*/
1294	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1295	{
1296	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1297	return false;
1298	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1299	return CPUMIsGuestIn64BitCodeSlow(pCtx);
1300	return pCtx->cs.Attr.n.u1Long;
1301	}
1302
1303	/**
1304	* Tests if the guest has paging enabled or not.
1305	*
1306	* @returns true if paging is enabled, otherwise false.
1307	* @param pCtx Current CPU context.
1308	*/
1309	DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
1310	{
1311	return !!(pCtx->cr0 & X86_CR0_PG);
1312	}
1313
1314	/**
1315	* Tests if the guest is running in PAE mode or not.
1316	*
1317	* @returns true if in PAE mode, otherwise false.
1318	* @param pCtx Current CPU context.
1319	*/
1320	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
1321	{
1322	/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1323	than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1324	return ( (pCtx->cr4 & X86_CR4_PAE)
1325	&& CPUMIsGuestPagingEnabledEx(pCtx)
1326	&& !(pCtx->msrEFER & MSR_K6_EFER_LMA));
1327	}
1328
1329	/**
1330	* Tests is if the guest has AMD SVM enabled or not.
1331	*
1332	* @returns true if SMV is enabled, otherwise false.
1333	* @param pCtx Current CPU context.
1334	*/
1335	DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1336	{
1337	return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1338	}
1339
1340	#ifndef IN_RC
1341	/**
1342	* Checks if the guest VMCB has the specified ctrl/instruction intercept active.
1343	*
1344	* @returns @c true if in intercept is set, @c false otherwise.
1345	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1346	* @param pCtx Pointer to the context.
1347	* @param fIntercept The SVM control/instruction intercept, see
1348	* SVM_CTRL_INTERCEPT_*.
1349	*/
1350	DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
1351	{
1352	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1353	if (!pVmcb)
1354	return false;
1355	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1356	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fIntercept);
1357	return HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, fIntercept);
1358	}
1359
1360	/**
1361	* Checks if the guest VMCB has the specified CR read intercept active.
1362	*
1363	* @returns @c true if in intercept is set, @c false otherwise.
1364	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1365	* @param pCtx Pointer to the context.
1366	* @param uCr The CR register number (0 to 15).
1367	*/
1368	DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1369	{
1370	Assert(uCr < 16);
1371	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1372	if (!pVmcb)
1373	return false;
1374	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1375	return RT_BOOL(pVmcb->ctrl.u16InterceptRdCRx & (UINT16_C(1) << uCr));
1376	return HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr);
1377	}
1378
1379	/**
1380	* Checks if the guest VMCB has the specified CR write intercept active.
1381	*
1382	* @returns @c true if in intercept is set, @c false otherwise.
1383	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1384	* @param pCtx Pointer to the context.
1385	* @param uCr The CR register number (0 to 15).
1386	*/
1387	DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
1388	{
1389	Assert(uCr < 16);
1390	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1391	if (!pVmcb)
1392	return false;
1393	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1394	return RT_BOOL(pVmcb->ctrl.u16InterceptWrCRx & (UINT16_C(1) << uCr));
1395	return HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr);
1396	}
1397
1398	/**
1399	* Checks if the guest VMCB has the specified DR read intercept active.
1400	*
1401	* @returns @c true if in intercept is set, @c false otherwise.
1402	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1403	* @param pCtx Pointer to the context.
1404	* @param uDr The DR register number (0 to 15).
1405	*/
1406	DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1407	{
1408	Assert(uDr < 16);
1409	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1410	if (!pVmcb)
1411	return false;
1412	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1413	return RT_BOOL(pVmcb->ctrl.u16InterceptRdDRx & (UINT16_C(1) << uDr));
1414	return HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr);
1415	}
1416
1417	/**
1418	* Checks if the guest VMCB has the specified DR write intercept active.
1419	*
1420	* @returns @c true if in intercept is set, @c false otherwise.
1421	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1422	* @param pCtx Pointer to the context.
1423	* @param uDr The DR register number (0 to 15).
1424	*/
1425	DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
1426	{
1427	Assert(uDr < 16);
1428	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1429	if (!pVmcb)
1430	return false;
1431	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1432	return RT_BOOL(pVmcb->ctrl.u16InterceptWrDRx & (UINT16_C(1) << uDr));
1433	return HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr);
1434	}
1435
1436	/**
1437	* Checks if the guest VMCB has the specified exception intercept active.
1438	*
1439	* @returns @c true if in intercept is active, @c false otherwise.
1440	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1441	* @param pCtx Pointer to the context.
1442	* @param uVector The exception / interrupt vector.
1443	*/
1444	DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
1445	{
1446	Assert(uVector < 32);
1447	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1448	if (!pVmcb)
1449	return false;
1450	if (!pCtx->hwvirt.svm.fHMCachedVmcb)
1451	return RT_BOOL(pVmcb->ctrl.u32InterceptXcpt & (UINT32_C(1) << uVector));
1452	return HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector);
1453	}
1454	#endif /* !IN_RC */
1455
1456	/**
1457	* Checks if we are executing inside an SVM nested hardware-virtualized guest.
1458	*
1459	* @returns @c true if in SVM nested-guest mode, @c false otherwise.
1460	* @param pCtx Pointer to the context.
1461	*/
1462	DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
1463	{
1464	/*
1465	* With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
1466	* See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
1467	*/
1468	#ifndef IN_RC
1469	PCSVMVMCB pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1470	return pVmcb && (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
1471	#else
1472	NOREF(pCtx);
1473	return false;
1474	#endif
1475	}
1476
1477	/**
1478	* Checks if we are executing inside a VMX nested hardware-virtualized guest.
1479	*
1480	* @returns @c true if in VMX nested-guest mode, @c false otherwise.
1481	* @param pCtx Pointer to the context.
1482	*/
1483	DECLINLINE(bool) CPUMIsGuestInVmxNestedHwVirtMode(PCCPUMCTX pCtx)
1484	{
1485	/** @todo Intel. */
1486	NOREF(pCtx);
1487	return false;
1488	}
1489
1490	/**
1491	* Checks if we are executing inside a nested hardware-virtualized guest.
1492	*
1493	* @returns @c true if in SVM/VMX nested-guest mode, @c false otherwise.
1494	* @param pCtx Pointer to the context.
1495	*/
1496	DECLINLINE(bool) CPUMIsGuestInNestedHwVirtMode(PCCPUMCTX pCtx)
1497	{
1498	return CPUMIsGuestInSvmNestedHwVirtMode(pCtx) \|\| CPUMIsGuestInVmxNestedHwVirtMode(pCtx);
1499	}
1500	#endif /* IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS */
1501
1502	/** @} */
1503
1504
1505	/** @name Hypervisor Register Getters.
1506	* @{ */
1507	VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu);
1508	VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu);
1509	VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu);
1510	VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu);
1511	VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu);
1512	VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu);
1513	#if 0 /* these are not correct. */
1514	VMMDECL(uint32_t) CPUMGetHyperCR0(PVMCPU pVCpu);
1515	VMMDECL(uint32_t) CPUMGetHyperCR2(PVMCPU pVCpu);
1516	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1517	VMMDECL(uint32_t) CPUMGetHyperCR4(PVMCPU pVCpu);
1518	#endif
1519	/** This register is only saved on fatal traps. */
1520	VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu);
1521	VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu);
1522	/** This register is only saved on fatal traps. */
1523	VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu);
1524	/** This register is only saved on fatal traps. */
1525	VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu);
1526	VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu);
1527	VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu);
1528	VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu);
1529	VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu);
1530	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu);
1531	VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu);
1532	VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu);
1533	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1534	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
1535	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu);
1536	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
1537	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
1538	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
1539	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
1540	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
1541	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
1542	VMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
1543	VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
1544	/** @} */
1545
1546	/** @name Hypervisor Register Setters.
1547	* @{ */
1548	VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1549	VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
1550	VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
1551	VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
1552	VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
1553	VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
1554	VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
1555	VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
1556	VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
1557	VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
1558	VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
1559	VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
1560	VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
1561	VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
1562	VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
1563	VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
1564	VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
1565	VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
1566	VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
1567	VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
1568	VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
1569	VMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1570	VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
1571	/** @} */
1572
1573	VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
1574	VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
1575	VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu);
1576	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
1577	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
1578	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
1579	VMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu);
1580	VMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, int rc);
1581	VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu);
1582	VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
1583
1584	/** @name Changed flags.
1585	* These flags are used to keep track of which important register that
1586	* have been changed since last they were reset. The only one allowed
1587	* to clear them is REM!
1588	* @{
1589	*/
1590	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
1591	#define CPUM_CHANGED_CR0 RT_BIT(1)
1592	#define CPUM_CHANGED_CR4 RT_BIT(2)
1593	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
1594	#define CPUM_CHANGED_CR3 RT_BIT(4)
1595	#define CPUM_CHANGED_GDTR RT_BIT(5)
1596	#define CPUM_CHANGED_IDTR RT_BIT(6)
1597	#define CPUM_CHANGED_LDTR RT_BIT(7)
1598	#define CPUM_CHANGED_TR RT_BIT(8) /*@< Currently unused. /
1599	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
1600	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /*@< Currently unused. /
1601	#define CPUM_CHANGED_CPUID RT_BIT(11)
1602	#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
1603	\| CPUM_CHANGED_CR0 \
1604	\| CPUM_CHANGED_CR4 \
1605	\| CPUM_CHANGED_GLOBAL_TLB_FLUSH \
1606	\| CPUM_CHANGED_CR3 \
1607	\| CPUM_CHANGED_GDTR \
1608	\| CPUM_CHANGED_IDTR \
1609	\| CPUM_CHANGED_LDTR \
1610	\| CPUM_CHANGED_TR \
1611	\| CPUM_CHANGED_SYSENTER_MSR \
1612	\| CPUM_CHANGED_HIDDEN_SEL_REGS \
1613	\| CPUM_CHANGED_CPUID )
1614	/** @} */
1615
1616	VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
1617	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
1618	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
1619	VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
1620	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
1621	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
1622	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
1623	VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
1624	VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
1625	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
1626	VMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
1627	VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
1628	VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
1629	VMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
1630	VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
1631	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
1632	VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
1633	VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
1634	VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
1635	VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
1636	VMMDECL(int) CPUMQueryValidatedGuestEfer(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
1637	uint64_t *puValidEfer);
1638	VMMDECL(void) CPUMSetGuestMsrEferNoCheck(PVMCPU pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
1639
1640
1641	/** @name Typical scalable bus frequency values.
1642	* @{ */
1643	/** Special internal value indicating that we don't know the frequency.
1644	* @internal */
1645	#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
1646	#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
1647	#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
1648	#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
1649	#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
1650	#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
1651	#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
1652	#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
1653	/** @} */
1654
1655
1656	#ifdef IN_RING3
1657	/** @defgroup grp_cpum_r3 The CPUM ring-3 API
1658	* @{
1659	*/
1660
1661	VMMR3DECL(int) CPUMR3Init(PVM pVM);
1662	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1663	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM);
1664	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
1665	VMMR3DECL(int) CPUMR3Term(PVM pVM);
1666	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
1667	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1668	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
1669	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
1670	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
1671
1672	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
1673	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
1674	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
1675	uint8_t bModel, uint8_t bStepping);
1676	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
1677	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves);
1678	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
1679	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
1680	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1681	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
1682	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
1683
1684	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
1685
1686	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
1687	/** @name APIs for the CPUID raw-mode patch (legacy).
1688	* @{ */
1689	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM);
1690	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM);
1691	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM);
1692	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM);
1693	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM);
1694	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM);
1695	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM);
1696	/** @} */
1697	# endif
1698
1699	/** @} */
1700	#endif /* IN_RING3 */
1701
1702	#ifdef IN_RC
1703	/** @defgroup grp_cpum_rc The CPUM Raw-mode Context API
1704	* @{
1705	*/
1706
1707	/**
1708	* Calls a guest trap/interrupt handler directly
1709	*
1710	* Assumes a trap stack frame has already been setup on the guest's stack!
1711	* This function does not return!
1712	*
1713	* @param pRegFrame Original trap/interrupt context
1714	* @param selCS Code selector of handler
1715	* @param pHandler GC virtual address of handler
1716	* @param eflags Callee's EFLAGS
1717	* @param selSS Stack selector for handler
1718	* @param pEsp Stack address for handler
1719	*/
1720	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
1721	uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1722
1723	/**
1724	* Call guest V86 code directly.
1725	*
1726	* This function does not return!
1727	*
1728	* @param pRegFrame Original trap/interrupt context
1729	*/
1730	DECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1731
1732	VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu);
1733	VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
1734	#ifdef VBOX_WITH_RAW_RING1
1735	VMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
1736	#endif
1737	VMMRCDECL(void) CPUMRCProcessForceFlag(PVMCPU pVCpu);
1738
1739	/** @} */
1740	#endif /* IN_RC */
1741
1742	#ifdef IN_RING0
1743	/** @defgroup grp_cpum_r0 The CPUM ring-0 API
1744	* @{
1745	*/
1746	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
1747	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
1748	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM);
1749	DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPU pVCpu);
1750	DECLASM(void) CPUMR0TouchHostFpu(void);
1751	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu);
1752	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu);
1753	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu);
1754	VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
1755	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
1756	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
1757
1758	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
1759	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
1760	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1761	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet);
1762	#endif
1763
1764	/** @} */
1765	#endif /* IN_RING0 */
1766
1767	/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
1768	* @{
1769	*/
1770	VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPU pVCpu);
1771	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPU pVCpu);
1772	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPU pVCpu);
1773	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPU pVCpu);
1774	VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPU pVCpu);
1775	/** @} */
1776
1777
1778	#endif /* !VBOX_FOR_DTRACE_LIB */
1779	/** @} */
1780	RT_C_DECLS_END
1781
1782
1783	#endif
1784

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source: vbox/trunk/include/VBox/vmm/cpum.h@ 70450

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