VirtualBox

source: vbox/trunk/include/VBox/vmm/cpum.h@ 98703

Last change on this file since 98703 was 98703, checked in by vboxsync, 2 years ago

VMM/{CPUM,IEM}: Implement SHA instruction set extension emulation in IEM and expose it to the guest if available on the host, bugref:9898
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File size: 123.2 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_cpum_h
37#define VBOX_INCLUDED_vmm_cpum_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <iprt/x86.h>
43#include <VBox/types.h>
44#include <VBox/vmm/cpumctx.h>
45#include <VBox/vmm/stam.h>
46#include <VBox/vmm/vmapi.h>
47#include <VBox/vmm/hm_svm.h>
48#include <VBox/vmm/hm_vmx.h>
49
50RT_C_DECLS_BEGIN
51
52/** @defgroup grp_cpum The CPU Monitor / Manager API
53 * @ingroup grp_vmm
54 * @{
55 */
56
57/**
58 * CPUID feature to set or clear.
59 */
60typedef enum CPUMCPUIDFEATURE
61{
62 CPUMCPUIDFEATURE_INVALID = 0,
63 /** The APIC feature bit. (Std+Ext)
64 * Note! There is a per-cpu flag for masking this CPUID feature bit when the
65 * APICBASE.ENABLED bit is zero. So, this feature is only set/cleared
66 * at VM construction time like all the others. This didn't used to be
67 * that way, this is new with 5.1. */
68 CPUMCPUIDFEATURE_APIC,
69 /** The sysenter/sysexit feature bit. (Std) */
70 CPUMCPUIDFEATURE_SEP,
71 /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
72 CPUMCPUIDFEATURE_SYSCALL,
73 /** The PAE feature bit. (Std+Ext) */
74 CPUMCPUIDFEATURE_PAE,
75 /** The NX feature bit. (Ext) */
76 CPUMCPUIDFEATURE_NX,
77 /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
78 CPUMCPUIDFEATURE_LAHF,
79 /** The LONG MODE feature bit. (Ext) */
80 CPUMCPUIDFEATURE_LONG_MODE,
81 /** The x2APIC feature bit. (Std) */
82 CPUMCPUIDFEATURE_X2APIC,
83 /** The RDTSCP feature bit. (Ext) */
84 CPUMCPUIDFEATURE_RDTSCP,
85 /** The Hypervisor Present bit. (Std) */
86 CPUMCPUIDFEATURE_HVP,
87 /** The speculation control feature bits. (StExt) */
88 CPUMCPUIDFEATURE_SPEC_CTRL,
89 /** 32bit hackishness. */
90 CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
91} CPUMCPUIDFEATURE;
92
93/**
94 * CPU Vendor.
95 */
96typedef enum CPUMCPUVENDOR
97{
98 CPUMCPUVENDOR_INVALID = 0,
99 CPUMCPUVENDOR_INTEL,
100 CPUMCPUVENDOR_AMD,
101 CPUMCPUVENDOR_VIA,
102 CPUMCPUVENDOR_CYRIX,
103 CPUMCPUVENDOR_SHANGHAI,
104 CPUMCPUVENDOR_HYGON,
105 CPUMCPUVENDOR_UNKNOWN,
106 /** 32bit hackishness. */
107 CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
108} CPUMCPUVENDOR;
109
110
111/**
112 * X86 and AMD64 CPU microarchitectures and in processor generations.
113 *
114 * @remarks The separation here is sometimes a little bit too finely grained,
115 * and the differences is more like processor generation than micro
116 * arch. This can be useful, so we'll provide functions for getting at
117 * more coarse grained info.
118 */
119typedef enum CPUMMICROARCH
120{
121 kCpumMicroarch_Invalid = 0,
122
123 kCpumMicroarch_Intel_First,
124
125 kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
126 kCpumMicroarch_Intel_80186,
127 kCpumMicroarch_Intel_80286,
128 kCpumMicroarch_Intel_80386,
129 kCpumMicroarch_Intel_80486,
130 kCpumMicroarch_Intel_P5,
131
132 kCpumMicroarch_Intel_P6_Core_Atom_First,
133 kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
134 kCpumMicroarch_Intel_P6_II,
135 kCpumMicroarch_Intel_P6_III,
136
137 kCpumMicroarch_Intel_P6_M_Banias,
138 kCpumMicroarch_Intel_P6_M_Dothan,
139 kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
140
141 kCpumMicroarch_Intel_Core2_First,
142 kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First, /**< 65nm, Merom/Conroe/Kentsfield/Tigerton */
143 kCpumMicroarch_Intel_Core2_Penryn, /**< 45nm, Penryn/Wolfdale/Yorkfield/Harpertown */
144 kCpumMicroarch_Intel_Core2_End,
145
146 kCpumMicroarch_Intel_Core7_First,
147 kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
148 kCpumMicroarch_Intel_Core7_Westmere,
149 kCpumMicroarch_Intel_Core7_SandyBridge,
150 kCpumMicroarch_Intel_Core7_IvyBridge,
151 kCpumMicroarch_Intel_Core7_Haswell,
152 kCpumMicroarch_Intel_Core7_Broadwell,
153 kCpumMicroarch_Intel_Core7_Skylake,
154 kCpumMicroarch_Intel_Core7_KabyLake,
155 kCpumMicroarch_Intel_Core7_CoffeeLake,
156 kCpumMicroarch_Intel_Core7_WhiskeyLake,
157 kCpumMicroarch_Intel_Core7_CascadeLake,
158 kCpumMicroarch_Intel_Core7_CannonLake, /**< Limited 10nm. */
159 kCpumMicroarch_Intel_Core7_CometLake, /**< 10th gen, 14nm desktop + high power mobile. */
160 kCpumMicroarch_Intel_Core7_IceLake, /**< 10th gen, 10nm mobile and some Xeons. Actually 'Sunny Cove' march. */
161 kCpumMicroarch_Intel_Core7_SunnyCove = kCpumMicroarch_Intel_Core7_IceLake,
162 kCpumMicroarch_Intel_Core7_RocketLake, /**< 11th gen, 14nm desktop + high power mobile. Aka 'Cypress Cove', backport of 'Willow Cove' to 14nm. */
163 kCpumMicroarch_Intel_Core7_CypressCove = kCpumMicroarch_Intel_Core7_RocketLake,
164 kCpumMicroarch_Intel_Core7_TigerLake, /**< 11th gen, 10nm mobile. Actually 'Willow Cove' march. */
165 kCpumMicroarch_Intel_Core7_WillowCove = kCpumMicroarch_Intel_Core7_TigerLake,
166 kCpumMicroarch_Intel_Core7_AlderLake, /**< 12th gen, 10nm all platforms(?). */
167 kCpumMicroarch_Intel_Core7_SapphireRapids, /**< 12th? gen, 10nm server? */
168 kCpumMicroarch_Intel_Core7_End,
169
170 kCpumMicroarch_Intel_Atom_First,
171 kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
172 kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
173 kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
174 kCpumMicroarch_Intel_Atom_Silvermont, /**< 22nm */
175 kCpumMicroarch_Intel_Atom_Airmount, /**< 14nm */
176 kCpumMicroarch_Intel_Atom_Goldmont, /**< 14nm */
177 kCpumMicroarch_Intel_Atom_GoldmontPlus, /**< 14nm */
178 kCpumMicroarch_Intel_Atom_Unknown,
179 kCpumMicroarch_Intel_Atom_End,
180
181
182 kCpumMicroarch_Intel_Phi_First,
183 kCpumMicroarch_Intel_Phi_KnightsFerry = kCpumMicroarch_Intel_Phi_First,
184 kCpumMicroarch_Intel_Phi_KnightsCorner,
185 kCpumMicroarch_Intel_Phi_KnightsLanding,
186 kCpumMicroarch_Intel_Phi_KnightsHill,
187 kCpumMicroarch_Intel_Phi_KnightsMill,
188 kCpumMicroarch_Intel_Phi_End,
189
190 kCpumMicroarch_Intel_P6_Core_Atom_End,
191
192 kCpumMicroarch_Intel_NB_First,
193 kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
194 kCpumMicroarch_Intel_NB_Northwood, /**< 130nm */
195 kCpumMicroarch_Intel_NB_Prescott, /**< 90nm */
196 kCpumMicroarch_Intel_NB_Prescott2M, /**< 90nm */
197 kCpumMicroarch_Intel_NB_CedarMill, /**< 65nm */
198 kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
199 kCpumMicroarch_Intel_NB_Unknown,
200 kCpumMicroarch_Intel_NB_End,
201
202 kCpumMicroarch_Intel_Unknown,
203 kCpumMicroarch_Intel_End,
204
205 kCpumMicroarch_AMD_First,
206 kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
207 kCpumMicroarch_AMD_Am386,
208 kCpumMicroarch_AMD_Am486,
209 kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
210 kCpumMicroarch_AMD_K5,
211 kCpumMicroarch_AMD_K6,
212
213 kCpumMicroarch_AMD_K7_First,
214 kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
215 kCpumMicroarch_AMD_K7_Spitfire,
216 kCpumMicroarch_AMD_K7_Thunderbird,
217 kCpumMicroarch_AMD_K7_Morgan,
218 kCpumMicroarch_AMD_K7_Thoroughbred,
219 kCpumMicroarch_AMD_K7_Barton,
220 kCpumMicroarch_AMD_K7_Unknown,
221 kCpumMicroarch_AMD_K7_End,
222
223 kCpumMicroarch_AMD_K8_First,
224 kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
225 kCpumMicroarch_AMD_K8_90nm, /**< 90nm shrink */
226 kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
227 kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
228 kCpumMicroarch_AMD_K8_65nm, /**< 65nm shrink. */
229 kCpumMicroarch_AMD_K8_End,
230
231 kCpumMicroarch_AMD_K10,
232 kCpumMicroarch_AMD_K10_Lion,
233 kCpumMicroarch_AMD_K10_Llano,
234 kCpumMicroarch_AMD_Bobcat,
235 kCpumMicroarch_AMD_Jaguar,
236
237 kCpumMicroarch_AMD_15h_First,
238 kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
239 kCpumMicroarch_AMD_15h_Piledriver,
240 kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
241 kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
242 kCpumMicroarch_AMD_15h_Unknown,
243 kCpumMicroarch_AMD_15h_End,
244
245 kCpumMicroarch_AMD_16h_First,
246 kCpumMicroarch_AMD_16h_End,
247
248 kCpumMicroarch_AMD_Zen_First,
249 kCpumMicroarch_AMD_Zen_Ryzen = kCpumMicroarch_AMD_Zen_First,
250 kCpumMicroarch_AMD_Zen_End,
251
252 kCpumMicroarch_AMD_Unknown,
253 kCpumMicroarch_AMD_End,
254
255 kCpumMicroarch_Hygon_First,
256 kCpumMicroarch_Hygon_Dhyana = kCpumMicroarch_Hygon_First,
257 kCpumMicroarch_Hygon_Unknown,
258 kCpumMicroarch_Hygon_End,
259
260 kCpumMicroarch_VIA_First,
261 kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
262 kCpumMicroarch_Centaur_C2,
263 kCpumMicroarch_Centaur_C3,
264 kCpumMicroarch_VIA_C3_M2,
265 kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
266 kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
267 kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
268 kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
269 kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
270 kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
271 kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
272 kCpumMicroarch_VIA_Isaiah,
273 kCpumMicroarch_VIA_Unknown,
274 kCpumMicroarch_VIA_End,
275
276 kCpumMicroarch_Shanghai_First,
277 kCpumMicroarch_Shanghai_Wudaokou = kCpumMicroarch_Shanghai_First,
278 kCpumMicroarch_Shanghai_Unknown,
279 kCpumMicroarch_Shanghai_End,
280
281 kCpumMicroarch_Cyrix_First,
282 kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
283 kCpumMicroarch_Cyrix_M1,
284 kCpumMicroarch_Cyrix_MediaGX,
285 kCpumMicroarch_Cyrix_MediaGXm,
286 kCpumMicroarch_Cyrix_M2,
287 kCpumMicroarch_Cyrix_Unknown,
288 kCpumMicroarch_Cyrix_End,
289
290 kCpumMicroarch_NEC_First,
291 kCpumMicroarch_NEC_V20 = kCpumMicroarch_NEC_First,
292 kCpumMicroarch_NEC_V30,
293 kCpumMicroarch_NEC_End,
294
295 kCpumMicroarch_Unknown,
296
297 kCpumMicroarch_32BitHack = 0x7fffffff
298} CPUMMICROARCH;
299
300
301/** Predicate macro for catching netburst CPUs. */
302#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
303 ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
304
305/** Predicate macro for catching Core7 CPUs. */
306#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
307 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
308
309/** Predicate macro for catching Core 2 CPUs. */
310#define CPUMMICROARCH_IS_INTEL_CORE2(a_enmMicroarch) \
311 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core2_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core2_End)
312
313/** Predicate macro for catching Atom CPUs, Silvermont and upwards. */
314#define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \
315 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End)
316
317/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
318#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
319 ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
320
321/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
322#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
323
324/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
325#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
326
327/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
328#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
329
330/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
331#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
332
333/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
334 * decendants). */
335#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
336 ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
337
338/** Predicate macro for catching AMD Family 16H CPUs. */
339#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
340 ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
341
342/** Predicate macro for catching AMD Zen Family CPUs. */
343#define CPUMMICROARCH_IS_AMD_FAM_ZEN(a_enmMicroarch) \
344 ((a_enmMicroarch) >= kCpumMicroarch_AMD_Zen_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_Zen_End)
345
346
347/**
348 * CPUID leaf.
349 *
350 * @remarks This structure is used by the patch manager and is therefore
351 * more or less set in stone.
352 */
353typedef struct CPUMCPUIDLEAF
354{
355 /** The leaf number. */
356 uint32_t uLeaf;
357 /** The sub-leaf number. */
358 uint32_t uSubLeaf;
359 /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
360 uint32_t fSubLeafMask;
361
362 /** The EAX value. */
363 uint32_t uEax;
364 /** The EBX value. */
365 uint32_t uEbx;
366 /** The ECX value. */
367 uint32_t uEcx;
368 /** The EDX value. */
369 uint32_t uEdx;
370
371 /** Flags. */
372 uint32_t fFlags;
373} CPUMCPUIDLEAF;
374#ifndef VBOX_FOR_DTRACE_LIB
375AssertCompileSize(CPUMCPUIDLEAF, 32);
376#endif
377/** Pointer to a CPUID leaf. */
378typedef CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
379/** Pointer to a const CPUID leaf. */
380typedef CPUMCPUIDLEAF const *PCCPUMCPUIDLEAF;
381
382/** @name CPUMCPUIDLEAF::fFlags
383 * @{ */
384/** Indicates working intel leaf 0xb where the lower 8 ECX bits are not modified
385 * and EDX containing the extended APIC ID. */
386#define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
387/** The leaf contains an APIC ID that needs changing to that of the current CPU. */
388#define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID RT_BIT_32(1)
389/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
390#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE RT_BIT_32(2)
391/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
392#define CPUMCPUIDLEAF_F_CONTAINS_APIC RT_BIT_32(3)
393/** Mask of the valid flags. */
394#define CPUMCPUIDLEAF_F_VALID_MASK UINT32_C(0xf)
395/** @} */
396
397/**
398 * Method used to deal with unknown CPUID leaves.
399 * @remarks Used in patch code.
400 */
401typedef enum CPUMUNKNOWNCPUID
402{
403 /** Invalid zero value. */
404 CPUMUNKNOWNCPUID_INVALID = 0,
405 /** Use given default values (DefCpuId). */
406 CPUMUNKNOWNCPUID_DEFAULTS,
407 /** Return the last standard leaf.
408 * Intel Sandy Bridge has been observed doing this. */
409 CPUMUNKNOWNCPUID_LAST_STD_LEAF,
410 /** Return the last standard leaf, with ecx observed.
411 * Intel Sandy Bridge has been observed doing this. */
412 CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX,
413 /** The register values are passed thru unmodified. */
414 CPUMUNKNOWNCPUID_PASSTHRU,
415 /** End of valid value. */
416 CPUMUNKNOWNCPUID_END,
417 /** Ensure 32-bit type. */
418 CPUMUNKNOWNCPUID_32BIT_HACK = 0x7fffffff
419} CPUMUNKNOWNCPUID;
420/** Pointer to unknown CPUID leaf method. */
421typedef CPUMUNKNOWNCPUID *PCPUMUNKNOWNCPUID;
422
423
424/**
425 * The register set returned by a CPUID operation.
426 */
427typedef struct CPUMCPUID
428{
429 uint32_t uEax;
430 uint32_t uEbx;
431 uint32_t uEcx;
432 uint32_t uEdx;
433} CPUMCPUID;
434/** Pointer to a CPUID leaf. */
435typedef CPUMCPUID *PCPUMCPUID;
436/** Pointer to a const CPUID leaf. */
437typedef const CPUMCPUID *PCCPUMCPUID;
438
439
440/**
441 * MSR read functions.
442 */
443typedef enum CPUMMSRRDFN
444{
445 /** Invalid zero value. */
446 kCpumMsrRdFn_Invalid = 0,
447 /** Return the CPUMMSRRANGE::uValue. */
448 kCpumMsrRdFn_FixedValue,
449 /** Alias to the MSR range starting at the MSR given by
450 * CPUMMSRRANGE::uValue. Must be used in pair with
451 * kCpumMsrWrFn_MsrAlias. */
452 kCpumMsrRdFn_MsrAlias,
453 /** Write only register, GP all read attempts. */
454 kCpumMsrRdFn_WriteOnly,
455
456 kCpumMsrRdFn_Ia32P5McAddr,
457 kCpumMsrRdFn_Ia32P5McType,
458 kCpumMsrRdFn_Ia32TimestampCounter,
459 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
460 kCpumMsrRdFn_Ia32ApicBase,
461 kCpumMsrRdFn_Ia32FeatureControl,
462 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
463 kCpumMsrRdFn_Ia32SmmMonitorCtl,
464 kCpumMsrRdFn_Ia32PmcN,
465 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
466 kCpumMsrRdFn_Ia32MPerf,
467 kCpumMsrRdFn_Ia32APerf,
468 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
469 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
470 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
471 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
472 kCpumMsrRdFn_Ia32MtrrDefType,
473 kCpumMsrRdFn_Ia32Pat,
474 kCpumMsrRdFn_Ia32SysEnterCs,
475 kCpumMsrRdFn_Ia32SysEnterEsp,
476 kCpumMsrRdFn_Ia32SysEnterEip,
477 kCpumMsrRdFn_Ia32McgCap,
478 kCpumMsrRdFn_Ia32McgStatus,
479 kCpumMsrRdFn_Ia32McgCtl,
480 kCpumMsrRdFn_Ia32DebugCtl,
481 kCpumMsrRdFn_Ia32SmrrPhysBase,
482 kCpumMsrRdFn_Ia32SmrrPhysMask,
483 kCpumMsrRdFn_Ia32PlatformDcaCap,
484 kCpumMsrRdFn_Ia32CpuDcaCap,
485 kCpumMsrRdFn_Ia32Dca0Cap,
486 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
487 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
488 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
489 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
490 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
491 kCpumMsrRdFn_Ia32FixedCtrCtrl,
492 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
493 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
494 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
495 kCpumMsrRdFn_Ia32PebsEnable,
496 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
497 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
498 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
499 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
500 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
501 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
502 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
503 kCpumMsrRdFn_Ia32DsArea,
504 kCpumMsrRdFn_Ia32TscDeadline,
505 kCpumMsrRdFn_Ia32X2ApicN,
506 kCpumMsrRdFn_Ia32DebugInterface,
507 kCpumMsrRdFn_Ia32VmxBasic, /**< Takes real value as reference. */
508 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
509 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
510 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
511 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
512 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
513 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
514 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
515 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
516 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
517 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
518 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
519 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
520 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
521 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
522 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
523 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
524 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */
525 kCpumMsrRdFn_Ia32SpecCtrl,
526 kCpumMsrRdFn_Ia32ArchCapabilities,
527
528 kCpumMsrRdFn_Amd64Efer,
529 kCpumMsrRdFn_Amd64SyscallTarget,
530 kCpumMsrRdFn_Amd64LongSyscallTarget,
531 kCpumMsrRdFn_Amd64CompSyscallTarget,
532 kCpumMsrRdFn_Amd64SyscallFlagMask,
533 kCpumMsrRdFn_Amd64FsBase,
534 kCpumMsrRdFn_Amd64GsBase,
535 kCpumMsrRdFn_Amd64KernelGsBase,
536 kCpumMsrRdFn_Amd64TscAux,
537
538 kCpumMsrRdFn_IntelEblCrPowerOn,
539 kCpumMsrRdFn_IntelI7CoreThreadCount,
540 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
541 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
542 kCpumMsrRdFn_IntelP4EbcFrequencyId,
543 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
544 kCpumMsrRdFn_IntelPlatformInfo,
545 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
546 kCpumMsrRdFn_IntelPkgCStConfigControl,
547 kCpumMsrRdFn_IntelPmgIoCaptureBase,
548 kCpumMsrRdFn_IntelLastBranchFromToN,
549 kCpumMsrRdFn_IntelLastBranchFromN,
550 kCpumMsrRdFn_IntelLastBranchToN,
551 kCpumMsrRdFn_IntelLastBranchTos,
552 kCpumMsrRdFn_IntelBblCrCtl,
553 kCpumMsrRdFn_IntelBblCrCtl3,
554 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
555 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
556 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
557 kCpumMsrRdFn_IntelP6CrN,
558 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
559 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
560 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
561 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
562 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
563 kCpumMsrRdFn_IntelI7LbrSelect,
564 kCpumMsrRdFn_IntelI7SandyErrorControl,
565 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
566 kCpumMsrRdFn_IntelI7PowerCtl,
567 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
568 kCpumMsrRdFn_IntelI7PebsLdLat,
569 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
570 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
571 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
572 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
573 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
574 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
575 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
576 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
577 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
578 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
579 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
580 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
581 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
582 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
583 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
584 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
585 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
586 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
587 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
588 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
589 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
590 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
591 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
592 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
593 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
594 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
595 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
596 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
597 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
598 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
599 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
600 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
601 kCpumMsrRdFn_IntelI7UncCBoxConfig,
602 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
603 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
604 kCpumMsrRdFn_IntelI7SmiCount,
605 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
606 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
607 kCpumMsrRdFn_IntelCore1ExtConfig,
608 kCpumMsrRdFn_IntelCore1DtsCalControl,
609 kCpumMsrRdFn_IntelCore2PeciControl,
610 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency,
611
612 kCpumMsrRdFn_P6LastBranchFromIp,
613 kCpumMsrRdFn_P6LastBranchToIp,
614 kCpumMsrRdFn_P6LastIntFromIp,
615 kCpumMsrRdFn_P6LastIntToIp,
616
617 kCpumMsrRdFn_AmdFam15hTscRate,
618 kCpumMsrRdFn_AmdFam15hLwpCfg,
619 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
620 kCpumMsrRdFn_AmdFam10hMc4MiscN,
621 kCpumMsrRdFn_AmdK8PerfCtlN,
622 kCpumMsrRdFn_AmdK8PerfCtrN,
623 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
624 kCpumMsrRdFn_AmdK8HwCr,
625 kCpumMsrRdFn_AmdK8IorrBaseN,
626 kCpumMsrRdFn_AmdK8IorrMaskN,
627 kCpumMsrRdFn_AmdK8TopOfMemN,
628 kCpumMsrRdFn_AmdK8NbCfg1,
629 kCpumMsrRdFn_AmdK8McXcptRedir,
630 kCpumMsrRdFn_AmdK8CpuNameN,
631 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
632 kCpumMsrRdFn_AmdK8SwThermalCtrl,
633 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
634 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
635 kCpumMsrRdFn_AmdK8McCtlMaskN,
636 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
637 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
638 kCpumMsrRdFn_AmdK8IntPendingMessage,
639 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
640 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
641 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
642 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
643 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
644 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
645 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
646 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
647 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
648 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
649 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
650 kCpumMsrRdFn_AmdK8SmmBase,
651 kCpumMsrRdFn_AmdK8SmmAddr,
652 kCpumMsrRdFn_AmdK8SmmMask,
653 kCpumMsrRdFn_AmdK8VmCr,
654 kCpumMsrRdFn_AmdK8IgnNe,
655 kCpumMsrRdFn_AmdK8SmmCtl,
656 kCpumMsrRdFn_AmdK8VmHSavePa,
657 kCpumMsrRdFn_AmdFam10hVmLockKey,
658 kCpumMsrRdFn_AmdFam10hSmmLockKey,
659 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
660 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
661 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
662 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
663 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
664 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
665 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
666 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
667 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
668 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
669 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
670 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
671 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
672 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
673 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
674 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
675 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
676 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
677 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
678 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
679 kCpumMsrRdFn_AmdK7NodeId,
680 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
681 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
682 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
683 kCpumMsrRdFn_AmdK7LoadStoreCfg,
684 kCpumMsrRdFn_AmdK7InstrCacheCfg,
685 kCpumMsrRdFn_AmdK7DataCacheCfg,
686 kCpumMsrRdFn_AmdK7BusUnitCfg,
687 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
688 kCpumMsrRdFn_AmdFam15hFpuCfg,
689 kCpumMsrRdFn_AmdFam15hDecoderCfg,
690 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
691 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
692 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
693 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
694 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
695 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
696 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
697 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
698 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
699 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
700 kCpumMsrRdFn_AmdFam10hIbsOpRip,
701 kCpumMsrRdFn_AmdFam10hIbsOpData,
702 kCpumMsrRdFn_AmdFam10hIbsOpData2,
703 kCpumMsrRdFn_AmdFam10hIbsOpData3,
704 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
705 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
706 kCpumMsrRdFn_AmdFam10hIbsCtl,
707 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
708
709 kCpumMsrRdFn_Gim,
710
711 /** End of valid MSR read function indexes. */
712 kCpumMsrRdFn_End
713} CPUMMSRRDFN;
714
715/**
716 * MSR write functions.
717 */
718typedef enum CPUMMSRWRFN
719{
720 /** Invalid zero value. */
721 kCpumMsrWrFn_Invalid = 0,
722 /** Writes are ignored, the fWrGpMask is observed though. */
723 kCpumMsrWrFn_IgnoreWrite,
724 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
725 kCpumMsrWrFn_ReadOnly,
726 /** Alias to the MSR range starting at the MSR given by
727 * CPUMMSRRANGE::uValue. Must be used in pair with
728 * kCpumMsrRdFn_MsrAlias. */
729 kCpumMsrWrFn_MsrAlias,
730
731 kCpumMsrWrFn_Ia32P5McAddr,
732 kCpumMsrWrFn_Ia32P5McType,
733 kCpumMsrWrFn_Ia32TimestampCounter,
734 kCpumMsrWrFn_Ia32ApicBase,
735 kCpumMsrWrFn_Ia32FeatureControl,
736 kCpumMsrWrFn_Ia32BiosSignId,
737 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
738 kCpumMsrWrFn_Ia32SmmMonitorCtl,
739 kCpumMsrWrFn_Ia32PmcN,
740 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
741 kCpumMsrWrFn_Ia32MPerf,
742 kCpumMsrWrFn_Ia32APerf,
743 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
744 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
745 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
746 kCpumMsrWrFn_Ia32MtrrDefType,
747 kCpumMsrWrFn_Ia32Pat,
748 kCpumMsrWrFn_Ia32SysEnterCs,
749 kCpumMsrWrFn_Ia32SysEnterEsp,
750 kCpumMsrWrFn_Ia32SysEnterEip,
751 kCpumMsrWrFn_Ia32McgStatus,
752 kCpumMsrWrFn_Ia32McgCtl,
753 kCpumMsrWrFn_Ia32DebugCtl,
754 kCpumMsrWrFn_Ia32SmrrPhysBase,
755 kCpumMsrWrFn_Ia32SmrrPhysMask,
756 kCpumMsrWrFn_Ia32PlatformDcaCap,
757 kCpumMsrWrFn_Ia32Dca0Cap,
758 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
759 kCpumMsrWrFn_Ia32PerfStatus,
760 kCpumMsrWrFn_Ia32PerfCtl,
761 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
762 kCpumMsrWrFn_Ia32PerfCapabilities,
763 kCpumMsrWrFn_Ia32FixedCtrCtrl,
764 kCpumMsrWrFn_Ia32PerfGlobalStatus,
765 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
766 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
767 kCpumMsrWrFn_Ia32PebsEnable,
768 kCpumMsrWrFn_Ia32ClockModulation,
769 kCpumMsrWrFn_Ia32ThermInterrupt,
770 kCpumMsrWrFn_Ia32ThermStatus,
771 kCpumMsrWrFn_Ia32Therm2Ctl,
772 kCpumMsrWrFn_Ia32MiscEnable,
773 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
774 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
775 kCpumMsrWrFn_Ia32DsArea,
776 kCpumMsrWrFn_Ia32TscDeadline,
777 kCpumMsrWrFn_Ia32X2ApicN,
778 kCpumMsrWrFn_Ia32DebugInterface,
779 kCpumMsrWrFn_Ia32SpecCtrl,
780 kCpumMsrWrFn_Ia32PredCmd,
781 kCpumMsrWrFn_Ia32FlushCmd,
782
783 kCpumMsrWrFn_Amd64Efer,
784 kCpumMsrWrFn_Amd64SyscallTarget,
785 kCpumMsrWrFn_Amd64LongSyscallTarget,
786 kCpumMsrWrFn_Amd64CompSyscallTarget,
787 kCpumMsrWrFn_Amd64SyscallFlagMask,
788 kCpumMsrWrFn_Amd64FsBase,
789 kCpumMsrWrFn_Amd64GsBase,
790 kCpumMsrWrFn_Amd64KernelGsBase,
791 kCpumMsrWrFn_Amd64TscAux,
792 kCpumMsrWrFn_IntelEblCrPowerOn,
793 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
794 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
795 kCpumMsrWrFn_IntelP4EbcFrequencyId,
796 kCpumMsrWrFn_IntelFlexRatio,
797 kCpumMsrWrFn_IntelPkgCStConfigControl,
798 kCpumMsrWrFn_IntelPmgIoCaptureBase,
799 kCpumMsrWrFn_IntelLastBranchFromToN,
800 kCpumMsrWrFn_IntelLastBranchFromN,
801 kCpumMsrWrFn_IntelLastBranchToN,
802 kCpumMsrWrFn_IntelLastBranchTos,
803 kCpumMsrWrFn_IntelBblCrCtl,
804 kCpumMsrWrFn_IntelBblCrCtl3,
805 kCpumMsrWrFn_IntelI7TemperatureTarget,
806 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
807 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
808 kCpumMsrWrFn_IntelP6CrN,
809 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
810 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
811 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
812 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
813 kCpumMsrWrFn_IntelI7TurboRatioLimit,
814 kCpumMsrWrFn_IntelI7LbrSelect,
815 kCpumMsrWrFn_IntelI7SandyErrorControl,
816 kCpumMsrWrFn_IntelI7PowerCtl,
817 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
818 kCpumMsrWrFn_IntelI7PebsLdLat,
819 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
820 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
821 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */
822 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
823 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */
824 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
825 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
826 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
827 kCpumMsrWrFn_IntelI7RaplPp0Policy,
828 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
829 kCpumMsrWrFn_IntelI7RaplPp1Policy,
830 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
831 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
832 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
833 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
834 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
835 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
836 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
837 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
838 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
839 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
840 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
841 kCpumMsrWrFn_IntelCore1ExtConfig,
842 kCpumMsrWrFn_IntelCore1DtsCalControl,
843 kCpumMsrWrFn_IntelCore2PeciControl,
844
845 kCpumMsrWrFn_P6LastIntFromIp,
846 kCpumMsrWrFn_P6LastIntToIp,
847
848 kCpumMsrWrFn_AmdFam15hTscRate,
849 kCpumMsrWrFn_AmdFam15hLwpCfg,
850 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
851 kCpumMsrWrFn_AmdFam10hMc4MiscN,
852 kCpumMsrWrFn_AmdK8PerfCtlN,
853 kCpumMsrWrFn_AmdK8PerfCtrN,
854 kCpumMsrWrFn_AmdK8SysCfg,
855 kCpumMsrWrFn_AmdK8HwCr,
856 kCpumMsrWrFn_AmdK8IorrBaseN,
857 kCpumMsrWrFn_AmdK8IorrMaskN,
858 kCpumMsrWrFn_AmdK8TopOfMemN,
859 kCpumMsrWrFn_AmdK8NbCfg1,
860 kCpumMsrWrFn_AmdK8McXcptRedir,
861 kCpumMsrWrFn_AmdK8CpuNameN,
862 kCpumMsrWrFn_AmdK8HwThermalCtrl,
863 kCpumMsrWrFn_AmdK8SwThermalCtrl,
864 kCpumMsrWrFn_AmdK8FidVidControl,
865 kCpumMsrWrFn_AmdK8McCtlMaskN,
866 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
867 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
868 kCpumMsrWrFn_AmdK8IntPendingMessage,
869 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
870 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
871 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
872 kCpumMsrWrFn_AmdFam10hPStateControl,
873 kCpumMsrWrFn_AmdFam10hPStateStatus,
874 kCpumMsrWrFn_AmdFam10hPStateN,
875 kCpumMsrWrFn_AmdFam10hCofVidControl,
876 kCpumMsrWrFn_AmdFam10hCofVidStatus,
877 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
878 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
879 kCpumMsrWrFn_AmdK8SmmBase,
880 kCpumMsrWrFn_AmdK8SmmAddr,
881 kCpumMsrWrFn_AmdK8SmmMask,
882 kCpumMsrWrFn_AmdK8VmCr,
883 kCpumMsrWrFn_AmdK8IgnNe,
884 kCpumMsrWrFn_AmdK8SmmCtl,
885 kCpumMsrWrFn_AmdK8VmHSavePa,
886 kCpumMsrWrFn_AmdFam10hVmLockKey,
887 kCpumMsrWrFn_AmdFam10hSmmLockKey,
888 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
889 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
890 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
891 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
892 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
893 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
894 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
895 kCpumMsrWrFn_AmdK7MicrocodeCtl,
896 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
897 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
898 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
899 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
900 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
901 kCpumMsrWrFn_AmdK8PatchLoader,
902 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
903 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
904 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
905 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
906 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
907 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
908 kCpumMsrWrFn_AmdK7NodeId,
909 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
910 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
911 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
912 kCpumMsrWrFn_AmdK7LoadStoreCfg,
913 kCpumMsrWrFn_AmdK7InstrCacheCfg,
914 kCpumMsrWrFn_AmdK7DataCacheCfg,
915 kCpumMsrWrFn_AmdK7BusUnitCfg,
916 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
917 kCpumMsrWrFn_AmdFam15hFpuCfg,
918 kCpumMsrWrFn_AmdFam15hDecoderCfg,
919 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
920 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
921 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
922 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
923 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
924 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
925 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
926 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
927 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
928 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
929 kCpumMsrWrFn_AmdFam10hIbsOpRip,
930 kCpumMsrWrFn_AmdFam10hIbsOpData,
931 kCpumMsrWrFn_AmdFam10hIbsOpData2,
932 kCpumMsrWrFn_AmdFam10hIbsOpData3,
933 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
934 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
935 kCpumMsrWrFn_AmdFam10hIbsCtl,
936 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
937
938 kCpumMsrWrFn_Gim,
939
940 /** End of valid MSR write function indexes. */
941 kCpumMsrWrFn_End
942} CPUMMSRWRFN;
943
944/**
945 * MSR range.
946 */
947typedef struct CPUMMSRRANGE
948{
949 /** The first MSR. [0] */
950 uint32_t uFirst;
951 /** The last MSR. [4] */
952 uint32_t uLast;
953 /** The read function (CPUMMSRRDFN). [8] */
954 uint16_t enmRdFn;
955 /** The write function (CPUMMSRWRFN). [10] */
956 uint16_t enmWrFn;
957 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
958 * UINT16_MAX if not used by the read and write functions. [12] */
959 uint32_t offCpumCpu : 24;
960 /** Reserved for future hacks. [15] */
961 uint32_t fReserved : 8;
962 /** The init/read value. [16]
963 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
964 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
965 * offset into CPUM. */
966 uint64_t uValue;
967 /** The bits to ignore when writing. [24] */
968 uint64_t fWrIgnMask;
969 /** The bits that will cause a GP(0) when writing. [32]
970 * This is always checked prior to calling the write function. Using
971 * UINT64_MAX effectively marks the MSR as read-only. */
972 uint64_t fWrGpMask;
973 /** The register name, if applicable. [40] */
974 char szName[56];
975
976 /** The number of reads. */
977 STAMCOUNTER cReads;
978 /** The number of writes. */
979 STAMCOUNTER cWrites;
980 /** The number of times ignored bits were written. */
981 STAMCOUNTER cIgnoredBits;
982 /** The number of GPs generated. */
983 STAMCOUNTER cGps;
984} CPUMMSRRANGE;
985#ifndef VBOX_FOR_DTRACE_LIB
986AssertCompileSize(CPUMMSRRANGE, 128);
987#endif
988/** Pointer to an MSR range. */
989typedef CPUMMSRRANGE *PCPUMMSRRANGE;
990/** Pointer to a const MSR range. */
991typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
992
993
994/**
995 * MSRs which are required while exploding features.
996 */
997typedef struct CPUMMSRS
998{
999 union
1000 {
1001 VMXMSRS vmx;
1002 SVMMSRS svm;
1003 } hwvirt;
1004} CPUMMSRS;
1005/** Pointer to an CPUMMSRS struct. */
1006typedef CPUMMSRS *PCPUMMSRS;
1007/** Pointer to a const CPUMMSRS struct. */
1008typedef CPUMMSRS const *PCCPUMMSRS;
1009
1010
1011/**
1012 * CPU features and quirks.
1013 * This is mostly exploded CPUID info.
1014 */
1015typedef struct CPUMFEATURES
1016{
1017 /** The CPU vendor (CPUMCPUVENDOR). */
1018 uint8_t enmCpuVendor;
1019 /** The CPU family. */
1020 uint8_t uFamily;
1021 /** The CPU model. */
1022 uint8_t uModel;
1023 /** The CPU stepping. */
1024 uint8_t uStepping;
1025 /** The microarchitecture. */
1026#ifndef VBOX_FOR_DTRACE_LIB
1027 CPUMMICROARCH enmMicroarch;
1028#else
1029 uint32_t enmMicroarch;
1030#endif
1031 /** The maximum physical address width of the CPU. */
1032 uint8_t cMaxPhysAddrWidth;
1033 /** The maximum linear address width of the CPU. */
1034 uint8_t cMaxLinearAddrWidth;
1035 /** Max size of the extended state (or FPU state if no XSAVE). */
1036 uint16_t cbMaxExtendedState;
1037
1038 /** Supports MSRs. */
1039 uint32_t fMsr : 1;
1040 /** Supports the page size extension (4/2 MB pages). */
1041 uint32_t fPse : 1;
1042 /** Supports 36-bit page size extension (4 MB pages can map memory above
1043 * 4GB). */
1044 uint32_t fPse36 : 1;
1045 /** Supports physical address extension (PAE). */
1046 uint32_t fPae : 1;
1047 /** Supports page-global extension (PGE). */
1048 uint32_t fPge : 1;
1049 /** Page attribute table (PAT) support (page level cache control). */
1050 uint32_t fPat : 1;
1051 /** Supports the FXSAVE and FXRSTOR instructions. */
1052 uint32_t fFxSaveRstor : 1;
1053 /** Supports the XSAVE and XRSTOR instructions. */
1054 uint32_t fXSaveRstor : 1;
1055 /** Supports the XSAVEOPT instruction. */
1056 uint32_t fXSaveOpt : 1;
1057 /** The XSAVE/XRSTOR bit in CR4 has been set (only applicable for host!). */
1058 uint32_t fOpSysXSaveRstor : 1;
1059 /** Supports MMX. */
1060 uint32_t fMmx : 1;
1061 /** Supports AMD extensions to MMX instructions. */
1062 uint32_t fAmdMmxExts : 1;
1063 /** Supports SSE. */
1064 uint32_t fSse : 1;
1065 /** Supports SSE2. */
1066 uint32_t fSse2 : 1;
1067 /** Supports SSE3. */
1068 uint32_t fSse3 : 1;
1069 /** Supports SSSE3. */
1070 uint32_t fSsse3 : 1;
1071 /** Supports SSE4.1. */
1072 uint32_t fSse41 : 1;
1073 /** Supports SSE4.2. */
1074 uint32_t fSse42 : 1;
1075 /** Supports AVX. */
1076 uint32_t fAvx : 1;
1077 /** Supports AVX2. */
1078 uint32_t fAvx2 : 1;
1079 /** Supports AVX512 foundation. */
1080 uint32_t fAvx512Foundation : 1;
1081 /** Supports RDTSC. */
1082 uint32_t fTsc : 1;
1083 /** Intel SYSENTER/SYSEXIT support */
1084 uint32_t fSysEnter : 1;
1085 /** First generation APIC. */
1086 uint32_t fApic : 1;
1087 /** Second generation APIC. */
1088 uint32_t fX2Apic : 1;
1089 /** Hypervisor present. */
1090 uint32_t fHypervisorPresent : 1;
1091 /** MWAIT & MONITOR instructions supported. */
1092 uint32_t fMonitorMWait : 1;
1093 /** MWAIT Extensions present. */
1094 uint32_t fMWaitExtensions : 1;
1095 /** Supports CMPXCHG16B in 64-bit mode. */
1096 uint32_t fMovCmpXchg16b : 1;
1097 /** Supports CLFLUSH. */
1098 uint32_t fClFlush : 1;
1099 /** Supports CLFLUSHOPT. */
1100 uint32_t fClFlushOpt : 1;
1101 /** Supports IA32_PRED_CMD.IBPB. */
1102 uint32_t fIbpb : 1;
1103 /** Supports IA32_SPEC_CTRL.IBRS. */
1104 uint32_t fIbrs : 1;
1105 /** Supports IA32_SPEC_CTRL.STIBP. */
1106 uint32_t fStibp : 1;
1107 /** Supports IA32_FLUSH_CMD. */
1108 uint32_t fFlushCmd : 1;
1109 /** Supports IA32_ARCH_CAP. */
1110 uint32_t fArchCap : 1;
1111 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
1112 uint32_t fMdsClear : 1;
1113 /** Supports PCID. */
1114 uint32_t fPcid : 1;
1115 /** Supports INVPCID. */
1116 uint32_t fInvpcid : 1;
1117 /** Supports read/write FSGSBASE instructions. */
1118 uint32_t fFsGsBase : 1;
1119 /** Supports BMI1 instructions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, and TZCNT). */
1120 uint32_t fBmi1 : 1;
1121 /** Supports BMI2 instructions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX,
1122 * and SHLX). */
1123 uint32_t fBmi2 : 1;
1124 /** Supports POPCNT instruction. */
1125 uint32_t fPopCnt : 1;
1126 /** Supports RDRAND instruction. */
1127 uint32_t fRdRand : 1;
1128 /** Supports RDSEED instruction. */
1129 uint32_t fRdSeed : 1;
1130 /** Supports Hardware Lock Elision (HLE). */
1131 uint32_t fHle : 1;
1132 /** Supports Restricted Transactional Memory (RTM - XBEGIN, XEND, XABORT). */
1133 uint32_t fRtm : 1;
1134 /** Supports PCLMULQDQ instruction. */
1135 uint32_t fPclMul : 1;
1136 /** Supports AES-NI (six AESxxx instructions). */
1137 uint32_t fAesNi : 1;
1138 /** Support MOVBE instruction. */
1139 uint32_t fMovBe : 1;
1140 /** Support SHA instructions. */
1141 uint32_t fSha : 1;
1142
1143 /** Supports AMD 3DNow instructions. */
1144 uint32_t f3DNow : 1;
1145 /** Supports the 3DNow/AMD64 prefetch instructions (could be nops). */
1146 uint32_t f3DNowPrefetch : 1;
1147
1148 /** AMD64: Supports long mode. */
1149 uint32_t fLongMode : 1;
1150 /** AMD64: SYSCALL/SYSRET support. */
1151 uint32_t fSysCall : 1;
1152 /** AMD64: No-execute page table bit. */
1153 uint32_t fNoExecute : 1;
1154 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
1155 uint32_t fLahfSahf : 1;
1156 /** AMD64: Supports RDTSCP. */
1157 uint32_t fRdTscP : 1;
1158 /** AMD64: Supports MOV CR8 in 32-bit code (lock prefix hack). */
1159 uint32_t fMovCr8In32Bit : 1;
1160 /** AMD64: Supports XOP (similar to VEX3/AVX). */
1161 uint32_t fXop : 1;
1162 /** AMD64: Supports ABM, i.e. the LZCNT instruction. */
1163 uint32_t fAbm : 1;
1164 /** AMD64: Supports TBM (BEXTR, BLCFILL, BLCI, BLCIC, BLCMSK, BLCS,
1165 * BLSFILL, BLSIC, T1MSKC, and TZMSK). */
1166 uint32_t fTbm : 1;
1167
1168 /** Indicates that FPU instruction and data pointers may leak.
1169 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
1170 * is only saved and restored if an exception is pending. */
1171 uint32_t fLeakyFxSR : 1;
1172
1173 /** AMD64: Supports AMD SVM. */
1174 uint32_t fSvm : 1;
1175
1176 /** Support for Intel VMX. */
1177 uint32_t fVmx : 1;
1178
1179 /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
1180 * The details are different for Intel and AMD but both have similar
1181 * functionality. */
1182 uint32_t fSpeculationControl : 1;
1183
1184 /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
1185 * @remarks Only safe use after CPUM ring-0 init! */
1186 uint32_t fArchRdclNo : 1;
1187 /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
1188 * @remarks Only safe use after CPUM ring-0 init! */
1189 uint32_t fArchIbrsAll : 1;
1190 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
1191 * @remarks Only safe use after CPUM ring-0 init! */
1192 uint32_t fArchRsbOverride : 1;
1193 /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
1194 * @remarks Only safe use after CPUM ring-0 init! */
1195 uint32_t fArchVmmNeedNotFlushL1d : 1;
1196 /** MSR_IA32_ARCH_CAPABILITIES: MDS_NO (bit 4).
1197 * @remarks Only safe use after CPUM ring-0 init! */
1198 uint32_t fArchMdsNo : 1;
1199
1200 /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
1201 * prior to the bit fields -> total of 24 bytes) */
1202 uint32_t fPadding0 : 25;
1203
1204
1205 /** @name SVM
1206 * @{ */
1207 /** SVM: Supports Nested-paging. */
1208 uint32_t fSvmNestedPaging : 1;
1209 /** SVM: Support LBR (Last Branch Record) virtualization. */
1210 uint32_t fSvmLbrVirt : 1;
1211 /** SVM: Supports SVM lock. */
1212 uint32_t fSvmSvmLock : 1;
1213 /** SVM: Supports Next RIP save. */
1214 uint32_t fSvmNextRipSave : 1;
1215 /** SVM: Supports TSC rate MSR. */
1216 uint32_t fSvmTscRateMsr : 1;
1217 /** SVM: Supports VMCB clean bits. */
1218 uint32_t fSvmVmcbClean : 1;
1219 /** SVM: Supports Flush-by-ASID. */
1220 uint32_t fSvmFlusbByAsid : 1;
1221 /** SVM: Supports decode assist. */
1222 uint32_t fSvmDecodeAssists : 1;
1223 /** SVM: Supports Pause filter. */
1224 uint32_t fSvmPauseFilter : 1;
1225 /** SVM: Supports Pause filter threshold. */
1226 uint32_t fSvmPauseFilterThreshold : 1;
1227 /** SVM: Supports AVIC (Advanced Virtual Interrupt Controller). */
1228 uint32_t fSvmAvic : 1;
1229 /** SVM: Supports Virtualized VMSAVE/VMLOAD. */
1230 uint32_t fSvmVirtVmsaveVmload : 1;
1231 /** SVM: Supports VGIF (Virtual Global Interrupt Flag). */
1232 uint32_t fSvmVGif : 1;
1233 /** SVM: Supports GMET (Guest Mode Execute Trap Extension). */
1234 uint32_t fSvmGmet : 1;
1235 /** SVM: Supports SSSCheck (SVM Supervisor Shadow Stack). */
1236 uint32_t fSvmSSSCheck : 1;
1237 /** SVM: Supports SPEC_CTRL virtualization. */
1238 uint32_t fSvmSpecCtrl : 1;
1239 /** SVM: Supports HOST_MCE_OVERRIDE. */
1240 uint32_t fSvmHostMceOverride : 1;
1241 /** SVM: Supports TlbiCtl (INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept). */
1242 uint32_t fSvmTlbiCtl : 1;
1243 /** SVM: Padding / reserved for future features (64 bits total w/ max ASID). */
1244 uint32_t fSvmPadding0 : 14;
1245 /** SVM: Maximum supported ASID. */
1246 uint32_t uSvmMaxAsid;
1247 /** @} */
1248
1249
1250 /** VMX: Maximum physical address width. */
1251 uint32_t cVmxMaxPhysAddrWidth : 8;
1252
1253 /** @name VMX basic controls.
1254 * @{ */
1255 /** VMX: Supports INS/OUTS VM-exit instruction info. */
1256 uint32_t fVmxInsOutInfo : 1;
1257 /** @} */
1258
1259 /** @name VMX Pin-based controls.
1260 * @{ */
1261 /** VMX: Supports external interrupt VM-exit. */
1262 uint32_t fVmxExtIntExit : 1;
1263 /** VMX: Supports NMI VM-exit. */
1264 uint32_t fVmxNmiExit : 1;
1265 /** VMX: Supports Virtual NMIs. */
1266 uint32_t fVmxVirtNmi : 1;
1267 /** VMX: Supports preemption timer. */
1268 uint32_t fVmxPreemptTimer : 1;
1269 /** VMX: Supports posted interrupts. */
1270 uint32_t fVmxPostedInt : 1;
1271 /** @} */
1272
1273 /** @name VMX Processor-based controls.
1274 * @{ */
1275 /** VMX: Supports Interrupt-window exiting. */
1276 uint32_t fVmxIntWindowExit : 1;
1277 /** VMX: Supports TSC offsetting. */
1278 uint32_t fVmxTscOffsetting : 1;
1279 /** VMX: Supports HLT exiting. */
1280 uint32_t fVmxHltExit : 1;
1281 /** VMX: Supports INVLPG exiting. */
1282 uint32_t fVmxInvlpgExit : 1;
1283 /** VMX: Supports MWAIT exiting. */
1284 uint32_t fVmxMwaitExit : 1;
1285 /** VMX: Supports RDPMC exiting. */
1286 uint32_t fVmxRdpmcExit : 1;
1287 /** VMX: Supports RDTSC exiting. */
1288 uint32_t fVmxRdtscExit : 1;
1289 /** VMX: Supports CR3-load exiting. */
1290 uint32_t fVmxCr3LoadExit : 1;
1291 /** VMX: Supports CR3-store exiting. */
1292 uint32_t fVmxCr3StoreExit : 1;
1293 /** VMX: Supports tertiary processor-based VM-execution controls. */
1294 uint32_t fVmxTertiaryExecCtls : 1;
1295 /** VMX: Supports CR8-load exiting. */
1296 uint32_t fVmxCr8LoadExit : 1;
1297 /** VMX: Supports CR8-store exiting. */
1298 uint32_t fVmxCr8StoreExit : 1;
1299 /** VMX: Supports TPR shadow. */
1300 uint32_t fVmxUseTprShadow : 1;
1301 /** VMX: Supports NMI-window exiting. */
1302 uint32_t fVmxNmiWindowExit : 1;
1303 /** VMX: Supports Mov-DRx exiting. */
1304 uint32_t fVmxMovDRxExit : 1;
1305 /** VMX: Supports Unconditional I/O exiting. */
1306 uint32_t fVmxUncondIoExit : 1;
1307 /** VMX: Supportgs I/O bitmaps. */
1308 uint32_t fVmxUseIoBitmaps : 1;
1309 /** VMX: Supports Monitor Trap Flag. */
1310 uint32_t fVmxMonitorTrapFlag : 1;
1311 /** VMX: Supports MSR bitmap. */
1312 uint32_t fVmxUseMsrBitmaps : 1;
1313 /** VMX: Supports MONITOR exiting. */
1314 uint32_t fVmxMonitorExit : 1;
1315 /** VMX: Supports PAUSE exiting. */
1316 uint32_t fVmxPauseExit : 1;
1317 /** VMX: Supports secondary processor-based VM-execution controls. */
1318 uint32_t fVmxSecondaryExecCtls : 1;
1319 /** @} */
1320
1321 /** @name VMX Secondary processor-based controls.
1322 * @{ */
1323 /** VMX: Supports virtualize-APIC access. */
1324 uint32_t fVmxVirtApicAccess : 1;
1325 /** VMX: Supports EPT (Extended Page Tables). */
1326 uint32_t fVmxEpt : 1;
1327 /** VMX: Supports descriptor-table exiting. */
1328 uint32_t fVmxDescTableExit : 1;
1329 /** VMX: Supports RDTSCP. */
1330 uint32_t fVmxRdtscp : 1;
1331 /** VMX: Supports virtualize-x2APIC mode. */
1332 uint32_t fVmxVirtX2ApicMode : 1;
1333 /** VMX: Supports VPID. */
1334 uint32_t fVmxVpid : 1;
1335 /** VMX: Supports WBIND exiting. */
1336 uint32_t fVmxWbinvdExit : 1;
1337 /** VMX: Supports Unrestricted guest. */
1338 uint32_t fVmxUnrestrictedGuest : 1;
1339 /** VMX: Supports APIC-register virtualization. */
1340 uint32_t fVmxApicRegVirt : 1;
1341 /** VMX: Supports virtual-interrupt delivery. */
1342 uint32_t fVmxVirtIntDelivery : 1;
1343 /** VMX: Supports Pause-loop exiting. */
1344 uint32_t fVmxPauseLoopExit : 1;
1345 /** VMX: Supports RDRAND exiting. */
1346 uint32_t fVmxRdrandExit : 1;
1347 /** VMX: Supports INVPCID. */
1348 uint32_t fVmxInvpcid : 1;
1349 /** VMX: Supports VM functions. */
1350 uint32_t fVmxVmFunc : 1;
1351 /** VMX: Supports VMCS shadowing. */
1352 uint32_t fVmxVmcsShadowing : 1;
1353 /** VMX: Supports RDSEED exiting. */
1354 uint32_t fVmxRdseedExit : 1;
1355 /** VMX: Supports PML. */
1356 uint32_t fVmxPml : 1;
1357 /** VMX: Supports EPT-violations \#VE. */
1358 uint32_t fVmxEptXcptVe : 1;
1359 /** VMX: Supports conceal VMX from PT. */
1360 uint32_t fVmxConcealVmxFromPt : 1;
1361 /** VMX: Supports XSAVES/XRSTORS. */
1362 uint32_t fVmxXsavesXrstors : 1;
1363 /** VMX: Supports mode-based execute control for EPT. */
1364 uint32_t fVmxModeBasedExecuteEpt : 1;
1365 /** VMX: Supports sub-page write permissions for EPT. */
1366 uint32_t fVmxSppEpt : 1;
1367 /** VMX: Supports Intel PT to output guest-physical addresses for EPT. */
1368 uint32_t fVmxPtEpt : 1;
1369 /** VMX: Supports TSC scaling. */
1370 uint32_t fVmxUseTscScaling : 1;
1371 /** VMX: Supports TPAUSE, UMONITOR, or UMWAIT. */
1372 uint32_t fVmxUserWaitPause : 1;
1373 /** VMX: Supports enclave (ENCLV) exiting. */
1374 uint32_t fVmxEnclvExit : 1;
1375 /** @} */
1376
1377 /** @name VMX Tertiary processor-based controls.
1378 * @{ */
1379 /** VMX: Supports LOADIWKEY exiting. */
1380 uint32_t fVmxLoadIwKeyExit : 1;
1381 /** @} */
1382
1383 /** @name VMX VM-entry controls.
1384 * @{ */
1385 /** VMX: Supports load-debug controls on VM-entry. */
1386 uint32_t fVmxEntryLoadDebugCtls : 1;
1387 /** VMX: Supports IA32e mode guest. */
1388 uint32_t fVmxIa32eModeGuest : 1;
1389 /** VMX: Supports load guest EFER MSR on VM-entry. */
1390 uint32_t fVmxEntryLoadEferMsr : 1;
1391 /** VMX: Supports load guest PAT MSR on VM-entry. */
1392 uint32_t fVmxEntryLoadPatMsr : 1;
1393 /** @} */
1394
1395 /** @name VMX VM-exit controls.
1396 * @{ */
1397 /** VMX: Supports save debug controls on VM-exit. */
1398 uint32_t fVmxExitSaveDebugCtls : 1;
1399 /** VMX: Supports host-address space size. */
1400 uint32_t fVmxHostAddrSpaceSize : 1;
1401 /** VMX: Supports acknowledge external interrupt on VM-exit. */
1402 uint32_t fVmxExitAckExtInt : 1;
1403 /** VMX: Supports save guest PAT MSR on VM-exit. */
1404 uint32_t fVmxExitSavePatMsr : 1;
1405 /** VMX: Supports load hsot PAT MSR on VM-exit. */
1406 uint32_t fVmxExitLoadPatMsr : 1;
1407 /** VMX: Supports save guest EFER MSR on VM-exit. */
1408 uint32_t fVmxExitSaveEferMsr : 1;
1409 /** VMX: Supports load host EFER MSR on VM-exit. */
1410 uint32_t fVmxExitLoadEferMsr : 1;
1411 /** VMX: Supports save VMX preemption timer on VM-exit. */
1412 uint32_t fVmxSavePreemptTimer : 1;
1413 /** VMX: Supports secondary VM-exit controls. */
1414 uint32_t fVmxSecondaryExitCtls : 1;
1415 /** @} */
1416
1417 /** @name VMX Miscellaneous data.
1418 * @{ */
1419 /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
1420 uint32_t fVmxExitSaveEferLma : 1;
1421 /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
1422 uint32_t fVmxPt : 1;
1423 /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1424 * VMWRITE cannot modify read-only VM-exit information fields. */
1425 uint32_t fVmxVmwriteAll : 1;
1426 /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
1427 * length instructions. */
1428 uint32_t fVmxEntryInjectSoftInt : 1;
1429 /** @} */
1430
1431 /** VMX: Padding / reserved for future features. */
1432 uint32_t fVmxPadding0 : 16;
1433 /** VMX: Padding / reserved for future, making it a total of 128 bits. */
1434 uint32_t fVmxPadding1;
1435} CPUMFEATURES;
1436#ifndef VBOX_FOR_DTRACE_LIB
1437AssertCompileSize(CPUMFEATURES, 48);
1438#endif
1439/** Pointer to a CPU feature structure. */
1440typedef CPUMFEATURES *PCPUMFEATURES;
1441/** Pointer to a const CPU feature structure. */
1442typedef CPUMFEATURES const *PCCPUMFEATURES;
1443
1444/**
1445 * Chameleon wrapper structure for the host CPU features.
1446 *
1447 * This is used for the globally readable g_CpumHostFeatures variable, which is
1448 * initialized once during VMMR0 load for ring-0 and during CPUMR3Init in
1449 * ring-3. To reflect this immutability after load/init, we use this wrapper
1450 * structure to switch it between const and non-const depending on the context.
1451 * Only two files sees it as non-const (CPUMR0.cpp and CPUM.cpp).
1452 */
1453typedef struct CPUHOSTFEATURES
1454{
1455 CPUMFEATURES
1456#ifndef CPUM_WITH_NONCONST_HOST_FEATURES
1457 const
1458#endif
1459 s;
1460} CPUHOSTFEATURES;
1461/** Pointer to a const host CPU feature structure. */
1462typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
1463
1464/** Host CPU features.
1465 * @note In ring-3, only valid after CPUMR3Init. In ring-0, valid after
1466 * module init. */
1467extern CPUHOSTFEATURES g_CpumHostFeatures;
1468
1469
1470/**
1471 * CPU database entry.
1472 */
1473typedef struct CPUMDBENTRY
1474{
1475 /** The CPU name. */
1476 const char *pszName;
1477 /** The full CPU name. */
1478 const char *pszFullName;
1479 /** The CPU vendor (CPUMCPUVENDOR). */
1480 uint8_t enmVendor;
1481 /** The CPU family. */
1482 uint8_t uFamily;
1483 /** The CPU model. */
1484 uint8_t uModel;
1485 /** The CPU stepping. */
1486 uint8_t uStepping;
1487 /** The microarchitecture. */
1488 CPUMMICROARCH enmMicroarch;
1489 /** Scalable bus frequency used for reporting other frequencies. */
1490 uint64_t uScalableBusFreq;
1491 /** Flags - CPUMDB_F_XXX. */
1492 uint32_t fFlags;
1493 /** The maximum physical address with of the CPU. This should correspond to
1494 * the value in CPUID leaf 0x80000008 when present. */
1495 uint8_t cMaxPhysAddrWidth;
1496 /** The MXCSR mask. */
1497 uint32_t fMxCsrMask;
1498 /** Pointer to an array of CPUID leaves. */
1499 PCCPUMCPUIDLEAF paCpuIdLeaves;
1500 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
1501 uint32_t cCpuIdLeaves;
1502 /** The method used to deal with unknown CPUID leaves. */
1503 CPUMUNKNOWNCPUID enmUnknownCpuId;
1504 /** The default unknown CPUID value. */
1505 CPUMCPUID DefUnknownCpuId;
1506
1507 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
1508 * the RDMSR and WRMSR instructions. */
1509 uint32_t fMsrMask;
1510
1511 /** The number of ranges in the table pointed to b paMsrRanges. */
1512 uint32_t cMsrRanges;
1513 /** MSR ranges for this CPU. */
1514 PCCPUMMSRRANGE paMsrRanges;
1515} CPUMDBENTRY;
1516/** Pointer to a const CPU database entry. */
1517typedef CPUMDBENTRY const *PCCPUMDBENTRY;
1518
1519/** @name CPUMDB_F_XXX - CPUDBENTRY::fFlags
1520 * @{ */
1521/** Should execute all in IEM.
1522 * @todo Implement this - currently done in Main... */
1523#define CPUMDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
1524/** @} */
1525
1526
1527
1528#ifndef VBOX_FOR_DTRACE_LIB
1529
1530#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1531VMMDECL(int) CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
1532VMMDECL(CPUMCPUVENDOR) CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
1533#endif
1534
1535VMM_INT_DECL(bool) CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu);
1536
1537
1538/** @name Guest Register Getters.
1539 * @{ */
1540VMMDECL(void) CPUMGetGuestGDTR(PCVMCPU pVCpu, PVBOXGDTR pGDTR);
1541VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PCVMCPU pVCpu, uint16_t *pcbLimit);
1542VMMDECL(RTSEL) CPUMGetGuestTR(PCVMCPU pVCpu, PCPUMSELREGHID pHidden);
1543VMMDECL(RTSEL) CPUMGetGuestLDTR(PCVMCPU pVCpu);
1544VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PCVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
1545VMMDECL(uint64_t) CPUMGetGuestCR0(PCVMCPU pVCpu);
1546VMMDECL(uint64_t) CPUMGetGuestCR2(PCVMCPU pVCpu);
1547VMMDECL(uint64_t) CPUMGetGuestCR3(PCVMCPU pVCpu);
1548VMMDECL(uint64_t) CPUMGetGuestCR4(PCVMCPU pVCpu);
1549VMMDECL(uint64_t) CPUMGetGuestCR8(PCVMCPUCC pVCpu);
1550VMMDECL(int) CPUMGetGuestCRx(PCVMCPUCC pVCpu, unsigned iReg, uint64_t *pValue);
1551VMMDECL(uint32_t) CPUMGetGuestEFlags(PCVMCPU pVCpu);
1552VMMDECL(uint32_t) CPUMGetGuestEIP(PCVMCPU pVCpu);
1553VMMDECL(uint64_t) CPUMGetGuestRIP(PCVMCPU pVCpu);
1554VMMDECL(uint32_t) CPUMGetGuestEAX(PCVMCPU pVCpu);
1555VMMDECL(uint32_t) CPUMGetGuestEBX(PCVMCPU pVCpu);
1556VMMDECL(uint32_t) CPUMGetGuestECX(PCVMCPU pVCpu);
1557VMMDECL(uint32_t) CPUMGetGuestEDX(PCVMCPU pVCpu);
1558VMMDECL(uint32_t) CPUMGetGuestESI(PCVMCPU pVCpu);
1559VMMDECL(uint32_t) CPUMGetGuestEDI(PCVMCPU pVCpu);
1560VMMDECL(uint32_t) CPUMGetGuestESP(PCVMCPU pVCpu);
1561VMMDECL(uint32_t) CPUMGetGuestEBP(PCVMCPU pVCpu);
1562VMMDECL(RTSEL) CPUMGetGuestCS(PCVMCPU pVCpu);
1563VMMDECL(RTSEL) CPUMGetGuestDS(PCVMCPU pVCpu);
1564VMMDECL(RTSEL) CPUMGetGuestES(PCVMCPU pVCpu);
1565VMMDECL(RTSEL) CPUMGetGuestFS(PCVMCPU pVCpu);
1566VMMDECL(RTSEL) CPUMGetGuestGS(PCVMCPU pVCpu);
1567VMMDECL(RTSEL) CPUMGetGuestSS(PCVMCPU pVCpu);
1568VMMDECL(uint64_t) CPUMGetGuestFlatPC(PVMCPU pVCpu);
1569VMMDECL(uint64_t) CPUMGetGuestFlatSP(PVMCPU pVCpu);
1570VMMDECL(uint64_t) CPUMGetGuestDR0(PCVMCPU pVCpu);
1571VMMDECL(uint64_t) CPUMGetGuestDR1(PCVMCPU pVCpu);
1572VMMDECL(uint64_t) CPUMGetGuestDR2(PCVMCPU pVCpu);
1573VMMDECL(uint64_t) CPUMGetGuestDR3(PCVMCPU pVCpu);
1574VMMDECL(uint64_t) CPUMGetGuestDR6(PCVMCPU pVCpu);
1575VMMDECL(uint64_t) CPUMGetGuestDR7(PCVMCPU pVCpu);
1576VMMDECL(int) CPUMGetGuestDRx(PCVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
1577VMMDECL(void) CPUMGetGuestCpuId(PVMCPUCC pVCpu, uint32_t iLeaf, uint32_t iSubLeaf, int f64BitMode,
1578 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
1579VMMDECL(uint64_t) CPUMGetGuestEFER(PCVMCPU pVCpu);
1580VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
1581VMM_INT_DECL(uint64_t) CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
1582VMM_INT_DECL(uint64_t) CPUMGetGuestIa32SmmMonitorCtl(PCVMCPUCC pVCpu);
1583VMM_INT_DECL(uint64_t) CPUMGetGuestIa32VmxEptVpidCap(PCVMCPUCC pVCpu);
1584VMMDECL(VBOXSTRICTRC) CPUMQueryGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *puValue);
1585VMMDECL(VBOXSTRICTRC) CPUMSetGuestMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t uValue);
1586VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
1587VMMDECL(CPUMMICROARCH) CPUMGetGuestMicroarch(PCVM pVM);
1588VMMDECL(void) CPUMGetGuestAddrWidths(PCVM pVM, uint8_t *pcPhysAddrWidth, uint8_t *pcLinearAddrWidth);
1589VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
1590VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM);
1591/** @} */
1592
1593/** @name Guest Register Setters.
1594 * @{ */
1595VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1596VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
1597VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
1598VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
1599VMMDECL(int) CPUMSetGuestCR0(PVMCPUCC pVCpu, uint64_t cr0);
1600VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
1601VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
1602VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
1603VMMDECL(int) CPUMSetGuestDR0(PVMCPUCC pVCpu, uint64_t uDr0);
1604VMMDECL(int) CPUMSetGuestDR1(PVMCPUCC pVCpu, uint64_t uDr1);
1605VMMDECL(int) CPUMSetGuestDR2(PVMCPUCC pVCpu, uint64_t uDr2);
1606VMMDECL(int) CPUMSetGuestDR3(PVMCPUCC pVCpu, uint64_t uDr3);
1607VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
1608VMMDECL(int) CPUMSetGuestDR7(PVMCPUCC pVCpu, uint64_t uDr7);
1609VMMDECL(int) CPUMSetGuestDRx(PVMCPUCC pVCpu, uint32_t iReg, uint64_t Value);
1610VMM_INT_DECL(int) CPUMSetGuestXcr0(PVMCPUCC pVCpu, uint64_t uNewValue);
1611VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
1612VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
1613VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
1614VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
1615VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
1616VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
1617VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
1618VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
1619VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
1620VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
1621VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
1622VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
1623VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
1624VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
1625VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
1626VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
1627VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
1628VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1629VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1630VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
1631VMMDECL(bool) CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
1632VMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
1633VMM_INT_DECL(void) CPUMSetGuestTscAux(PVMCPUCC pVCpu, uint64_t uValue);
1634VMM_INT_DECL(uint64_t) CPUMGetGuestTscAux(PVMCPUCC pVCpu);
1635VMM_INT_DECL(void) CPUMSetGuestSpecCtrl(PVMCPUCC pVCpu, uint64_t uValue);
1636VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
1637VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
1638VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
1639VMM_INT_DECL(void) CPUMGetGuestPaePdpes(PVMCPU pVCpu, PX86PDPE paPaePdpes);
1640/** @} */
1641
1642
1643/** @name Misc Guest Predicate Functions.
1644 * @{ */
1645VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu);
1646VMMDECL(bool) CPUMIsGuestNXEnabled(PCVMCPU pVCpu);
1647VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PCVMCPU pVCpu);
1648VMMDECL(bool) CPUMIsGuestPagingEnabled(PCVMCPU pVCpu);
1649VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PCVMCPU pVCpu);
1650VMMDECL(bool) CPUMIsGuestInRealMode(PCVMCPU pVCpu);
1651VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PCVMCPU pVCpu);
1652VMMDECL(bool) CPUMIsGuestInProtectedMode(PCVMCPU pVCpu);
1653VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PCVMCPU pVCpu);
1654VMMDECL(bool) CPUMIsGuestInLongMode(PCVMCPU pVCpu);
1655VMMDECL(bool) CPUMIsGuestInPAEMode(PCVMCPU pVCpu);
1656/** @} */
1657
1658/** @name Nested Hardware-Virtualization Helpers.
1659 * @{ */
1660VMM_INT_DECL(bool) CPUMIsGuestPhysIntrEnabled(PVMCPU pVCpu);
1661VMM_INT_DECL(bool) CPUMIsGuestVirtIntrEnabled(PVMCPU pVCpu);
1662VMM_INT_DECL(uint64_t) CPUMApplyNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1663VMM_INT_DECL(uint64_t) CPUMRemoveNestedGuestTscOffset(PCVMCPU pVCpu, uint64_t uTscValue);
1664
1665/* SVM helpers. */
1666VMM_INT_DECL(bool) CPUMIsGuestSvmPhysIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1667VMM_INT_DECL(bool) CPUMIsGuestSvmVirtIntrEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx);
1668VMM_INT_DECL(uint8_t) CPUMGetGuestSvmVirtIntrVector(PCCPUMCTX pCtx);
1669VMM_INT_DECL(void) CPUMSvmVmExitRestoreHostState(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1670VMM_INT_DECL(void) CPUMSvmVmRunSaveHostState(PCPUMCTX pCtx, uint8_t cbInstr);
1671VMM_INT_DECL(bool) CPUMIsSvmIoInterceptSet(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1672 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
1673 PSVMIOIOEXITINFO pIoExitInfo);
1674VMM_INT_DECL(int) CPUMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t *pbOffMsrpm, uint8_t *puMsrpmBit);
1675
1676/* VMX helpers. */
1677VMM_INT_DECL(bool) CPUMIsGuestVmxVmcsFieldValid(PVMCC pVM, uint64_t u64VmcsField);
1678VMM_INT_DECL(bool) CPUMIsGuestVmxIoInterceptSet(PCVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess);
1679VMM_INT_DECL(bool) CPUMIsGuestVmxMovToCr3InterceptSet(PVMCPU pVCpu, uint64_t uNewCr3);
1680VMM_INT_DECL(bool) CPUMIsGuestVmxVmreadVmwriteInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc);
1681VMM_INT_DECL(int) CPUMStartGuestVmxPremptTimer(PVMCPUCC pVCpu, uint32_t uTimer, uint8_t cShift, uint64_t *pu64EntryTick);
1682VMM_INT_DECL(int) CPUMStopGuestVmxPremptTimer(PVMCPUCC pVCpu);
1683VMM_INT_DECL(uint32_t) CPUMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr);
1684VMM_INT_DECL(bool) CPUMIsGuestVmxEptPagingEnabled(PCVMCPUCC pVCpu);
1685VMM_INT_DECL(bool) CPUMIsGuestVmxEptPaePagingEnabled(PCVMCPUCC pVCpu);
1686VMM_INT_DECL(uint64_t) CPUMGetGuestVmxApicAccessPageAddr(PCVMCPUCC pVCpu);
1687/** @} */
1688
1689/** @name Externalized State Helpers.
1690 * @{ */
1691/** @def CPUM_ASSERT_NOT_EXTRN
1692 * Macro for asserting that @a a_fNotExtrn are present.
1693 *
1694 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1695 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1696 *
1697 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1698 */
1699#define CPUM_ASSERT_NOT_EXTRN(a_pVCpu, a_fNotExtrn) \
1700 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fNotExtrn)), \
1701 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fNotExtrn)))
1702
1703/** @def CPUMCTX_ASSERT_NOT_EXTRN
1704 * Macro for asserting that @a a_fNotExtrn are present in @a a_pCtx.
1705 *
1706 * @param a_pCtx The CPU context of the calling EMT.
1707 * @param a_fNotExtrn Mask of CPUMCTX_EXTRN_XXX bits to check.
1708 */
1709#define CPUMCTX_ASSERT_NOT_EXTRN(a_pCtx, a_fNotExtrn) \
1710 AssertMsg(!((a_pCtx)->fExtrn & (a_fNotExtrn)), \
1711 ("%#RX64; a_fNotExtrn=%#RX64\n", (a_pCtx)->fExtrn, (a_fNotExtrn)))
1712
1713/** @def CPUM_IMPORT_EXTRN_RET
1714 * Macro for making sure the state specified by @a fExtrnImport is present,
1715 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1716 *
1717 * Will return if CPUMImportGuestStateOnDemand() fails.
1718 *
1719 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1720 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1721 * @thread EMT(a_pVCpu)
1722 *
1723 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1724 */
1725#define CPUM_IMPORT_EXTRN_RET(a_pVCpu, a_fExtrnImport) \
1726 do { \
1727 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1728 { /* already present, consider this likely */ } \
1729 else \
1730 { \
1731 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1732 AssertRCReturn(rcCpumImport, rcCpumImport); \
1733 } \
1734 } while (0)
1735
1736/** @def CPUM_IMPORT_EXTRN_RCSTRICT
1737 * Macro for making sure the state specified by @a fExtrnImport is present,
1738 * calling CPUMImportGuestStateOnDemand() to get it if necessary.
1739 *
1740 * Will update a_rcStrict if CPUMImportGuestStateOnDemand() fails.
1741 *
1742 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1743 * @param a_fExtrnImport Mask of CPUMCTX_EXTRN_XXX bits to get.
1744 * @param a_rcStrict Strict status code variable to update on failure.
1745 * @thread EMT(a_pVCpu)
1746 *
1747 * @remarks Requires VMCPU_INCL_CPUM_GST_CTX to be defined.
1748 */
1749#define CPUM_IMPORT_EXTRN_RCSTRICT(a_pVCpu, a_fExtrnImport, a_rcStrict) \
1750 do { \
1751 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1752 { /* already present, consider this likely */ } \
1753 else \
1754 { \
1755 int rcCpumImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1756 AssertStmt(RT_SUCCESS(rcCpumImport) || RT_FAILURE_NP(a_rcStrict), a_rcStrict = rcCpumImport); \
1757 } \
1758 } while (0)
1759
1760VMM_INT_DECL(int) CPUMImportGuestStateOnDemand(PVMCPUCC pVCpu, uint64_t fExtrnImport);
1761/** @} */
1762
1763#if !defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS) || defined(DOXYGEN_RUNNING)
1764/** @name Inlined Guest Getters and predicates Functions.
1765 * @{ */
1766
1767/**
1768 * Gets valid CR0 bits for the guest.
1769 *
1770 * @returns Valid CR0 bits.
1771 */
1772DECLINLINE(uint64_t) CPUMGetGuestCR0ValidMask(void)
1773{
1774 return ( X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
1775 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
1776 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG);
1777}
1778
1779/**
1780 * Tests if the guest is running in real mode or not.
1781 *
1782 * @returns true if in real mode, otherwise false.
1783 * @param pCtx Current CPU context.
1784 */
1785DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCCPUMCTX pCtx)
1786{
1787 return !(pCtx->cr0 & X86_CR0_PE);
1788}
1789
1790/**
1791 * Tests if the guest is running in real or virtual 8086 mode.
1792 *
1793 * @returns @c true if it is, @c false if not.
1794 * @param pCtx Current CPU context.
1795 */
1796DECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCCPUMCTX pCtx)
1797{
1798 return !(pCtx->cr0 & X86_CR0_PE)
1799 || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
1800}
1801
1802/**
1803 * Tests if the guest is running in virtual 8086 mode.
1804 *
1805 * @returns @c true if it is, @c false if not.
1806 * @param pCtx Current CPU context.
1807 */
1808DECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCCPUMCTX pCtx)
1809{
1810 return (pCtx->eflags.Bits.u1VM == 1);
1811}
1812
1813/**
1814 * Tests if the guest is running in paged protected or not.
1815 *
1816 * @returns true if in paged protected mode, otherwise false.
1817 * @param pCtx Current CPU context.
1818 */
1819DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
1820{
1821 return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
1822}
1823
1824/**
1825 * Tests if the guest is running in long mode or not.
1826 *
1827 * @returns true if in long mode, otherwise false.
1828 * @param pCtx Current CPU context.
1829 */
1830DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCCPUMCTX pCtx)
1831{
1832 return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
1833}
1834
1835VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
1836
1837/**
1838 * Tests if the guest is running in 64 bits mode or not.
1839 *
1840 * @returns true if in 64 bits protected mode, otherwise false.
1841 * @param pCtx Current CPU context.
1842 */
1843DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
1844{
1845 if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
1846 return false;
1847 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
1848 return CPUMIsGuestIn64BitCodeSlow(pCtx);
1849 return pCtx->cs.Attr.n.u1Long;
1850}
1851
1852/**
1853 * Tests if the guest has paging enabled or not.
1854 *
1855 * @returns true if paging is enabled, otherwise false.
1856 * @param pCtx Current CPU context.
1857 */
1858DECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCCPUMCTX pCtx)
1859{
1860 return !!(pCtx->cr0 & X86_CR0_PG);
1861}
1862
1863/**
1864 * Tests if PAE paging is enabled given the relevant control registers.
1865 *
1866 * @returns @c true if in PAE mode, @c false otherwise.
1867 * @param uCr0 The CR0 value.
1868 * @param uCr4 The CR4 value.
1869 * @param uEferMsr The EFER value.
1870 */
1871DECLINLINE(bool) CPUMIsPaePagingEnabled(uint64_t uCr0, uint64_t uCr4, uint64_t uEferMsr)
1872{
1873 /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
1874 than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
1875 return ( (uCr4 & X86_CR4_PAE)
1876 && (uCr0 & X86_CR0_PG)
1877 && !(uEferMsr & MSR_K6_EFER_LMA));
1878}
1879
1880/**
1881 * Tests if the guest is running in PAE mode or not.
1882 *
1883 * @returns @c true if in PAE mode, @c false otherwise.
1884 * @param pCtx Current CPU context.
1885 */
1886DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCCPUMCTX pCtx)
1887{
1888 return CPUMIsPaePagingEnabled(pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1889}
1890
1891/**
1892 * Tests if the guest has AMD SVM enabled or not.
1893 *
1894 * @returns true if SMV is enabled, otherwise false.
1895 * @param pCtx Current CPU context.
1896 */
1897DECLINLINE(bool) CPUMIsGuestSvmEnabled(PCCPUMCTX pCtx)
1898{
1899 return RT_BOOL(pCtx->msrEFER & MSR_K6_EFER_SVME);
1900}
1901
1902/**
1903 * Tests if the guest has Intel VT-x enabled or not.
1904 *
1905 * @returns true if VMX is enabled, otherwise false.
1906 * @param pCtx Current CPU context.
1907 */
1908DECLINLINE(bool) CPUMIsGuestVmxEnabled(PCCPUMCTX pCtx)
1909{
1910 return RT_BOOL(pCtx->cr4 & X86_CR4_VMXE);
1911}
1912
1913/**
1914 * Returns the guest's global-interrupt (GIF) flag.
1915 *
1916 * @returns true when global-interrupts are enabled, otherwise false.
1917 * @param pCtx Current CPU context.
1918 */
1919DECLINLINE(bool) CPUMGetGuestGif(PCCPUMCTX pCtx)
1920{
1921 return pCtx->hwvirt.fGif;
1922}
1923
1924/**
1925 * Sets the guest's global-interrupt flag (GIF).
1926 *
1927 * @param pCtx Current CPU context.
1928 * @param fGif The value to set.
1929 */
1930DECLINLINE(void) CPUMSetGuestGif(PCPUMCTX pCtx, bool fGif)
1931{
1932 pCtx->hwvirt.fGif = fGif;
1933}
1934
1935/**
1936 * Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS.
1937 *
1938 * This also inhibit NMIs, except perhaps for nested guests.
1939 *
1940 * @returns true if interrupts are inhibited by interrupt shadow, false if not.
1941 * @param pCtx Current guest CPU context.
1942 * @note Requires pCtx->rip to be up to date.
1943 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1944 * differs from CPUMCTX::rip.
1945 */
1946DECLINLINE(bool) CPUMIsInInterruptShadow(PCCPUMCTX pCtx)
1947{
1948 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1949 return false;
1950
1951 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1952 return pCtx->uRipInhibitInt == pCtx->rip;
1953}
1954
1955/**
1956 * Checks if we're in an "interrupt shadow", i.e. after a STI, POP SS or MOV SS,
1957 * updating the state if stale.
1958 *
1959 * This also inhibit NMIs, except perhaps for nested guests.
1960 *
1961 * @retval true if interrupts are inhibited by interrupt shadow.
1962 * @retval false if not.
1963 * @param pCtx Current guest CPU context.
1964 * @note Requires pCtx->rip to be up to date.
1965 */
1966DECLINLINE(bool) CPUMIsInInterruptShadowWithUpdate(PCPUMCTX pCtx)
1967{
1968 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW))
1969 return false;
1970
1971 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
1972 if (pCtx->uRipInhibitInt == pCtx->rip)
1973 return true;
1974
1975 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
1976 return false;
1977}
1978
1979/**
1980 * Checks if we're in an "interrupt shadow" due to a POP SS or MOV SS
1981 * instruction.
1982 *
1983 * This also inhibit NMIs, except perhaps for nested guests.
1984 *
1985 * @retval true if interrupts are inhibited due to POP/MOV SS.
1986 * @retval false if not.
1987 * @param pCtx Current guest CPU context.
1988 * @note Requires pCtx->rip to be up to date.
1989 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
1990 * differs from CPUMCTX::rip.
1991 * @note Both CPUMIsInInterruptShadowAfterSti() and this function may return
1992 * true depending on the execution engine being used.
1993 */
1994DECLINLINE(bool) CPUMIsInInterruptShadowAfterSs(PCCPUMCTX pCtx)
1995{
1996 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_SS))
1997 return false;
1998
1999 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2000 return pCtx->uRipInhibitInt == pCtx->rip;
2001}
2002
2003/**
2004 * Checks if we're in an "interrupt shadow" due to an STI instruction.
2005 *
2006 * This also inhibit NMIs, except perhaps for nested guests.
2007 *
2008 * @retval true if interrupts are inhibited due to STI.
2009 * @retval false if not.
2010 * @param pCtx Current guest CPU context.
2011 * @note Requires pCtx->rip to be up to date.
2012 * @note Does NOT clear CPUMCTX_INHIBIT_SHADOW when CPUMCTX::uRipInhibitInt
2013 * differs from CPUMCTX::rip.
2014 * @note Both CPUMIsInInterruptShadowAfterSs() and this function may return
2015 * true depending on the execution engine being used.
2016 */
2017DECLINLINE(bool) CPUMIsInInterruptShadowAfterSti(PCCPUMCTX pCtx)
2018{
2019 if (!(pCtx->eflags.uBoth & CPUMCTX_INHIBIT_SHADOW_STI))
2020 return false;
2021
2022 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2023 return pCtx->uRipInhibitInt == pCtx->rip;
2024}
2025
2026/**
2027 * Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction.
2028 *
2029 * @param pCtx Current guest CPU context.
2030 * @note Requires pCtx->rip to be up to date.
2031 */
2032DECLINLINE(void) CPUMSetInInterruptShadow(PCPUMCTX pCtx)
2033{
2034 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2035 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
2036 pCtx->uRipInhibitInt = pCtx->rip;
2037}
2038
2039/**
2040 * Sets the "interrupt shadow" flag, after a STI, POP SS or MOV SS instruction,
2041 * extended version.
2042 *
2043 * @param pCtx Current guest CPU context.
2044 * @param rip The RIP for which it is inhibited.
2045 */
2046DECLINLINE(void) CPUMSetInInterruptShadowEx(PCPUMCTX pCtx, uint64_t rip)
2047{
2048 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
2049 pCtx->uRipInhibitInt = rip;
2050}
2051
2052/**
2053 * Sets the "interrupt shadow" flag after a POP SS or MOV SS instruction.
2054 *
2055 * @param pCtx Current guest CPU context.
2056 * @note Requires pCtx->rip to be up to date.
2057 */
2058DECLINLINE(void) CPUMSetInInterruptShadowSs(PCPUMCTX pCtx)
2059{
2060 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2061 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW_SS;
2062 pCtx->uRipInhibitInt = pCtx->rip;
2063}
2064
2065/**
2066 * Sets the "interrupt shadow" flag after an STI instruction.
2067 *
2068 * @param pCtx Current guest CPU context.
2069 * @note Requires pCtx->rip to be up to date.
2070 */
2071DECLINLINE(void) CPUMSetInInterruptShadowSti(PCPUMCTX pCtx)
2072{
2073 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2074 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW_STI;
2075 pCtx->uRipInhibitInt = pCtx->rip;
2076}
2077
2078/**
2079 * Clears the "interrupt shadow" flag.
2080 *
2081 * @param pCtx Current guest CPU context.
2082 */
2083DECLINLINE(void) CPUMClearInterruptShadow(PCPUMCTX pCtx)
2084{
2085 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
2086}
2087
2088/**
2089 * Update the "interrupt shadow" flag.
2090 *
2091 * @param pCtx Current guest CPU context.
2092 * @param fInhibited The new state.
2093 * @note Requires pCtx->rip to be up to date.
2094 */
2095DECLINLINE(void) CPUMUpdateInterruptShadow(PCPUMCTX pCtx, bool fInhibited)
2096{
2097 CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RIP);
2098 if (!fInhibited)
2099 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
2100 else
2101 {
2102 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
2103 pCtx->uRipInhibitInt = pCtx->rip;
2104 }
2105}
2106
2107/**
2108 * Update the "interrupt shadow" flag, extended version.
2109 *
2110 * @returns fInhibited.
2111 * @param pCtx Current guest CPU context.
2112 * @param fInhibited The new state.
2113 * @param rip The RIP for which it is inhibited.
2114 */
2115DECLINLINE(bool) CPUMUpdateInterruptShadowEx(PCPUMCTX pCtx, bool fInhibited, uint64_t rip)
2116{
2117 if (!fInhibited)
2118 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
2119 else
2120 {
2121 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_SHADOW;
2122 pCtx->uRipInhibitInt = rip;
2123 }
2124 return fInhibited;
2125}
2126
2127/**
2128 * Update the two "interrupt shadow" flags separately, extended version.
2129 *
2130 * @param pCtx Current guest CPU context.
2131 * @param fInhibitedBySs The new state for the MOV SS & POP SS aspect.
2132 * @param fInhibitedBySti The new state for the STI aspect.
2133 * @param rip The RIP for which it is inhibited.
2134 */
2135DECLINLINE(void) CPUMUpdateInterruptShadowSsStiEx(PCPUMCTX pCtx, bool fInhibitedBySs, bool fInhibitedBySti, uint64_t rip)
2136{
2137 if (!(fInhibitedBySs | fInhibitedBySti))
2138 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_SHADOW;
2139 else
2140 {
2141 pCtx->eflags.uBoth |= (fInhibitedBySs ? CPUMCTX_INHIBIT_SHADOW_SS : UINT32_C(0))
2142 | (fInhibitedBySti ? CPUMCTX_INHIBIT_SHADOW_STI : UINT32_C(0));
2143 pCtx->uRipInhibitInt = rip;
2144 }
2145}
2146
2147/* VMX forward declarations used by extended function versions: */
2148DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx);
2149DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls);
2150DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx);
2151DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking);
2152
2153/**
2154 * Checks whether interrupts, include NMIs, are inhibited by pending NMI
2155 * delivery.
2156 *
2157 * This only checks the inhibit mask.
2158 *
2159 * @retval true if interrupts are inhibited by NMI handling.
2160 * @retval false if interrupts are not inhibited by NMI handling.
2161 * @param pCtx Current guest CPU context.
2162 */
2163DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmi(PCCPUMCTX pCtx)
2164{
2165 return (pCtx->eflags.uBoth & CPUMCTX_INHIBIT_NMI) != 0;
2166}
2167
2168/**
2169 * Extended version of CPUMAreInterruptsInhibitedByNmi() that takes VMX non-root
2170 * mode into account when check whether interrupts are inhibited by NMI.
2171 *
2172 * @retval true if interrupts are inhibited by NMI handling.
2173 * @retval false if interrupts are not inhibited by NMI handling.
2174 * @param pCtx Current guest CPU context.
2175 */
2176DECLINLINE(bool) CPUMAreInterruptsInhibitedByNmiEx(PCCPUMCTX pCtx)
2177{
2178 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
2179 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
2180 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2181 return CPUMAreInterruptsInhibitedByNmi(pCtx);
2182 return CPUMIsGuestVmxVirtNmiBlocking(pCtx);
2183}
2184
2185/**
2186 * Marks interrupts, include NMIs, as inhibited by pending NMI delivery.
2187 *
2188 * @param pCtx Current guest CPU context.
2189 */
2190DECLINLINE(void) CPUMSetInterruptInhibitingByNmi(PCPUMCTX pCtx)
2191{
2192 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_NMI;
2193}
2194
2195/**
2196 * Extended version of CPUMSetInterruptInhibitingByNmi() that takes VMX non-root
2197 * mode into account when marking interrupts as inhibited by NMI.
2198 *
2199 * @param pCtx Current guest CPU context.
2200 */
2201DECLINLINE(void) CPUMSetInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
2202{
2203 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
2204 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
2205 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2206 CPUMSetInterruptInhibitingByNmi(pCtx);
2207 else
2208 CPUMSetGuestVmxVirtNmiBlocking(pCtx, true);
2209}
2210
2211/**
2212 * Marks interrupts, include NMIs, as no longer inhibited by pending NMI
2213 * delivery.
2214 *
2215 * @param pCtx Current guest CPU context.
2216 */
2217DECLINLINE(void) CPUMClearInterruptInhibitingByNmi(PCPUMCTX pCtx)
2218{
2219 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
2220}
2221
2222/**
2223 * Extended version of CPUMClearInterruptInhibitingByNmi() that takes VMX
2224 * non-root mode into account when doing the updating.
2225 *
2226 * @param pCtx Current guest CPU context.
2227 */
2228DECLINLINE(void) CPUMClearInterruptInhibitingByNmiEx(PCPUMCTX pCtx)
2229{
2230 /* See CPUMUpdateInterruptInhibitingByNmiEx for comments. */
2231 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
2232 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2233 CPUMClearInterruptInhibitingByNmi(pCtx);
2234 else
2235 CPUMSetGuestVmxVirtNmiBlocking(pCtx, false);
2236}
2237
2238/**
2239 * Update whether interrupts, include NMIs, are inhibited by pending NMI
2240 * delivery.
2241 *
2242 * @param pCtx Current guest CPU context.
2243 * @param fInhibited The new state.
2244 */
2245DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmi(PCPUMCTX pCtx, bool fInhibited)
2246{
2247 if (!fInhibited)
2248 pCtx->eflags.uBoth &= ~CPUMCTX_INHIBIT_NMI;
2249 else
2250 pCtx->eflags.uBoth |= CPUMCTX_INHIBIT_NMI;
2251}
2252
2253/**
2254 * Extended version of CPUMUpdateInterruptInhibitingByNmi() that takes VMX
2255 * non-root mode into account when doing the updating.
2256 *
2257 * @param pCtx Current guest CPU context.
2258 * @param fInhibited The new state.
2259 */
2260DECLINLINE(void) CPUMUpdateInterruptInhibitingByNmiEx(PCPUMCTX pCtx, bool fInhibited)
2261{
2262 /*
2263 * Set the state of guest-NMI blocking in any of the following cases:
2264 * - We're not executing a nested-guest.
2265 * - We're executing an SVM nested-guest[1].
2266 * - We're executing a VMX nested-guest without virtual-NMIs enabled.
2267 *
2268 * [1] -- SVM does not support virtual-NMIs or virtual-NMI blocking.
2269 * SVM hypervisors must track NMI blocking themselves by intercepting
2270 * the IRET instruction after injection of an NMI.
2271 */
2272 if ( !CPUMIsGuestInVmxNonRootMode(pCtx)
2273 || !CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI))
2274 CPUMUpdateInterruptInhibitingByNmi(pCtx, fInhibited);
2275 /*
2276 * Set the state of virtual-NMI blocking, if we are executing a
2277 * VMX nested-guest with virtual-NMIs enabled.
2278 */
2279 else
2280 CPUMSetGuestVmxVirtNmiBlocking(pCtx, fInhibited);
2281}
2282
2283
2284/**
2285 * Checks if we are executing inside an SVM nested hardware-virtualized guest.
2286 *
2287 * @returns @c true if in SVM nested-guest mode, @c false otherwise.
2288 * @param pCtx Current CPU context.
2289 */
2290DECLINLINE(bool) CPUMIsGuestInSvmNestedHwVirtMode(PCCPUMCTX pCtx)
2291{
2292 /*
2293 * With AMD-V, the VMRUN intercept is a pre-requisite to entering SVM guest-mode.
2294 * See AMD spec. 15.5 "VMRUN instruction" subsection "Canonicalization and Consistency Checks".
2295 */
2296#ifndef IN_RC
2297 if ( pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM
2298 || !(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN))
2299 return false;
2300 return true;
2301#else
2302 NOREF(pCtx);
2303 return false;
2304#endif
2305}
2306
2307/**
2308 * Checks if the guest is in VMX non-root operation.
2309 *
2310 * @returns @c true if in VMX non-root operation, @c false otherwise.
2311 * @param pCtx Current CPU context.
2312 */
2313DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
2314{
2315#ifndef IN_RC
2316 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2317 return false;
2318 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2319 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2320#else
2321 NOREF(pCtx);
2322 return false;
2323#endif
2324}
2325
2326/**
2327 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2328 * guest.
2329 *
2330 * @returns @c true if in nested-guest mode, @c false otherwise.
2331 * @param pCtx Current CPU context.
2332 */
2333DECLINLINE(bool) CPUMIsGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2334{
2335#if 0
2336 return CPUMIsGuestInVmxNonRootMode(pCtx) || CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
2337#else
2338 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2339 return false;
2340 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2341 {
2342 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2343 return pCtx->hwvirt.vmx.fInVmxNonRootMode;
2344 }
2345 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2346 return RT_BOOL(pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN);
2347#endif
2348}
2349
2350/**
2351 * Checks if we are executing inside an SVM or VMX nested hardware-virtualized
2352 * guest.
2353 *
2354 * @retval CPUMHWVIRT_NONE if not in SVM or VMX non-root mode.
2355 * @retval CPUMHWVIRT_VMX if in VMX non-root mode.
2356 * @retval CPUMHWVIRT_SVM if in SVM non-root mode.
2357 * @param pCtx Current CPU context.
2358 */
2359DECLINLINE(CPUMHWVIRT) CPUMGetGuestInNestedHwvirtMode(PCCPUMCTX pCtx)
2360{
2361 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_NONE)
2362 return CPUMHWVIRT_NONE;
2363 if (pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX)
2364 {
2365 Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
2366 return pCtx->hwvirt.vmx.fInVmxNonRootMode ? CPUMHWVIRT_VMX : CPUMHWVIRT_NONE;
2367 }
2368 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2369 return pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN ? CPUMHWVIRT_SVM : CPUMHWVIRT_NONE;
2370}
2371
2372/**
2373 * Checks if the guest is in VMX root operation.
2374 *
2375 * @returns @c true if in VMX root operation, @c false otherwise.
2376 * @param pCtx Current CPU context.
2377 */
2378DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
2379{
2380#ifndef IN_RC
2381 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_VMX)
2382 return false;
2383 return pCtx->hwvirt.vmx.fInVmxRootMode;
2384#else
2385 NOREF(pCtx);
2386 return false;
2387#endif
2388}
2389
2390# ifndef IN_RC
2391
2392/**
2393 * Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
2394 * active.
2395 *
2396 * @returns @c true if in intercept is set, @c false otherwise.
2397 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2398 * @param pCtx Current CPU context.
2399 * @param fIntercept The SVM control/instruction intercept, see
2400 * SVM_CTRL_INTERCEPT_*.
2401 */
2402DECLINLINE(bool) CPUMIsGuestSvmCtrlInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint64_t fIntercept)
2403{
2404 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2405 return false;
2406 uint64_t u64Intercepts;
2407 if (!HMGetGuestSvmCtrlIntercepts(pVCpu, &u64Intercepts))
2408 u64Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl;
2409 return RT_BOOL(u64Intercepts & fIntercept);
2410}
2411
2412/**
2413 * Checks if the nested-guest VMCB has the specified CR read intercept active.
2414 *
2415 * @returns @c true if in intercept is set, @c false otherwise.
2416 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2417 * @param pCtx Current CPU context.
2418 * @param uCr The CR register number (0 to 15).
2419 */
2420DECLINLINE(bool) CPUMIsGuestSvmReadCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2421{
2422 Assert(uCr < 16);
2423 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2424 return false;
2425 uint16_t u16Intercepts;
2426 if (!HMGetGuestSvmReadCRxIntercepts(pVCpu, &u16Intercepts))
2427 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdCRx;
2428 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2429}
2430
2431/**
2432 * Checks if the nested-guest VMCB has the specified CR write intercept active.
2433 *
2434 * @returns @c true if in intercept is set, @c false otherwise.
2435 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2436 * @param pCtx Current CPU context.
2437 * @param uCr The CR register number (0 to 15).
2438 */
2439DECLINLINE(bool) CPUMIsGuestSvmWriteCRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
2440{
2441 Assert(uCr < 16);
2442 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2443 return false;
2444 uint16_t u16Intercepts;
2445 if (!HMGetGuestSvmWriteCRxIntercepts(pVCpu, &u16Intercepts))
2446 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrCRx;
2447 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uCr));
2448}
2449
2450/**
2451 * Checks if the nested-guest VMCB has the specified DR read intercept active.
2452 *
2453 * @returns @c true if in intercept is set, @c false otherwise.
2454 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2455 * @param pCtx Current CPU context.
2456 * @param uDr The DR register number (0 to 15).
2457 */
2458DECLINLINE(bool) CPUMIsGuestSvmReadDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2459{
2460 Assert(uDr < 16);
2461 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2462 return false;
2463 uint16_t u16Intercepts;
2464 if (!HMGetGuestSvmReadDRxIntercepts(pVCpu, &u16Intercepts))
2465 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptRdDRx;
2466 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2467}
2468
2469/**
2470 * Checks if the nested-guest VMCB has the specified DR write intercept active.
2471 *
2472 * @returns @c true if in intercept is set, @c false otherwise.
2473 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2474 * @param pCtx Current CPU context.
2475 * @param uDr The DR register number (0 to 15).
2476 */
2477DECLINLINE(bool) CPUMIsGuestSvmWriteDRxInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
2478{
2479 Assert(uDr < 16);
2480 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2481 return false;
2482 uint16_t u16Intercepts;
2483 if (!HMGetGuestSvmWriteDRxIntercepts(pVCpu, &u16Intercepts))
2484 u16Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u16InterceptWrDRx;
2485 return RT_BOOL(u16Intercepts & (UINT16_C(1) << uDr));
2486}
2487
2488/**
2489 * Checks if the nested-guest VMCB has the specified exception intercept active.
2490 *
2491 * @returns @c true if in intercept is active, @c false otherwise.
2492 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2493 * @param pCtx Current CPU context.
2494 * @param uVector The exception / interrupt vector.
2495 */
2496DECLINLINE(bool) CPUMIsGuestSvmXcptInterceptSet(PCVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
2497{
2498 Assert(uVector <= X86_XCPT_LAST);
2499 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2500 return false;
2501 uint32_t u32Intercepts;
2502 if (!HMGetGuestSvmXcptIntercepts(pVCpu, &u32Intercepts))
2503 u32Intercepts = pCtx->hwvirt.svm.Vmcb.ctrl.u32InterceptXcpt;
2504 return RT_BOOL(u32Intercepts & RT_BIT(uVector));
2505}
2506
2507/**
2508 * Checks if the nested-guest VMCB has virtual-interrupt masking enabled.
2509 *
2510 * @returns @c true if virtual-interrupts are masked, @c false otherwise.
2511 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2512 * @param pCtx Current CPU context.
2513 *
2514 * @remarks Should only be called when SVM feature is exposed to the guest.
2515 */
2516DECLINLINE(bool) CPUMIsGuestSvmVirtIntrMasking(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2517{
2518 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2519 return false;
2520 bool fVIntrMasking;
2521 if (!HMGetGuestSvmVirtIntrMasking(pVCpu, &fVIntrMasking))
2522 fVIntrMasking = pCtx->hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u1VIntrMasking;
2523 return fVIntrMasking;
2524}
2525
2526/**
2527 * Checks if the nested-guest VMCB has nested-paging enabled.
2528 *
2529 * @returns @c true if nested-paging is enabled, @c false otherwise.
2530 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2531 * @param pCtx Current CPU context.
2532 *
2533 * @remarks Should only be called when SVM feature is exposed to the guest.
2534 */
2535DECLINLINE(bool) CPUMIsGuestSvmNestedPagingEnabled(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2536{
2537 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2538 return false;
2539 bool fNestedPaging;
2540 if (!HMGetGuestSvmNestedPaging(pVCpu, &fNestedPaging))
2541 fNestedPaging = pCtx->hwvirt.svm.Vmcb.ctrl.NestedPagingCtrl.n.u1NestedPaging;
2542 return fNestedPaging;
2543}
2544
2545/**
2546 * Gets the nested-guest VMCB pause-filter count.
2547 *
2548 * @returns The pause-filter count.
2549 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2550 * @param pCtx Current CPU context.
2551 *
2552 * @remarks Should only be called when SVM feature is exposed to the guest.
2553 */
2554DECLINLINE(uint16_t) CPUMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, PCCPUMCTX pCtx)
2555{
2556 if (pCtx->hwvirt.enmHwvirt != CPUMHWVIRT_SVM)
2557 return false;
2558 uint16_t u16PauseFilterCount;
2559 if (!HMGetGuestSvmPauseFilterCount(pVCpu, &u16PauseFilterCount))
2560 u16PauseFilterCount = pCtx->hwvirt.svm.Vmcb.ctrl.u16PauseFilterCount;
2561 return u16PauseFilterCount;
2562}
2563
2564/**
2565 * Updates the NextRIP (NRIP) field in the nested-guest VMCB.
2566 *
2567 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2568 * @param pCtx Current CPU context.
2569 * @param cbInstr The length of the current instruction in bytes.
2570 *
2571 * @remarks Should only be called when SVM feature is exposed to the guest.
2572 */
2573DECLINLINE(void) CPUMGuestSvmUpdateNRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr)
2574{
2575 RT_NOREF(pVCpu);
2576 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
2577 pCtx->hwvirt.svm.Vmcb.ctrl.u64NextRIP = pCtx->rip + cbInstr;
2578}
2579
2580/**
2581 * Checks whether one of the given Pin-based VM-execution controls are set when
2582 * executing a nested-guest.
2583 *
2584 * @returns @c true if set, @c false otherwise.
2585 * @param pCtx Current CPU context.
2586 * @param uPinCtls The Pin-based VM-execution controls to check.
2587 *
2588 * @remarks This does not check if all given controls are set if more than one
2589 * control is passed in @a uPinCtl.
2590 */
2591DECLINLINE(bool) CPUMIsGuestVmxPinCtlsSet(PCCPUMCTX pCtx, uint32_t uPinCtls)
2592{
2593 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2594 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & uPinCtls);
2595}
2596
2597/**
2598 * Checks whether one of the given Processor-based VM-execution controls are set
2599 * when executing a nested-guest.
2600 *
2601 * @returns @c true if set, @c false otherwise.
2602 * @param pCtx Current CPU context.
2603 * @param uProcCtls The Processor-based VM-execution controls to check.
2604 *
2605 * @remarks This does not check if all given controls are set if more than one
2606 * control is passed in @a uProcCtls.
2607 */
2608DECLINLINE(bool) CPUMIsGuestVmxProcCtlsSet(PCCPUMCTX pCtx, uint32_t uProcCtls)
2609{
2610 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2611 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls & uProcCtls);
2612}
2613
2614/**
2615 * Checks whether one of the given Secondary Processor-based VM-execution controls
2616 * are set when executing a nested-guest.
2617 *
2618 * @returns @c true if set, @c false otherwise.
2619 * @param pCtx Current CPU context.
2620 * @param uProcCtls2 The Secondary Processor-based VM-execution controls to
2621 * check.
2622 *
2623 * @remarks This does not check if all given controls are set if more than one
2624 * control is passed in @a uProcCtls2.
2625 */
2626DECLINLINE(bool) CPUMIsGuestVmxProcCtls2Set(PCCPUMCTX pCtx, uint32_t uProcCtls2)
2627{
2628 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2629 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ProcCtls2 & uProcCtls2);
2630}
2631
2632/**
2633 * Checks whether one of the given Tertiary Processor-based VM-execution controls
2634 * are set when executing a nested-guest.
2635 *
2636 * @returns @c true if set, @c false otherwise.
2637 * @param pCtx Current CPU context.
2638 * @param uProcCtls3 The Tertiary Processor-based VM-execution controls to
2639 * check.
2640 *
2641 * @remarks This does not check if all given controls are set if more than one
2642 * control is passed in @a uProcCtls3.
2643 */
2644DECLINLINE(bool) CPUMIsGuestVmxProcCtls3Set(PCCPUMCTX pCtx, uint64_t uProcCtls3)
2645{
2646 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2647 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u64ProcCtls3.u & uProcCtls3);
2648}
2649
2650/**
2651 * Checks whether one of the given VM-exit controls are set when executing a
2652 * nested-guest.
2653 *
2654 * @returns @c true if set, @c false otherwise.
2655 * @param pCtx Current CPU context.
2656 * @param uExitCtls The VM-exit controls to check.
2657 *
2658 * @remarks This does not check if all given controls are set if more than one
2659 * control is passed in @a uExitCtls.
2660 */
2661DECLINLINE(bool) CPUMIsGuestVmxExitCtlsSet(PCCPUMCTX pCtx, uint32_t uExitCtls)
2662{
2663 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2664 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32ExitCtls & uExitCtls);
2665}
2666
2667/**
2668 * Checks whether one of the given VM-entry controls are set when executing a
2669 * nested-guest.
2670 *
2671 * @returns @c true if set, @c false otherwise.
2672 * @param pCtx Current CPU context.
2673 * @param uEntryCtls The VM-entry controls to check.
2674 *
2675 * @remarks This does not check if all given controls are set if more than one
2676 * control is passed in @a uEntryCtls.
2677 */
2678DECLINLINE(bool) CPUMIsGuestVmxEntryCtlsSet(PCCPUMCTX pCtx, uint32_t uEntryCtls)
2679{
2680 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2681 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32EntryCtls & uEntryCtls);
2682}
2683
2684/**
2685 * Checks whether events injected in the nested-guest are subject to VM-exit checks.
2686 *
2687 * @returns @c true if set, @c false otherwise.
2688 * @param pCtx Current CPU context.
2689 */
2690DECLINLINE(bool) CPUMIsGuestVmxInterceptEvents(PCCPUMCTX pCtx)
2691{
2692 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2693 return pCtx->hwvirt.vmx.fInterceptEvents;
2694}
2695
2696/**
2697 * Sets whether events injected in the nested-guest are subject to VM-exit checks.
2698 *
2699 * @param pCtx Current CPU context.
2700 * @param fIntercept Whether to subject injected events to VM-exits or not.
2701 */
2702DECLINLINE(void) CPUMSetGuestVmxInterceptEvents(PCPUMCTX pCtx, bool fInterceptEvents)
2703{
2704 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2705 pCtx->hwvirt.vmx.fInterceptEvents = fInterceptEvents;
2706}
2707
2708/**
2709 * Checks whether the given exception causes a VM-exit.
2710 *
2711 * The exception type include hardware exceptions, software exceptions (#BP, #OF)
2712 * and privileged software exceptions (#DB generated by INT1/ICEBP).
2713 *
2714 * Software interrupts do -not- cause VM-exits and hence must not be used with this
2715 * function.
2716 *
2717 * @returns @c true if the exception causes a VM-exit, @c false otherwise.
2718 * @param pCtx Current CPU context.
2719 * @param uVector The exception vector.
2720 * @param uErrCode The error code associated with the exception. Pass 0 if not
2721 * applicable.
2722 */
2723DECLINLINE(bool) CPUMIsGuestVmxXcptInterceptSet(PCCPUMCTX pCtx, uint8_t uVector, uint32_t uErrCode)
2724{
2725 Assert(uVector <= X86_XCPT_LAST);
2726
2727 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2728
2729 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
2730 if (uVector == X86_XCPT_NMI)
2731 return RT_BOOL(pCtx->hwvirt.vmx.Vmcs.u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
2732
2733 /* Page-faults are subject to masking using its error code. */
2734 uint32_t fXcptBitmap = pCtx->hwvirt.vmx.Vmcs.u32XcptBitmap;
2735 if (uVector == X86_XCPT_PF)
2736 {
2737 uint32_t const fXcptPFMask = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMask;
2738 uint32_t const fXcptPFMatch = pCtx->hwvirt.vmx.Vmcs.u32XcptPFMatch;
2739 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
2740 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
2741 }
2742
2743 /* Consult the exception bitmap for all other exceptions. */
2744 if (fXcptBitmap & RT_BIT(uVector))
2745 return true;
2746 return false;
2747}
2748
2749
2750/**
2751 * Checks whether the guest is in VMX non-root mode and using EPT paging.
2752 *
2753 * @returns @c true if in VMX non-root operation with EPT, @c false otherwise.
2754 * @param pCtx Current CPU context.
2755 */
2756DECLINLINE(bool) CPUMIsGuestVmxEptPagingEnabledEx(PCCPUMCTX pCtx)
2757{
2758 return CPUMIsGuestInVmxNonRootMode(pCtx)
2759 && CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_EPT);
2760}
2761
2762
2763/**
2764 * Implements VMSucceed for VMX instruction success.
2765 *
2766 * @param pCtx Current CPU context.
2767 */
2768DECLINLINE(void) CPUMSetGuestVmxVmSucceed(PCPUMCTX pCtx)
2769{
2770 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2771}
2772
2773/**
2774 * Implements VMFailInvalid for VMX instruction failure.
2775 *
2776 * @param pCtx Current CPU context.
2777 */
2778DECLINLINE(void) CPUMSetGuestVmxVmFailInvalid(PCPUMCTX pCtx)
2779{
2780 pCtx->eflags.uBoth &= ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2781 pCtx->eflags.uBoth |= X86_EFL_CF;
2782}
2783
2784/**
2785 * Implements VMFailValid for VMX instruction failure.
2786 *
2787 * @param pCtx Current CPU context.
2788 * @param enmInsErr The VM instruction error.
2789 */
2790DECLINLINE(void) CPUMSetGuestVmxVmFailValid(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2791{
2792 pCtx->eflags.uBoth &= ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF);
2793 pCtx->eflags.uBoth |= X86_EFL_ZF;
2794 pCtx->hwvirt.vmx.Vmcs.u32RoVmInstrError = enmInsErr;
2795}
2796
2797/**
2798 * Implements VMFail for VMX instruction failure.
2799 *
2800 * @param pCtx Current CPU context.
2801 * @param enmInsErr The VM instruction error.
2802 */
2803DECLINLINE(void) CPUMSetGuestVmxVmFail(PCPUMCTX pCtx, VMXINSTRERR enmInsErr)
2804{
2805 if (pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS)
2806 CPUMSetGuestVmxVmFailValid(pCtx, enmInsErr);
2807 else
2808 CPUMSetGuestVmxVmFailInvalid(pCtx);
2809}
2810
2811/**
2812 * Returns the guest-physical address of the APIC-access page when executing a
2813 * nested-guest.
2814 *
2815 * @returns The APIC-access page guest-physical address.
2816 * @param pCtx Current CPU context.
2817 */
2818DECLINLINE(uint64_t) CPUMGetGuestVmxApicAccessPageAddrEx(PCCPUMCTX pCtx)
2819{
2820 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2821 return pCtx->hwvirt.vmx.Vmcs.u64AddrApicAccess.u;
2822}
2823
2824/**
2825 * Gets the nested-guest CR0 subject to the guest/host mask and the read-shadow.
2826 *
2827 * @returns The nested-guest CR0.
2828 * @param pCtx Current CPU context.
2829 * @param fGstHostMask The CR0 guest/host mask to use.
2830 */
2831DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr0(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2832{
2833 /*
2834 * For each CR0 bit owned by the host, the corresponding bit from the
2835 * CR0 read shadow is loaded. For each CR0 bit that is not owned by the host,
2836 * the corresponding bit from the guest CR0 is loaded.
2837 *
2838 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2839 */
2840 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2841 uint64_t const uGstCr0 = pCtx->cr0;
2842 uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2843 return (fReadShadow & fGstHostMask) | (uGstCr0 & ~fGstHostMask);
2844}
2845
2846/**
2847 * Gets the nested-guest CR4 subject to the guest/host mask and the read-shadow.
2848 *
2849 * @returns The nested-guest CR4.
2850 * @param pCtx Current CPU context.
2851 * @param fGstHostMask The CR4 guest/host mask to use.
2852 */
2853DECLINLINE(uint64_t) CPUMGetGuestVmxMaskedCr4(PCCPUMCTX pCtx, uint64_t fGstHostMask)
2854{
2855 /*
2856 * For each CR4 bit owned by the host, the corresponding bit from the
2857 * CR4 read shadow is loaded. For each CR4 bit that is not owned by the host,
2858 * the corresponding bit from the guest CR4 is loaded.
2859 *
2860 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
2861 */
2862 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2863 uint64_t const uGstCr4 = pCtx->cr4;
2864 uint64_t const fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2865 return (fReadShadow & fGstHostMask) | (uGstCr4 & ~fGstHostMask);
2866}
2867
2868/**
2869 * Checks whether the LMSW access causes a VM-exit or not.
2870 *
2871 * @returns @c true if the LMSW access causes a VM-exit, @c false otherwise.
2872 * @param pCtx Current CPU context.
2873 * @param uNewMsw The LMSW source operand (the Machine Status Word).
2874 */
2875DECLINLINE(bool) CPUMIsGuestVmxLmswInterceptSet(PCCPUMCTX pCtx, uint16_t uNewMsw)
2876{
2877 /*
2878 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
2879 *
2880 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
2881 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2882 */
2883 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2884
2885 uint32_t const fGstHostMask = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2886 uint32_t const fReadShadow = (uint32_t)pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2887
2888 /*
2889 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
2890 * CR0.PE case first, before the rest of the bits in the MSW.
2891 *
2892 * If CR0.PE is owned by the host and CR0.PE differs between the
2893 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
2894 */
2895 if ( (fGstHostMask & X86_CR0_PE)
2896 && (uNewMsw & X86_CR0_PE)
2897 && !(fReadShadow & X86_CR0_PE))
2898 return true;
2899
2900 /*
2901 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
2902 * bits differ between the MSW (source operand) and the read-shadow, we must
2903 * cause a VM-exit.
2904 */
2905 uint32_t const fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2906 if ((fReadShadow & fGstHostLmswMask) != (uNewMsw & fGstHostLmswMask))
2907 return true;
2908
2909 return false;
2910}
2911
2912/**
2913 * Checks whether the Mov-to-CR0/CR4 access causes a VM-exit or not.
2914 *
2915 * @returns @c true if the Mov CRX access causes a VM-exit, @c false otherwise.
2916 * @param pCtx Current CPU context.
2917 * @param iCrReg The control register number (must be 0 or 4).
2918 * @param uNewCrX The CR0/CR4 value being written.
2919 */
2920DECLINLINE(bool) CPUMIsGuestVmxMovToCr0Cr4InterceptSet(PCCPUMCTX pCtx, uint8_t iCrReg, uint64_t uNewCrX)
2921{
2922 /*
2923 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
2924 * corresponding bits differ between the source operand and the read-shadow,
2925 * we must cause a VM-exit.
2926 *
2927 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
2928 */
2929 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2930 Assert(iCrReg == 0 || iCrReg == 4);
2931
2932 uint64_t fGstHostMask;
2933 uint64_t fReadShadow;
2934 if (iCrReg == 0)
2935 {
2936 fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr0Mask.u;
2937 fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr0ReadShadow.u;
2938 }
2939 else
2940 {
2941 fGstHostMask = pCtx->hwvirt.vmx.Vmcs.u64Cr4Mask.u;
2942 fReadShadow = pCtx->hwvirt.vmx.Vmcs.u64Cr4ReadShadow.u;
2943 }
2944
2945 if ((fReadShadow & fGstHostMask) != (uNewCrX & fGstHostMask))
2946 {
2947 Assert(fGstHostMask != 0);
2948 return true;
2949 }
2950
2951 return false;
2952}
2953
2954/**
2955 * Returns whether the guest has an active, current VMCS.
2956 *
2957 * @returns @c true if the guest has an active, current VMCS, @c false otherwise.
2958 * @param pCtx Current CPU context.
2959 */
2960DECLINLINE(bool) CPUMIsGuestVmxCurrentVmcsValid(PCCPUMCTX pCtx)
2961{
2962 return pCtx->hwvirt.vmx.GCPhysVmcs != NIL_RTGCPHYS;
2963}
2964
2965# endif /* !IN_RC */
2966
2967/**
2968 * Checks whether the VMX nested-guest is in a state to receive physical (APIC)
2969 * interrupts.
2970 *
2971 * @returns @c true if it's ready, @c false otherwise.
2972 * @param pCtx The guest-CPU context.
2973 */
2974DECLINLINE(bool) CPUMIsGuestVmxPhysIntrEnabled(PCCPUMCTX pCtx)
2975{
2976#ifdef IN_RC
2977 AssertReleaseFailedReturn(false);
2978#else
2979 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
2980 if (CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
2981 return true;
2982 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
2983#endif
2984}
2985
2986/**
2987 * Checks whether the VMX nested-guest is blocking virtual-NMIs.
2988 *
2989 * @returns @c true if it's blocked, @c false otherwise.
2990 * @param pCtx The guest-CPU context.
2991 */
2992DECLINLINE(bool) CPUMIsGuestVmxVirtNmiBlocking(PCCPUMCTX pCtx)
2993{
2994#ifdef IN_RC
2995 RT_NOREF(pCtx);
2996 AssertReleaseFailedReturn(false);
2997#else
2998 /*
2999 * Return the state of virtual-NMI blocking, if we are executing a
3000 * VMX nested-guest with virtual-NMIs enabled.
3001 */
3002 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
3003 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
3004 return pCtx->hwvirt.vmx.fVirtNmiBlocking;
3005#endif
3006}
3007
3008/**
3009 * Sets or clears VMX nested-guest virtual-NMI blocking.
3010 *
3011 * @param pCtx The guest-CPU context.
3012 * @param fBlocking Whether virtual-NMI blocking is in effect or not.
3013 */
3014DECLINLINE(void) CPUMSetGuestVmxVirtNmiBlocking(PCPUMCTX pCtx, bool fBlocking)
3015{
3016#ifdef IN_RC
3017 RT_NOREF2(pCtx, fBlocking);
3018 AssertReleaseFailedReturnVoid();
3019#else
3020 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
3021 Assert(CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_VIRT_NMI));
3022 pCtx->hwvirt.vmx.fVirtNmiBlocking = fBlocking;
3023#endif
3024}
3025
3026/**
3027 * Checks whether the VMX nested-guest is in a state to receive virtual interrupts
3028 * (those injected with the "virtual-interrupt delivery" feature).
3029 *
3030 * @returns @c true if it's ready, @c false otherwise.
3031 * @param pCtx The guest-CPU context.
3032 */
3033DECLINLINE(bool) CPUMIsGuestVmxVirtIntrEnabled(PCCPUMCTX pCtx)
3034{
3035#ifdef IN_RC
3036 RT_NOREF2(pCtx);
3037 AssertReleaseFailedReturn(false);
3038#else
3039 Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
3040 return RT_BOOL(pCtx->eflags.u & X86_EFL_IF);
3041#endif
3042}
3043
3044/** @} */
3045#endif /* !IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS || DOXYGEN_RUNNING */
3046
3047
3048
3049/** @name Hypervisor Register Getters.
3050 * @{ */
3051VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu);
3052VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu);
3053VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu);
3054VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu);
3055VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu);
3056VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu);
3057VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu);
3058/** @} */
3059
3060/** @name Hypervisor Register Setters.
3061 * @{ */
3062VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
3063VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
3064VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
3065VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
3066VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
3067VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
3068VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
3069VMMDECL(int) CPUMRecalcHyperDRx(PVMCPUCC pVCpu, uint8_t iGstReg);
3070/** @} */
3071
3072VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
3073#ifdef VBOX_INCLUDED_vmm_cpumctx_h
3074VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
3075#endif
3076
3077/** @name Changed flags.
3078 * These flags are used to keep track of which important register that
3079 * have been changed since last they were reset. The only one allowed
3080 * to clear them is REM!
3081 *
3082 * @todo This is obsolete, but remains as it will be refactored for coordinating
3083 * IEM and NEM/HM later. Probably.
3084 * @{
3085 */
3086#define CPUM_CHANGED_FPU_REM RT_BIT(0)
3087#define CPUM_CHANGED_CR0 RT_BIT(1)
3088#define CPUM_CHANGED_CR4 RT_BIT(2)
3089#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
3090#define CPUM_CHANGED_CR3 RT_BIT(4)
3091#define CPUM_CHANGED_GDTR RT_BIT(5)
3092#define CPUM_CHANGED_IDTR RT_BIT(6)
3093#define CPUM_CHANGED_LDTR RT_BIT(7)
3094#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
3095#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
3096#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
3097#define CPUM_CHANGED_CPUID RT_BIT(11)
3098#define CPUM_CHANGED_ALL ( CPUM_CHANGED_FPU_REM \
3099 | CPUM_CHANGED_CR0 \
3100 | CPUM_CHANGED_CR4 \
3101 | CPUM_CHANGED_GLOBAL_TLB_FLUSH \
3102 | CPUM_CHANGED_CR3 \
3103 | CPUM_CHANGED_GDTR \
3104 | CPUM_CHANGED_IDTR \
3105 | CPUM_CHANGED_LDTR \
3106 | CPUM_CHANGED_TR \
3107 | CPUM_CHANGED_SYSENTER_MSR \
3108 | CPUM_CHANGED_HIDDEN_SEL_REGS \
3109 | CPUM_CHANGED_CPUID )
3110/** @} */
3111
3112VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedAdd);
3113VMMDECL(bool) CPUMSupportsXSave(PVM pVM);
3114VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
3115VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
3116VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
3117VMMDECL(bool) CPUMIsGuestFPUStateLoaded(PVMCPU pVCpu);
3118VMMDECL(bool) CPUMIsHostFPUStateSaved(PVMCPU pVCpu);
3119VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
3120VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
3121VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
3122VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu);
3123VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu);
3124VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
3125VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
3126VMMDECL(uint32_t) CPUMGetGuestMxCsrMask(PVM pVM);
3127VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
3128VMMDECL(uint64_t) CPUMGetGuestEferMsrValidMask(PVM pVM);
3129VMMDECL(int) CPUMIsGuestEferMsrWriteValid(PVM pVM, uint64_t uCr0, uint64_t uOldEfer, uint64_t uNewEfer,
3130 uint64_t *puValidEfer);
3131VMMDECL(void) CPUMSetGuestEferMsrNoChecks(PVMCPUCC pVCpu, uint64_t uOldEfer, uint64_t uValidEfer);
3132VMMDECL(bool) CPUMIsPatMsrValid(uint64_t uValue);
3133
3134
3135/** Guest CPU interruptibility level, see CPUMGetGuestInterruptibility(). */
3136typedef enum CPUMINTERRUPTIBILITY
3137{
3138 CPUMINTERRUPTIBILITY_INVALID = 0,
3139 CPUMINTERRUPTIBILITY_UNRESTRAINED,
3140 CPUMINTERRUPTIBILITY_VIRT_INT_DISABLED,
3141 CPUMINTERRUPTIBILITY_INT_DISABLED,
3142 CPUMINTERRUPTIBILITY_INT_INHIBITED, /**< @todo rename as it inhibits NMIs too. */
3143 CPUMINTERRUPTIBILITY_NMI_INHIBIT,
3144 CPUMINTERRUPTIBILITY_GLOBAL_INHIBIT,
3145 CPUMINTERRUPTIBILITY_END,
3146 CPUMINTERRUPTIBILITY_32BIT_HACK = 0x7fffffff
3147} CPUMINTERRUPTIBILITY;
3148
3149VMM_INT_DECL(CPUMINTERRUPTIBILITY) CPUMGetGuestInterruptibility(PVMCPU pVCpu);
3150
3151/** @name Typical scalable bus frequency values.
3152 * @{ */
3153/** Special internal value indicating that we don't know the frequency.
3154 * @internal */
3155#define CPUM_SBUSFREQ_UNKNOWN UINT64_C(1)
3156#define CPUM_SBUSFREQ_100MHZ UINT64_C(100000000)
3157#define CPUM_SBUSFREQ_133MHZ UINT64_C(133333333)
3158#define CPUM_SBUSFREQ_167MHZ UINT64_C(166666666)
3159#define CPUM_SBUSFREQ_200MHZ UINT64_C(200000000)
3160#define CPUM_SBUSFREQ_267MHZ UINT64_C(266666666)
3161#define CPUM_SBUSFREQ_333MHZ UINT64_C(333333333)
3162#define CPUM_SBUSFREQ_400MHZ UINT64_C(400000000)
3163/** @} */
3164
3165
3166#ifdef IN_RING3
3167/** @defgroup grp_cpum_r3 The CPUM ring-3 API
3168 * @{
3169 */
3170
3171VMMR3DECL(int) CPUMR3Init(PVM pVM);
3172VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
3173VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM);
3174VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
3175VMMR3DECL(int) CPUMR3Term(PVM pVM);
3176VMMR3DECL(void) CPUMR3Reset(PVM pVM);
3177VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
3178VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM);
3179VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
3180
3181VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf);
3182VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf);
3183VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves);
3184VMMDECL(CPUMMICROARCH) CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
3185 uint8_t bModel, uint8_t bStepping);
3186VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
3187VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
3188VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
3189VMMR3DECL(const char *) CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
3190#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
3191VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void);
3192#endif
3193
3194VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange);
3195
3196VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void);
3197/** Pointer to CPUMR3DbGetEntries. */
3198typedef DECLCALLBACKPTR(uint32_t, PFNCPUMDBGETENTRIES, (void));
3199VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb);
3200/** Pointer to CPUMR3DbGetEntryByIndex. */
3201typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYINDEX, (uint32_t idxCpuDb));
3202VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName);
3203/** Pointer to CPUMR3DbGetEntryByName. */
3204typedef DECLCALLBACKPTR(PCCPUMDBENTRY, PFNCPUMDBGETENTRYBYNAME, (const char *pszName));
3205
3206VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu);
3207VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu);
3208/** @} */
3209#endif /* IN_RING3 */
3210
3211#ifdef IN_RING0
3212/** @defgroup grp_cpum_r0 The CPUM ring-0 API
3213 * @{
3214 */
3215VMMR0_INT_DECL(int) CPUMR0ModuleInit(void);
3216VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void);
3217VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM);
3218VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM);
3219DECLASM(void) CPUMR0RegisterVCpuThread(PVMCPUCC pVCpu);
3220DECLASM(void) CPUMR0TouchHostFpu(void);
3221VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu);
3222VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu);
3223VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu);
3224VMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVMCC pVM, PVMCPUCC pVCpu);
3225VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6);
3226VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6);
3227
3228VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6);
3229VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6);
3230/** @} */
3231#endif /* IN_RING0 */
3232
3233/** @defgroup grp_cpum_rz The CPUM raw-mode and ring-0 context API
3234 * @{
3235 */
3236VMMRZ_INT_DECL(void) CPUMRZFpuStatePrepareHostCpuForUse(PVMCPUCC pVCpu);
3237VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForRead(PVMCPUCC pVCpu);
3238VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeForChange(PVMCPUCC pVCpu);
3239VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeSseForRead(PVMCPUCC pVCpu);
3240VMMRZ_INT_DECL(void) CPUMRZFpuStateActualizeAvxForRead(PVMCPUCC pVCpu);
3241/** @} */
3242
3243
3244#endif /* !VBOX_FOR_DTRACE_LIB */
3245/** @} */
3246RT_C_DECLS_END
3247
3248
3249#endif /* !VBOX_INCLUDED_vmm_cpum_h */
3250
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