cpumctx.h@ 97693

Last change on this file since 97693 was 97406, checked in by vboxsync, 2 years ago
VMM/IEM,CPUM: Partial single stepping support in the interpreter. bugref:9898
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_h
37	#define VBOX_INCLUDED_vmm_cpumctx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** @def CPUM_UNION_NM
127	* For compilers (like DTrace) that does not grok nameless unions, we have a
128	* little hack to make them palatable.
129	*/
130	/** @def CPUM_STRUCT_NM
131	* For compilers (like DTrace) that does not grok nameless structs (it is
132	* non-standard C++), we have a little hack to make them palatable.
133	*/
134	#ifdef VBOX_FOR_DTRACE_LIB
135	# define CPUM_UNION_NM(a_Nm) a_Nm
136	# define CPUM_STRUCT_NM(a_Nm) a_Nm
137	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138	# define CPUM_UNION_NM(a_Nm) a_Nm
139	# define CPUM_STRUCT_NM(a_Nm) a_Nm
140	#else
141	# define CPUM_UNION_NM(a_Nm)
142	# define CPUM_STRUCT_NM(a_Nm)
143	#endif
144	/** @def CPUM_UNION_STRUCT_NM
145	* Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146	* the screen in the compile time assertions.
147	*/
148	#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150	/** A general register (union). */
151	typedef union CPUMCTXGREG
152	{
153	/** Natural unsigned integer view. */
154	uint64_t u;
155	/** 64-bit view. */
156	uint64_t u64;
157	/** 32-bit view. */
158	uint32_t u32;
159	/** 16-bit view. */
160	uint16_t u16;
161	/** 8-bit view. */
162	uint8_t u8;
163	/** 8-bit low/high view. */
164	RT_GCC_EXTENSION struct
165	{
166	/** Low byte (al, cl, dl, bl, ++). */
167	uint8_t bLo;
168	/** High byte in the first word - ah, ch, dh, bh. */
169	uint8_t bHi;
170	} CPUM_STRUCT_NM(s);
171	} CPUMCTXGREG;
172	#ifndef VBOX_FOR_DTRACE_LIB
173	AssertCompileSize(CPUMCTXGREG, 8);
174	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176	#endif
177
178
179
180	/**
181	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
182	*
183	* @warning Exercise caution while modifying the layout of this struct. It's
184	* part of VM saved states.
185	*/
186	#pragma pack(1)
187	typedef struct SVMHOSTSTATE
188	{
189	uint64_t uEferMsr;
190	uint64_t uCr0;
191	uint64_t uCr4;
192	uint64_t uCr3;
193	uint64_t uRip;
194	uint64_t uRsp;
195	uint64_t uRax;
196	X86RFLAGS rflags;
197	CPUMSELREG es;
198	CPUMSELREG cs;
199	CPUMSELREG ss;
200	CPUMSELREG ds;
201	VBOXGDTR gdtr;
202	VBOXIDTR idtr;
203	uint8_t abPadding[4];
204	} SVMHOSTSTATE;
205	#pragma pack()
206	/** Pointer to the SVMHOSTSTATE structure. */
207	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
208	/** Pointer to a const SVMHOSTSTATE structure. */
209	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
210	#ifndef VBOX_FOR_DTRACE_LIB
211	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
212	AssertCompileSize(SVMHOSTSTATE, 184);
213	#endif
214
215
216	/**
217	* CPU hardware virtualization types.
218	*/
219	typedef enum
220	{
221	CPUMHWVIRT_NONE = 0,
222	CPUMHWVIRT_VMX,
223	CPUMHWVIRT_SVM,
224	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
225	} CPUMHWVIRT;
226	#ifndef VBOX_FOR_DTRACE_LIB
227	AssertCompileSize(CPUMHWVIRT, 4);
228	#endif
229
230	/** Number of EFLAGS bits we put aside for the hardware EFLAGS, with the bits
231	* above this we use for storing internal state not visible to the guest.
232	*
233	* Using a value less than 32 here means some code bloat when loading and
234	* fetching the hardware EFLAGS value. Comparing VMMR0.r0 text size when
235	* compiling release build using gcc 11.3.1 on linux:
236	* - 32 bits: 2475709 bytes
237	* - 24 bits: 2482069 bytes; +6360 bytes.
238	* - 22 bits: 2482261 bytes; +6552 bytes.
239	* Same for windows (virtual size of .text):
240	* - 32 bits: 1498502 bytes
241	* - 24 bits: 1502278 bytes; +3776 bytes.
242	* - 22 bits: 1502198 bytes; +3696 bytes.
243	*
244	* In addition we pass pointer the 32-bit EFLAGS to a number of IEM assembly
245	* functions, so it would be safer to not store anything in the lower 32 bits.
246	* OTOH, we'd sooner discover buggy assembly code by doing so, as we've had one
247	* example of accidental EFLAGS trashing by these functions already.
248	*
249	* It would be more efficient for IEM to store the interrupt shadow bit (and
250	* anything else that needs to be cleared at the same time) in the 30:22 bit
251	* range, because that would allow using a simple AND imm32 instruction on x86
252	* and a MOVN imm16,16 instruction to load the constant on ARM64 (assuming the
253	* other flag needing clearing is RF (bit 16)). Putting it in the 63:32 range
254	* means we that on x86 we'll either use a memory variant of AND or require a
255	* separate load instruction for the immediate, whereas on ARM we'll need more
256	* instructions to construct the immediate value.
257	*
258	* Comparing the instruction exit thruput via the bs2-test-1 testcase, there
259	* seems to be little difference between 32 and 24 here (best results out of 9
260	* runs on Linux/VT-x). So, unless the results are really wrong and there is
261	* clear drop in thruput, it would on the whole make the most sense to use 24
262	* here.
263	*/
264	#define CPUMX86EFLAGS_HW_BITS 24
265	/** Mask for the hardware EFLAGS bits, 64-bit version. */
266	#define CPUMX86EFLAGS_HW_MASK_64 (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1))
267	/** Mask for the hardware EFLAGS bits, 32-bit version. */
268	#if CPUMX86EFLAGS_HW_BITS == 32
269	# define CPUMX86EFLAGS_HW_MASK_32 UINT32_MAX
270	#elif CPUMX86EFLAGS_HW_BITS < 32 && CPUMX86EFLAGS_HW_BITS >= 22
271	# define CPUMX86EFLAGS_HW_MASK_32 (RT_BIT_32(CPUMX86EFLAGS_HW_BITS) - UINT32_C(1))
272	#else
273	# error "Misconfigured CPUMX86EFLAGS_HW_BITS value!"
274	#endif
275
276	/** Mask of internal flags kept with EFLAGS, 64-bit version.
277	* The first 3 available bits are taken by CPUMCTX_INHIBIT_SHADOW_SS,
278	* CPUMCTX_INHIBIT_SHADOW_STI and CPUMCTX_INHIBIT_NMI. The next 4 bits are
279	* taken by CPUMCTX_DBG_HIT_DRX_MASK.
280	*/
281	#define CPUMX86EFLAGS_INT_MASK_64 UINT64_C(0x000000007f000000)
282	/** Mask of internal flags kept with EFLAGS, 32-bit version. */
283	#define CPUMX86EFLAGS_INT_MASK_32 UINT32_C(0x7f000000)
284
285
286	/**
287	* CPUM EFLAGS.
288	*
289	* This differs from X86EFLAGS in that we could use bits 31:22 for internal
290	* purposes, see CPUMX86EFLAGS_HW_BITS.
291	*/
292	typedef union CPUMX86EFLAGS
293	{
294	/** The full unsigned view, both hardware and VBox bits. */
295	uint32_t uBoth;
296	/** The plain unsigned view of the hardware bits. */
297	#if CPUMX86EFLAGS_HW_BITS == 32
298	uint32_t u;
299	#else
300	uint32_t u : CPUMX86EFLAGS_HW_BITS;
301	#endif
302	#ifndef VBOX_FOR_DTRACE_LIB
303	/** The bitfield view. */
304	X86EFLAGSBITS Bits;
305	#endif
306	} CPUMX86EFLAGS;
307	/** Pointer to CPUM EFLAGS. */
308	typedef CPUMX86EFLAGS *PCPUMX86EFLAGS;
309	/** Pointer to const CPUM EFLAGS. */
310	typedef const CPUMX86EFLAGS *PCCPUMX86EFLAGS;
311
312	/**
313	* CPUM RFLAGS.
314	*
315	* This differs from X86EFLAGS in that we use could be using bits 63:22 for
316	* internal purposes, see CPUMX86EFLAGS_HW_BITS.
317	*/
318	typedef union CPUMX86RFLAGS
319	{
320	/** The full unsigned view, both hardware and VBox bits. */
321	uint64_t uBoth;
322	/** The plain unsigned view of the hardware bits. */
323	#if CPUMX86EFLAGS_HW_BITS == 32
324	uint32_t u;
325	#else
326	uint32_t u : CPUMX86EFLAGS_HW_BITS;
327	#endif
328	#ifndef VBOX_FOR_DTRACE_LIB
329	/** The bitfield view. */
330	X86EFLAGSBITS Bits;
331	#endif
332	} CPUMX86RFLAGS;
333	/** Pointer to CPUM RFLAGS. */
334	typedef CPUMX86RFLAGS *PCPUMX86RFLAGS;
335	/** Pointer to const CPUM RFLAGS. */
336	typedef const CPUMX86RFLAGS *PCCPUMX86RFLAGS;
337
338
339	/**
340	* CPU context.
341	*/
342	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
343	typedef struct CPUMCTX
344	{
345	/** General purpose registers. */
346	union /* no tag! */
347	{
348	/** The general purpose register array view, indexed by X86_GREG_XXX. */
349	CPUMCTXGREG aGRegs[16];
350
351	/** 64-bit general purpose register view. */
352	RT_GCC_EXTENSION struct /* no tag! */
353	{
354	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
355	} CPUM_STRUCT_NM(qw);
356	/** 64-bit general purpose register view. */
357	RT_GCC_EXTENSION struct /* no tag! */
358	{
359	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
360	} CPUM_STRUCT_NM(qw2);
361	/** 32-bit general purpose register view. */
362	RT_GCC_EXTENSION struct /* no tag! */
363	{
364	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
365	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
366	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
367	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
368	} CPUM_STRUCT_NM(dw);
369	/** 16-bit general purpose register view. */
370	RT_GCC_EXTENSION struct /* no tag! */
371	{
372	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
373	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
374	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
375	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
376	} CPUM_STRUCT_NM(w);
377	RT_GCC_EXTENSION struct /* no tag! */
378	{
379	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
380	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
381	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
382	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
383	} CPUM_STRUCT_NM(b);
384	} CPUM_UNION_NM(g);
385
386	/** Segment registers. */
387	union /* no tag! */
388	{
389	/** The segment register array view, indexed by X86_SREG_XXX. */
390	CPUMSELREG aSRegs[6];
391	/** The named segment register view. */
392	RT_GCC_EXTENSION struct /* no tag! */
393	{
394	CPUMSELREG es, cs, ss, ds, fs, gs;
395	} CPUM_STRUCT_NM(n);
396	} CPUM_UNION_NM(s);
397
398	/** The task register.
399	* Only the guest context uses all the members. */
400	CPUMSELREG ldtr;
401	/** The task register.
402	* Only the guest context uses all the members. */
403	CPUMSELREG tr;
404
405	/** The program counter. */
406	union
407	{
408	uint16_t ip;
409	uint32_t eip;
410	uint64_t rip;
411	} CPUM_UNION_NM(rip);
412
413	/** The flags register. */
414	union
415	{
416	CPUMX86EFLAGS eflags;
417	CPUMX86RFLAGS rflags;
418	} CPUM_UNION_NM(rflags);
419
420	/** 0x150 - Externalized state tracker, CPUMCTX_EXTRN_XXX. */
421	uint64_t fExtrn;
422
423	/** The RIP value an interrupt shadow is/was valid for. */
424	uint64_t uRipInhibitInt;
425
426	/** @name Control registers.
427	* @{ */
428	uint64_t cr0;
429	uint64_t cr2;
430	uint64_t cr3;
431	uint64_t cr4;
432	/** @} */
433
434	/** Debug registers.
435	* @remarks DR4 and DR5 should not be used since they are aliases for
436	* DR6 and DR7 respectively on both AMD and Intel CPUs.
437	* @remarks DR8-15 are currently not supported by AMD or Intel, so
438	* neither do we.
439	*/
440	uint64_t dr[8];
441
442	/** Padding before the structure so the 64-bit member is correctly aligned.
443	* @todo fix this structure! */
444	uint16_t gdtrPadding[3];
445	/** Global Descriptor Table register. */
446	VBOXGDTR gdtr;
447
448	/** Padding before the structure so the 64-bit member is correctly aligned.
449	* @todo fix this structure! */
450	uint16_t idtrPadding[3];
451	/** Interrupt Descriptor Table register. */
452	VBOXIDTR idtr;
453
454	/** The sysenter msr registers.
455	* This member is not used by the hypervisor context. */
456	CPUMSYSENTER SysEnter;
457
458	/** @name System MSRs.
459	* @{ */
460	uint64_t msrEFER; /*< @todo move EFER up to the crX registers for better cacheline mojo /
461	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
462	uint64_t msrPAT; /*< Page attribute table. /
463	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
464	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
465	uint64_t msrSFMASK; /*< syscall flag mask. /
466	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
467	/** @} */
468
469	uint64_t au64Unused[2];
470
471	/** 0x240 - PAE PDPTEs. */
472	X86PDPE aPaePdpes[4];
473
474	/** 0x260 - The XCR0..XCR1 registers. */
475	uint64_t aXcr[2];
476	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
477	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
478	uint64_t fXStateMask;
479	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
480	bool fUsedFpuGuest;
481	uint8_t afUnused[7];
482
483	/* ---- Start of members not zeroed at reset. ---- */
484
485	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
486	* @note Everything before this member will be memset to zero during reset. */
487	uint16_t aoffXState[64];
488	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
489	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
490	union /* no tag */
491	{
492	X86XSAVEAREA XState;
493	/** Byte view for simple indexing and space allocation. */
494	uint8_t abXState[0x4000 - 0x300];
495	} CPUM_UNION_NM(u);
496
497	/** 0x4000 - Hardware virtualization state.
498	* @note This is page aligned, so an full page member comes first in the
499	* substructures. */
500	struct
501	{
502	union /* no tag! */
503	{
504	struct
505	{
506	/** 0x4000 - Cache of the nested-guest VMCB. */
507	SVMVMCB Vmcb;
508	/** 0x5000 - The MSRPM (MSR Permission bitmap).
509	*
510	* This need not be physically contiguous pages because we use the one from
511	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
512	* This one is just used for caching the bitmap from guest physical memory.
513	*
514	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
515	* really need to even be page aligned.
516	*
517	* Also, couldn't we just access the guest page directly when we need to,
518	* or do we have to use a cached copy of it? */
519	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
520	/** 0x7000 - The IOPM (IO Permission bitmap).
521	*
522	* This need not be physically contiguous pages because we re-use the ring-0
523	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
524	* because it's identical (we trap all IO accesses).
525	*
526	* This one is just used for caching the IOPM from guest physical memory in
527	* case the guest hypervisor allows direct access to some IO ports.
528	*
529	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
530	* really need to even be page aligned.
531	*
532	* Also, couldn't we just access the guest page directly when we need to,
533	* or do we have to use a cached copy of it? */
534	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
535
536	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
537	uint64_t uMsrHSavePa;
538	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
539	RTGCPHYS GCPhysVmcb;
540	/** 0xa010 - Guest's host-state save area. */
541	SVMHOSTSTATE HostState;
542	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
543	* executed. */
544	uint64_t uPrevPauseTick;
545	/** 0xa0d0 - Pause filter count. */
546	uint16_t cPauseFilter;
547	/** 0xa0d2 - Pause filter threshold. */
548	uint16_t cPauseFilterThreshold;
549	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
550	bool fInterceptEvents;
551	/** 0xa0d5 - Padding. */
552	bool afPadding[3];
553	} svm;
554
555	struct
556	{
557	/** 0x4000 - The current VMCS. */
558	VMXVVMCS Vmcs;
559	/** 0X5000 - The shadow VMCS. */
560	VMXVVMCS ShadowVmcs;
561	/** 0x6000 - The VMREAD bitmap.
562	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
563	* access the guest memory directly as needed? */
564	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
565	/** 0x7000 - The VMWRITE bitmap.
566	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
567	* access the guest memory directly as needed? */
568	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
569	/** 0x8000 - The VM-entry MSR-load area. */
570	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
571	/** 0xa000 - The VM-exit MSR-store area. */
572	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
573	/** 0xc000 - The VM-exit MSR-load area. */
574	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
575	/** 0xe000 - The MSR permission bitmap.
576	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
577	* access the guest memory directly as needed? */
578	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
579	/** 0xf000 - The I/O permission bitmap.
580	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
581	* access the guest memory directly as needed? */
582	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
583
584	/** 0x11000 - Guest physical address of the VMXON region. */
585	RTGCPHYS GCPhysVmxon;
586	/** 0x11008 - Guest physical address of the current VMCS pointer. */
587	RTGCPHYS GCPhysVmcs;
588	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
589	RTGCPHYS GCPhysShadowVmcs;
590	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
591	VMXVDIAG enmDiag;
592	/** 0x1101c - VMX abort reason. */
593	VMXABORT enmAbort;
594	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
595	* (mainly used for info. that's not part of the VMCS). */
596	uint64_t uDiagAux;
597	/** 0x11028 - VMX abort auxiliary info. */
598	uint32_t uAbortAux;
599	/** 0x1102c - Whether the guest is in VMX root mode. */
600	bool fInVmxRootMode;
601	/** 0x1102d - Whether the guest is in VMX non-root mode. */
602	bool fInVmxNonRootMode;
603	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
604	bool fInterceptEvents;
605	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
606	* non-root mode before execution of IRET. */
607	bool fNmiUnblockingIret;
608	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
609	* considered to be the first in a loop. */
610	uint64_t uFirstPauseLoopTick;
611	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
612	uint64_t uPrevPauseTick;
613	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
614	* timer). */
615	uint64_t uEntryTick;
616	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
617	uint16_t offVirtApicWrite;
618	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
619	bool fVirtNmiBlocking;
620	/** 0x1104b - Padding. */
621	uint8_t abPadding0[5];
622	/** 0x11050 - Guest VMX MSRs. */
623	VMXMSRS Msrs;
624	} vmx;
625	} CPUM_UNION_NM(s);
626
627	/** 0x11130 - Hardware virtualization type currently in use. */
628	CPUMHWVIRT enmHwvirt;
629	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
630	bool fGif;
631	/** 0x11135 - Padding. */
632	bool afPadding0[3];
633	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
634	* saved while running the nested-guest. */
635	uint32_t fSavedInhibit;
636	/** 0x1113c - Pad to 64 byte boundary. */
637	uint8_t abPadding1[4];
638	} hwvirt;
639	} CPUMCTX;
640	#pragma pack()
641
642	#ifndef VBOX_FOR_DTRACE_LIB
643	AssertCompileSizeAlignment(CPUMCTX, 64);
644	AssertCompileSizeAlignment(CPUMCTX, 32);
645	AssertCompileSizeAlignment(CPUMCTX, 16);
646	AssertCompileSizeAlignment(CPUMCTX, 8);
647	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
648	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
649	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
650	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
651	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
652	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
653	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
654	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
655	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
656	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
657	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
658	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
659	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
660	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
661	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
662	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
663	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
664	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
665	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
666	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
667	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
668	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
669	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
670	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
671	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
672	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
673	AssertCompileMemberOffset(CPUMCTX, fExtrn, 0x0150);
674	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
675	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
676	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
677	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
678	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
679	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
680	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
681	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
682	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
683	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
684	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
685	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
686	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
687	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
688	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
689	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
690	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
691	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
692	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
693	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
694	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
695	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
696	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
697	/* Only do spot checks for hwvirt */
698	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
699	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
700	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
701	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
702	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
703	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
704	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
705	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
706	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
707	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
708	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
709	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
710	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
711	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
712	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
713	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
714	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
715	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
716	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
717	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
718	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
719	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
720	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
721	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
722	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
723	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
724	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
725	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
726	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
727	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
728	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
729	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
730	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
731	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
732	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
733	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
734	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
742	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
759	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
765	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
766	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
767	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
768	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
769	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
770	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
771	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
772	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
773	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
774	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
775	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
776	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
777	# ifndef _MSC_VER
778	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
779	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
780	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
781	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
782	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
783	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
784	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
785	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
786	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
787	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
788	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
789	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
790	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
791	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
792	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
793	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
794	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
795	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
796	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
797	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
798	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
799	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
800	# endif
801
802
803	/**
804	* Calculates the pointer to the given extended state component.
805	*
806	* @returns Pointer of type @a a_PtrType
807	* @param a_pCtx Pointer to the context.
808	* @param a_iCompBit The extended state component bit number. This bit
809	* must be set in CPUMCTX::fXStateMask.
810	* @param a_PtrType The pointer type of the extended state component.
811	*
812	*/
813	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
814	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
815	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
816	{ \
817	AssertCompile((a_iCompBit) < 64U); \
818	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
819	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
820	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
821	}(a_pCtx))
822	#elif defined(VBOX_STRICT) && defined(__GNUC__)
823	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
824	__extension__ (\
825	{ \
826	AssertCompile((a_iCompBit) < 64U); \
827	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
828	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
829	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
830	})
831	#else
832	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
833	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
834	#endif
835
836	/**
837	* Gets the first selector register of a CPUMCTX.
838	*
839	* Use this with X86_SREG_COUNT to loop thru the selector registers.
840	*/
841	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
842
843	#endif /* !VBOX_FOR_DTRACE_LIB */
844
845
846	/** @name CPUMCTX_EXTRN_XXX
847	* Used for parts of the CPUM state that is externalized and needs fetching
848	* before use.
849	*
850	* @{ */
851	/** External state keeper: Invalid. */
852	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
853	/** External state keeper: HM. */
854	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
855	/** External state keeper: NEM. */
856	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
857	/** External state keeper: REM. */
858	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
859	/** External state keeper mask. */
860	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
861
862	/** The RIP register value is kept externally. */
863	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
864	/** The RFLAGS register values are kept externally. */
865	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
866
867	/** The RAX register value is kept externally. */
868	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
869	/** The RCX register value is kept externally. */
870	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
871	/** The RDX register value is kept externally. */
872	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
873	/** The RBX register value is kept externally. */
874	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
875	/** The RSP register value is kept externally. */
876	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
877	/** The RBP register value is kept externally. */
878	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
879	/** The RSI register value is kept externally. */
880	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
881	/** The RDI register value is kept externally. */
882	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
883	/** The R8 thru R15 register values are kept externally. */
884	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
885	/** General purpose registers mask. */
886	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
887
888	/** The ES register values are kept externally. */
889	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
890	/** The CS register values are kept externally. */
891	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
892	/** The SS register values are kept externally. */
893	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
894	/** The DS register values are kept externally. */
895	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
896	/** The FS register values are kept externally. */
897	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
898	/** The GS register values are kept externally. */
899	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
900	/** Segment registers (includes CS). */
901	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
902	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
903	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
904	#ifndef VBOX_FOR_DTRACE_LIB
905	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
906	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
907	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
908	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
909	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
910	#endif
911
912	/** The GDTR register values are kept externally. */
913	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
914	/** The IDTR register values are kept externally. */
915	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
916	/** The LDTR register values are kept externally. */
917	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
918	/** The TR register values are kept externally. */
919	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
920	/** Table register mask. */
921	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
922
923	/** The CR0 register value is kept externally. */
924	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
925	/** The CR2 register value is kept externally. */
926	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
927	/** The CR3 register value is kept externally. */
928	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
929	/** The CR4 register value is kept externally. */
930	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
931	/** Control register mask. */
932	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
933	/** The TPR/CR8 register value is kept externally. */
934	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
935	/** The EFER register value is kept externally. */
936	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
937
938	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
939	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
940	/** The DR6 register value is kept externally. */
941	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
942	/** The DR7 register value is kept externally. */
943	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
944	/** Debug register mask. */
945	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
946
947	/** The XSAVE_C_X87 state is kept externally. */
948	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
949	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
950	* XSAVE_C_OPMASK state is kept externally. */
951	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
952	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
953	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
954	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
955	/** The state of XCR0 and XCR1 register values are kept externally. */
956	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
957
958
959	/** The KERNEL GS BASE MSR value is kept externally. */
960	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
961	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
962	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
963	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
964	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
965	/** The TSC_AUX MSR is kept externally. */
966	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
967	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
968	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
969	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
970	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
971
972	/** Mask of all the MSRs. */
973	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
974	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
975
976	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
977	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
978
979	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
980	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
981	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
982	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
983
984	/** Mask of bits the keepers can use for state tracking. */
985	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
986
987	/** NEM/Win: Event injection (known was interruption) pending state. */
988	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
989	/** NEM/Win: Mask. */
990	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
991
992	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
993	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
994	/** HM/SVM: Mask. */
995	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
996
997	/** All CPUM state bits, not including keeper specific ones. */
998	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
999	/** All CPUM state bits, including keeper specific ones. */
1000	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
1001	/** @} */
1002
1003
1004	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
1005	* @{ */
1006	/** Interrupt shadow following MOV SS or POP SS.
1007	*
1008	* When this in effect, both maskable and non-maskable interrupts are blocked
1009	* from delivery for one instruction. Same for certain debug exceptions too,
1010	* unlike the STI variant.
1011	*
1012	* It is implementation specific whether a sequence of two or more of these
1013	* instructions will have any effect on the instruction following the last one
1014	* of them. */
1015	#define CPUMCTX_INHIBIT_SHADOW_SS RT_BIT_32(0 + CPUMX86EFLAGS_HW_BITS)
1016	/** Interrupt shadow following STI.
1017	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
1018	#define CPUMCTX_INHIBIT_SHADOW_STI RT_BIT_32(1 + CPUMX86EFLAGS_HW_BITS)
1019	/** Mask combining STI and SS shadowing. */
1020	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
1021
1022	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
1023	*
1024	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
1025	* "The processor also invokes certain hardware conditions to ensure that no
1026	* other interrupts, including NMI interrupts, are received until the NMI
1027	* handler has completed executing." This flag indicates that these
1028	* conditions are currently active.
1029	*
1030	* @todo this does not really need to be in the lower 32-bits of EFLAGS.
1031	*/
1032	#define CPUMCTX_INHIBIT_NMI RT_BIT_32(2 + CPUMX86EFLAGS_HW_BITS)
1033
1034	/** Mask containing all the interrupt inhibit bits. */
1035	#define CPUMCTX_INHIBIT_ALL_MASK (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI \| CPUMCTX_INHIBIT_NMI)
1036	AssertCompile(CPUMCTX_INHIBIT_ALL_MASK < UINT32_MAX);
1037	/** @} */
1038
1039	/** @name CPUMCTX_DBG_XXX - Pending debug events.
1040	* @{ */
1041	/** Hit guest DR0 breakpoint. */
1042	#define CPUMCTX_DBG_HIT_DR0 RT_BIT_32(CPUMCTX_DBG_HIT_DR0_BIT)
1043	#define CPUMCTX_DBG_HIT_DR0_BIT (3 + CPUMX86EFLAGS_HW_BITS)
1044	/** Hit guest DR1 breakpoint. */
1045	#define CPUMCTX_DBG_HIT_DR1 RT_BIT_32(CPUMCTX_DBG_HIT_DR1_BIT)
1046	#define CPUMCTX_DBG_HIT_DR1_BIT (4 + CPUMX86EFLAGS_HW_BITS)
1047	/** Hit guest DR2 breakpoint. */
1048	#define CPUMCTX_DBG_HIT_DR2 RT_BIT_32(CPUMCTX_DBG_HIT_DR2_BIT)
1049	#define CPUMCTX_DBG_HIT_DR2_BIT (5 + CPUMX86EFLAGS_HW_BITS)
1050	/** Hit guest DR3 breakpoint. */
1051	#define CPUMCTX_DBG_HIT_DR3 RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
1052	#define CPUMCTX_DBG_HIT_DR3_BIT (6 + CPUMX86EFLAGS_HW_BITS)
1053	/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
1054	#define CPUMCTX_DBG_HIT_DRX_SHIFT CPUMCTX_DBG_HIT_DR0_BIT
1055	/** Mask of all guest pending DR0-DR3 breakpoint indicators. */
1056	#define CPUMCTX_DBG_HIT_DRX_MASK (CPUMCTX_DBG_HIT_DR0 \| CPUMCTX_DBG_HIT_DR1 \| CPUMCTX_DBG_HIT_DR2 \| CPUMCTX_DBG_HIT_DR3)
1057	AssertCompile(CPUMCTX_DBG_HIT_DRX_MASK < UINT32_MAX);
1058	/** @} */
1059
1060
1061
1062	/**
1063	* Additional guest MSRs (i.e. not part of the CPU context structure).
1064	*
1065	* @remarks Never change the order here because of the saved stated! The size
1066	* can in theory be changed, but keep older VBox versions in mind.
1067	*/
1068	typedef union CPUMCTXMSRS
1069	{
1070	struct
1071	{
1072	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1073	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1074	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1075	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1076	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1077	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1078	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1079	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1080	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1081	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1082	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1083	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1084	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1085	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1086	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1087	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1088	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1089	} msr;
1090	uint64_t au64[64];
1091	} CPUMCTXMSRS;
1092	/** Pointer to the guest MSR state. */
1093	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1094	/** Pointer to the const guest MSR state. */
1095	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1096
1097	/** @} */
1098
1099	RT_C_DECLS_END
1100
1101	#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
1102

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 97693

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