VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 37955

Last change on this file since 37955 was 37955, checked in by vboxsync, 13 years ago

Moved VBox/x86.h/mac to iprt/x86.h/mac.
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  • Property svn:keywords set to Author Date Id Revision
File size: 14.5 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#include <iprt/types.h>
30#include <iprt/x86.h>
31
32
33RT_C_DECLS_BEGIN
34
35/** @addgroup grp_cpum_ctx The CPUM Context Structures
36 * @ingroup grp_cpum
37 * @{
38 */
39
40/**
41 * Selector hidden registers.
42 */
43typedef struct CPUMSELREGHID
44{
45 /** Base register.
46 *
47 * Long mode remarks:
48 * - Unused in long mode for CS, DS, ES, SS
49 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
50 * - 64 bits for TR & LDTR
51 */
52 uint64_t u64Base;
53 /** Limit (expanded). */
54 uint32_t u32Limit;
55 /** Flags.
56 * This is the high 32-bit word of the descriptor entry.
57 * Only the flags, dpl and type are used. */
58 X86DESCATTR Attr;
59} CPUMSELREGHID;
60
61
62/**
63 * The sysenter register set.
64 */
65typedef struct CPUMSYSENTER
66{
67 /** Ring 0 cs.
68 * This value + 8 is the Ring 0 ss.
69 * This value + 16 is the Ring 3 cs.
70 * This value + 24 is the Ring 3 ss.
71 */
72 uint64_t cs;
73 /** Ring 0 eip. */
74 uint64_t eip;
75 /** Ring 0 esp. */
76 uint64_t esp;
77} CPUMSYSENTER;
78
79
80/**
81 * CPU context core.
82 */
83#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
84#pragma pack(1)
85typedef struct CPUMCTXCORE
86{
87 union
88 {
89 uint16_t di;
90 uint32_t edi;
91 uint64_t rdi;
92 };
93 union
94 {
95 uint16_t si;
96 uint32_t esi;
97 uint64_t rsi;
98 };
99 union
100 {
101 uint16_t bp;
102 uint32_t ebp;
103 uint64_t rbp;
104 };
105 union
106 {
107 uint16_t ax;
108 uint32_t eax;
109 uint64_t rax;
110 };
111 union
112 {
113 uint16_t bx;
114 uint32_t ebx;
115 uint64_t rbx;
116 };
117 union
118 {
119 uint16_t dx;
120 uint32_t edx;
121 uint64_t rdx;
122 };
123 union
124 {
125 uint16_t cx;
126 uint32_t ecx;
127 uint64_t rcx;
128 };
129 union
130 {
131 uint16_t sp;
132 uint32_t esp;
133 uint64_t rsp;
134 };
135 /* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
136 uint32_t lss_esp;
137 RTSEL ss;
138 RTSEL ssPadding;
139
140 RTSEL gs;
141 RTSEL gsPadding;
142 RTSEL fs;
143 RTSEL fsPadding;
144 RTSEL es;
145 RTSEL esPadding;
146 RTSEL ds;
147 RTSEL dsPadding;
148 RTSEL cs;
149 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
150
151 union
152 {
153 X86EFLAGS eflags;
154 X86RFLAGS rflags;
155 };
156 union
157 {
158 uint16_t ip;
159 uint32_t eip;
160 uint64_t rip;
161 };
162
163 uint64_t r8;
164 uint64_t r9;
165 uint64_t r10;
166 uint64_t r11;
167 uint64_t r12;
168 uint64_t r13;
169 uint64_t r14;
170 uint64_t r15;
171
172 /** Hidden selector registers.
173 * @{ */
174 CPUMSELREGHID esHid;
175 CPUMSELREGHID csHid;
176 CPUMSELREGHID ssHid;
177 CPUMSELREGHID dsHid;
178 CPUMSELREGHID fsHid;
179 CPUMSELREGHID gsHid;
180 /** @} */
181
182} CPUMCTXCORE;
183#pragma pack()
184#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
185typedef struct CPUMCTXCORE CPUMCTXCORE;
186#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
187
188
189/**
190 * CPU context.
191 */
192#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
193# pragma pack(1)
194typedef struct CPUMCTX
195{
196 /** FPU state. (16-byte alignment)
197 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
198 * actual format or convert it (waste of time). */
199 X86FXSTATE fpu;
200
201 /** CPUMCTXCORE Part.
202 * @{ */
203 union
204 {
205 uint8_t dil;
206 uint16_t di;
207 uint32_t edi;
208 uint64_t rdi;
209 };
210 union
211 {
212 uint8_t sil;
213 uint16_t si;
214 uint32_t esi;
215 uint64_t rsi;
216 };
217 union
218 {
219 uint16_t bp;
220 uint32_t ebp;
221 uint64_t rbp;
222 };
223 union
224 {
225 uint8_t al;
226 uint16_t ax;
227 uint32_t eax;
228 uint64_t rax;
229 };
230 union
231 {
232 uint8_t bl;
233 uint16_t bx;
234 uint32_t ebx;
235 uint64_t rbx;
236 };
237 union
238 {
239 uint8_t dl;
240 uint16_t dx;
241 uint32_t edx;
242 uint64_t rdx;
243 };
244 union
245 {
246 uint8_t cl;
247 uint16_t cx;
248 uint32_t ecx;
249 uint64_t rcx;
250 };
251 union
252 {
253 uint16_t sp;
254 uint32_t esp;
255 uint64_t rsp;
256 };
257 /** @note lss esp, [] in the switcher needs some space, so we reserve it here
258 * instead of relying on the exact esp & ss layout as before (prevented
259 * us from using a union with rsp). */
260 uint32_t lss_esp;
261 RTSEL ss;
262 RTSEL ssPadding;
263
264 RTSEL gs;
265 RTSEL gsPadding;
266 RTSEL fs;
267 RTSEL fsPadding;
268 RTSEL es;
269 RTSEL esPadding;
270 RTSEL ds;
271 RTSEL dsPadding;
272 RTSEL cs;
273 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
274
275 union
276 {
277 X86EFLAGS eflags;
278 X86RFLAGS rflags;
279 };
280 union
281 {
282 uint16_t ip;
283 uint32_t eip;
284 uint64_t rip;
285 };
286
287 uint64_t r8;
288 uint64_t r9;
289 uint64_t r10;
290 uint64_t r11;
291 uint64_t r12;
292 uint64_t r13;
293 uint64_t r14;
294 uint64_t r15;
295
296 /** Hidden selector registers.
297 * @{ */
298 CPUMSELREGHID esHid;
299 CPUMSELREGHID csHid;
300 CPUMSELREGHID ssHid;
301 CPUMSELREGHID dsHid;
302 CPUMSELREGHID fsHid;
303 CPUMSELREGHID gsHid;
304 /** @} */
305
306 /** @} */
307
308 /** Control registers.
309 * @{ */
310 uint64_t cr0;
311 uint64_t cr2;
312 uint64_t cr3;
313 uint64_t cr4;
314 /** @} */
315
316 /** Debug registers.
317 * @remarks DR4 and DR5 should not be used since they are aliases for
318 * DR6 and DR7 respectively on both AMD and Intel CPUs.
319 * @remarks DR8-15 are currently not supported by AMD or Intel, so
320 * neither do we.
321 * @{ */
322 uint64_t dr[8];
323 /** @} */
324
325 /** Global Descriptor Table register. */
326 VBOXGDTR gdtr;
327 uint16_t gdtrPadding;
328 /** Interrupt Descriptor Table register. */
329 VBOXIDTR idtr;
330 uint16_t idtrPadding;
331 /** The task register.
332 * Only the guest context uses all the members. */
333 RTSEL ldtr;
334 RTSEL ldtrPadding;
335 /** The task register.
336 * Only the guest context uses all the members. */
337 RTSEL tr;
338 RTSEL trPadding;
339
340 /** The sysenter msr registers.
341 * This member is not used by the hypervisor context. */
342 CPUMSYSENTER SysEnter;
343
344 /** System MSRs.
345 * @{ */
346 uint64_t msrEFER;
347 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
348 uint64_t msrPAT;
349 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
350 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
351 uint64_t msrSFMASK; /**< syscall flag mask. */
352 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
353 /** @} */
354
355 /** Hidden selector registers.
356 * @{ */
357 CPUMSELREGHID ldtrHid;
358 CPUMSELREGHID trHid;
359 /** @} */
360
361# if 0
362 /** Padding to align the size on a 64 byte boundary. */
363 uint32_t padding[6];
364# endif
365} CPUMCTX;
366# pragma pack()
367#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
368typedef struct CPUMCTX CPUMCTX;
369#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
370
371/**
372 * Gets the CPUMCTXCORE part of a CPUMCTX.
373 */
374#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
375
376/**
377 * Selector hidden registers, for version 1.6 saved state.
378 */
379typedef struct CPUMSELREGHID_VER1_6
380{
381 /** Base register. */
382 uint32_t u32Base;
383 /** Limit (expanded). */
384 uint32_t u32Limit;
385 /** Flags.
386 * This is the high 32-bit word of the descriptor entry.
387 * Only the flags, dpl and type are used. */
388 X86DESCATTR Attr;
389} CPUMSELREGHID_VER1_6;
390
391/**
392 * CPU context, for version 1.6 saved state.
393 * @remarks PATM uses this, which is why it has to be here.
394 */
395#ifndef VBOX_WITHOUT_UNNAMED_UNIONS
396# pragma pack(1)
397typedef struct CPUMCTX_VER1_6
398{
399 /** FPU state. (16-byte alignment)
400 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
401 * actual format or convert it (waste of time). */
402 X86FXSTATE fpu;
403
404 /** CPUMCTXCORE Part.
405 * @{ */
406 union
407 {
408 uint32_t edi;
409 uint64_t rdi;
410 };
411 union
412 {
413 uint32_t esi;
414 uint64_t rsi;
415 };
416 union
417 {
418 uint32_t ebp;
419 uint64_t rbp;
420 };
421 union
422 {
423 uint32_t eax;
424 uint64_t rax;
425 };
426 union
427 {
428 uint32_t ebx;
429 uint64_t rbx;
430 };
431 union
432 {
433 uint32_t edx;
434 uint64_t rdx;
435 };
436 union
437 {
438 uint32_t ecx;
439 uint64_t rcx;
440 };
441 /** @note We rely on the exact layout, because we use lss esp, [] in the
442 * switcher. */
443 uint32_t esp;
444 RTSEL ss;
445 RTSEL ssPadding;
446 /* Note: no overlap with esp here. */
447 uint64_t rsp_notused;
448
449 RTSEL gs;
450 RTSEL gsPadding;
451 RTSEL fs;
452 RTSEL fsPadding;
453 RTSEL es;
454 RTSEL esPadding;
455 RTSEL ds;
456 RTSEL dsPadding;
457 RTSEL cs;
458 RTSEL csPadding[3]; /**< 3 words to force 8 byte alignment for the remainder. */
459
460 union
461 {
462 X86EFLAGS eflags;
463 X86RFLAGS rflags;
464 };
465 union
466 {
467 uint32_t eip;
468 uint64_t rip;
469 };
470
471 uint64_t r8;
472 uint64_t r9;
473 uint64_t r10;
474 uint64_t r11;
475 uint64_t r12;
476 uint64_t r13;
477 uint64_t r14;
478 uint64_t r15;
479
480 /** Hidden selector registers.
481 * @{ */
482 CPUMSELREGHID_VER1_6 esHid;
483 CPUMSELREGHID_VER1_6 csHid;
484 CPUMSELREGHID_VER1_6 ssHid;
485 CPUMSELREGHID_VER1_6 dsHid;
486 CPUMSELREGHID_VER1_6 fsHid;
487 CPUMSELREGHID_VER1_6 gsHid;
488 /** @} */
489
490 /** @} */
491
492 /** Control registers.
493 * @{ */
494 uint64_t cr0;
495 uint64_t cr2;
496 uint64_t cr3;
497 uint64_t cr4;
498 uint64_t cr8;
499 /** @} */
500
501 /** Debug registers.
502 * @{ */
503 uint64_t dr0;
504 uint64_t dr1;
505 uint64_t dr2;
506 uint64_t dr3;
507 uint64_t dr4; /**< @todo remove dr4 and dr5. */
508 uint64_t dr5;
509 uint64_t dr6;
510 uint64_t dr7;
511 /* DR8-15 are currently not supported */
512 /** @} */
513
514 /** Global Descriptor Table register. */
515 VBOXGDTR_VER1_6 gdtr;
516 uint16_t gdtrPadding;
517 uint32_t gdtrPadding64;/** @todo fix this hack */
518 /** Interrupt Descriptor Table register. */
519 VBOXIDTR_VER1_6 idtr;
520 uint16_t idtrPadding;
521 uint32_t idtrPadding64;/** @todo fix this hack */
522 /** The task register.
523 * Only the guest context uses all the members. */
524 RTSEL ldtr;
525 RTSEL ldtrPadding;
526 /** The task register.
527 * Only the guest context uses all the members. */
528 RTSEL tr;
529 RTSEL trPadding;
530
531 /** The sysenter msr registers.
532 * This member is not used by the hypervisor context. */
533 CPUMSYSENTER SysEnter;
534
535 /** System MSRs.
536 * @{ */
537 uint64_t msrEFER;
538 uint64_t msrSTAR;
539 uint64_t msrPAT;
540 uint64_t msrLSTAR;
541 uint64_t msrCSTAR;
542 uint64_t msrSFMASK;
543 uint64_t msrFSBASE;
544 uint64_t msrGSBASE;
545 uint64_t msrKERNELGSBASE;
546 /** @} */
547
548 /** Hidden selector registers.
549 * @{ */
550 CPUMSELREGHID_VER1_6 ldtrHid;
551 CPUMSELREGHID_VER1_6 trHid;
552 /** @} */
553
554 /** padding to get 32byte aligned size. */
555 uint32_t padding[2];
556} CPUMCTX_VER1_6;
557#pragma pack()
558#else /* VBOX_WITHOUT_UNNAMED_UNIONS */
559typedef struct CPUMCTX_VER1_6 CPUMCTX_VER1_6;
560#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
561
562/**
563 * Guest MSR state.
564 *
565 * @note Never change the order here because of saved stated!
566 */
567typedef union CPUMCTXMSR
568{
569 struct
570 {
571 uint64_t tscAux; /**< MSR_K8_TSC_AUX */
572 uint64_t miscEnable; /**< MSR_IA32_MISC_ENABLE */
573 } msr;
574 uint64_t au64[64];
575} CPUMCTXMSR;
576/** Pointer to the guest MSR state. */
577typedef CPUMCTXMSR *PCPUMCTXMSR;
578/** Pointer to the const guest MSR state. */
579typedef const CPUMCTXMSR *PCCPUMCTXMSR;
580
581/**
582 * The register set returned by a CPUID operation.
583 */
584typedef struct CPUMCPUID
585{
586 uint32_t eax;
587 uint32_t ebx;
588 uint32_t ecx;
589 uint32_t edx;
590} CPUMCPUID;
591/** Pointer to a CPUID leaf. */
592typedef CPUMCPUID *PCPUMCPUID;
593/** Pointer to a const CPUID leaf. */
594typedef const CPUMCPUID *PCCPUMCPUID;
595
596/** @} */
597
598RT_C_DECLS_END
599
600#endif
601
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