cpumctx.h@ 41218

Last change on this file since 41218 was 41218, checked in by vboxsync, 13 years ago
Tweaks for DTrace.
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2012 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_cpumctx_h
27	#define ___VBox_vmm_cpumctx_h
28
29	#include <iprt/types.h>
30	#include <iprt/x86.h>
31
32
33	RT_C_DECLS_BEGIN
34
35	/** @addgroup grp_cpum_ctx The CPUM Context Structures
36	* @ingroup grp_cpum
37	* @{
38	*/
39
40	/**
41	* Selector hidden registers.
42	*/
43	typedef struct CPUMSELREGHID
44	{
45	/** Base register.
46	*
47	* Long mode remarks:
48	* - Unused in long mode for CS, DS, ES, SS
49	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
50	* - 64 bits for TR & LDTR
51	*/
52	uint64_t u64Base;
53	/** Limit (expanded). */
54	uint32_t u32Limit;
55	/** Flags.
56	* This is the high 32-bit word of the descriptor entry.
57	* Only the flags, dpl and type are used. */
58	X86DESCATTR Attr;
59	} CPUMSELREGHID;
60
61
62	/**
63	* The sysenter register set.
64	*/
65	typedef struct CPUMSYSENTER
66	{
67	/** Ring 0 cs.
68	* This value + 8 is the Ring 0 ss.
69	* This value + 16 is the Ring 3 cs.
70	* This value + 24 is the Ring 3 ss.
71	*/
72	uint64_t cs;
73	/** Ring 0 eip. */
74	uint64_t eip;
75	/** Ring 0 esp. */
76	uint64_t esp;
77	} CPUMSYSENTER;
78
79	/**
80	* For compilers (like DTrace) that does not grok nameless unions, we have a
81	* little hack to make them palatable.
82	*/
83	#ifdef VBOX_FOR_DTRACE_LIB
84	# define CPUM_UNION_NAME u
85	#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
86	# define CPUM_UNION_NAME u
87	#else
88	# define CPUM_UNION_NAME
89	#endif
90
91
92	/**
93	* CPU context core.
94	*/
95	#ifndef VBOX_FOR_DTRACE_LIB
96	# pragma pack(1)
97	#endif
98	typedef struct CPUMCTXCORE
99	{
100	union
101	{
102	uint16_t di;
103	uint32_t edi;
104	uint64_t rdi;
105	} CPUM_UNION_NAME;
106	union
107	{
108	uint16_t si;
109	uint32_t esi;
110	uint64_t rsi;
111	} CPUM_UNION_NAME;
112	union
113	{
114	uint16_t bp;
115	uint32_t ebp;
116	uint64_t rbp;
117	} CPUM_UNION_NAME;
118	union
119	{
120	uint16_t ax;
121	uint32_t eax;
122	uint64_t rax;
123	} CPUM_UNION_NAME;
124	union
125	{
126	uint16_t bx;
127	uint32_t ebx;
128	uint64_t rbx;
129	} CPUM_UNION_NAME;
130	union
131	{
132	uint16_t dx;
133	uint32_t edx;
134	uint64_t rdx;
135	} CPUM_UNION_NAME;
136	union
137	{
138	uint16_t cx;
139	uint32_t ecx;
140	uint64_t rcx;
141	} CPUM_UNION_NAME;
142	union
143	{
144	uint16_t sp;
145	uint32_t esp;
146	uint64_t rsp;
147	} CPUM_UNION_NAME;
148	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
149	uint32_t lss_esp;
150	RTSEL ss;
151	RTSEL ssPadding;
152
153	RTSEL gs;
154	RTSEL gsPadding;
155	RTSEL fs;
156	RTSEL fsPadding;
157	RTSEL es;
158	RTSEL esPadding;
159	RTSEL ds;
160	RTSEL dsPadding;
161	RTSEL cs;
162	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
163
164	union
165	{
166	X86EFLAGS eflags;
167	X86RFLAGS rflags;
168	} CPUM_UNION_NAME;
169	union
170	{
171	uint16_t ip;
172	uint32_t eip;
173	uint64_t rip;
174	} CPUM_UNION_NAME;
175
176	uint64_t r8;
177	uint64_t r9;
178	uint64_t r10;
179	uint64_t r11;
180	uint64_t r12;
181	uint64_t r13;
182	uint64_t r14;
183	uint64_t r15;
184
185	/** Hidden selector registers.
186	* @{ */
187	CPUMSELREGHID esHid;
188	CPUMSELREGHID csHid;
189	CPUMSELREGHID ssHid;
190	CPUMSELREGHID dsHid;
191	CPUMSELREGHID fsHid;
192	CPUMSELREGHID gsHid;
193	/** @} */
194
195	} CPUMCTXCORE;
196
197	# ifndef VBOX_FOR_DTRACE_LIB
198	# pragma pack()
199	# endif
200
201
202	/**
203	* CPU context.
204	*/
205	#ifndef VBOX_FOR_DTRACE_LIB
206	# pragma pack(1)
207	#endif
208	typedef struct CPUMCTX
209	{
210	/** FPU state. (16-byte alignment)
211	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
212	* actual format or convert it (waste of time). */
213	X86FXSTATE fpu;
214
215	/** CPUMCTXCORE Part.
216	* @{ */
217	union
218	{
219	uint8_t dil;
220	uint16_t di;
221	uint32_t edi;
222	uint64_t rdi;
223	} CPUM_UNION_NAME;
224	union
225	{
226	uint8_t sil;
227	uint16_t si;
228	uint32_t esi;
229	uint64_t rsi;
230	} CPUM_UNION_NAME;
231	union
232	{
233	uint16_t bp;
234	uint32_t ebp;
235	uint64_t rbp;
236	} CPUM_UNION_NAME;
237	union
238	{
239	uint8_t al;
240	uint16_t ax;
241	uint32_t eax;
242	uint64_t rax;
243	} CPUM_UNION_NAME;
244	union
245	{
246	uint8_t bl;
247	uint16_t bx;
248	uint32_t ebx;
249	uint64_t rbx;
250	} CPUM_UNION_NAME;
251	union
252	{
253	uint8_t dl;
254	uint16_t dx;
255	uint32_t edx;
256	uint64_t rdx;
257	} CPUM_UNION_NAME;
258	union
259	{
260	uint8_t cl;
261	uint16_t cx;
262	uint32_t ecx;
263	uint64_t rcx;
264	} CPUM_UNION_NAME;
265	union
266	{
267	uint16_t sp;
268	uint32_t esp;
269	uint64_t rsp;
270	} CPUM_UNION_NAME;
271	/** @note lss esp, [] in the switcher needs some space, so we reserve it here
272	* instead of relying on the exact esp & ss layout as before (prevented
273	* us from using a union with rsp). */
274	uint32_t lss_esp;
275	RTSEL ss;
276	RTSEL ssPadding;
277
278	RTSEL gs;
279	RTSEL gsPadding;
280	RTSEL fs;
281	RTSEL fsPadding;
282	RTSEL es;
283	RTSEL esPadding;
284	RTSEL ds;
285	RTSEL dsPadding;
286	RTSEL cs;
287	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
288
289	union
290	{
291	X86EFLAGS eflags;
292	X86RFLAGS rflags;
293	} CPUM_UNION_NAME;
294	union
295	{
296	uint16_t ip;
297	uint32_t eip;
298	uint64_t rip;
299	} CPUM_UNION_NAME;
300
301	uint64_t r8;
302	uint64_t r9;
303	uint64_t r10;
304	uint64_t r11;
305	uint64_t r12;
306	uint64_t r13;
307	uint64_t r14;
308	uint64_t r15;
309
310	/** Hidden selector registers.
311	* @{ */
312	CPUMSELREGHID esHid;
313	CPUMSELREGHID csHid;
314	CPUMSELREGHID ssHid;
315	CPUMSELREGHID dsHid;
316	CPUMSELREGHID fsHid;
317	CPUMSELREGHID gsHid;
318	/** @} */
319
320	/** @} */
321
322	/** Control registers.
323	* @{ */
324	uint64_t cr0;
325	uint64_t cr2;
326	uint64_t cr3;
327	uint64_t cr4;
328	/** @} */
329
330	/** Debug registers.
331	* @remarks DR4 and DR5 should not be used since they are aliases for
332	* DR6 and DR7 respectively on both AMD and Intel CPUs.
333	* @remarks DR8-15 are currently not supported by AMD or Intel, so
334	* neither do we.
335	* @{ */
336	uint64_t dr[8];
337	/** @} */
338
339	/** Global Descriptor Table register. */
340	VBOXGDTR gdtr;
341	uint16_t gdtrPadding;
342	/** Interrupt Descriptor Table register. */
343	VBOXIDTR idtr;
344	uint16_t idtrPadding;
345	/** The task register.
346	* Only the guest context uses all the members. */
347	RTSEL ldtr;
348	RTSEL ldtrPadding;
349	/** The task register.
350	* Only the guest context uses all the members. */
351	RTSEL tr;
352	RTSEL trPadding;
353
354	/** The sysenter msr registers.
355	* This member is not used by the hypervisor context. */
356	CPUMSYSENTER SysEnter;
357
358	/** System MSRs.
359	* @{ */
360	uint64_t msrEFER;
361	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
362	uint64_t msrPAT;
363	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
364	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
365	uint64_t msrSFMASK; /*< syscall flag mask. /
366	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
367	/** @} */
368
369	/** Hidden selector registers.
370	* @{ */
371	CPUMSELREGHID ldtrHid;
372	CPUMSELREGHID trHid;
373	/** @} */
374
375	# if 0
376	/** Padding to align the size on a 64 byte boundary. */
377	uint32_t padding[6];
378	# endif
379	} CPUMCTX;
380	# ifndef VBOX_FOR_DTRACE_LIB
381	# pragma pack()
382	# endif
383
384	#ifndef VBOX_FOR_DTRACE_LIB
385
386	/**
387	* Gets the CPUMCTXCORE part of a CPUMCTX.
388	*/
389	# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
390
391
392	/**
393	* Selector hidden registers, for version 1.6 saved state.
394	*/
395	typedef struct CPUMSELREGHID_VER1_6
396	{
397	/** Base register. */
398	uint32_t u32Base;
399	/** Limit (expanded). */
400	uint32_t u32Limit;
401	/** Flags.
402	* This is the high 32-bit word of the descriptor entry.
403	* Only the flags, dpl and type are used. */
404	X86DESCATTR Attr;
405	} CPUMSELREGHID_VER1_6;
406
407	/**
408	* CPU context, for version 1.6 saved state.
409	* @remarks PATM uses this, which is why it has to be here.
410	*/
411	# pragma pack(1)
412	typedef struct CPUMCTX_VER1_6
413	{
414	/** FPU state. (16-byte alignment)
415	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
416	* actual format or convert it (waste of time). */
417	X86FXSTATE fpu;
418
419	/** CPUMCTXCORE Part.
420	* @{ */
421	union
422	{
423	uint32_t edi;
424	uint64_t rdi;
425	} CPUM_UNION_NAME;
426	union
427	{
428	uint32_t esi;
429	uint64_t rsi;
430	} CPUM_UNION_NAME;
431	union
432	{
433	uint32_t ebp;
434	uint64_t rbp;
435	} CPUM_UNION_NAME;
436	union
437	{
438	uint32_t eax;
439	uint64_t rax;
440	} CPUM_UNION_NAME;
441	union
442	{
443	uint32_t ebx;
444	uint64_t rbx;
445	} CPUM_UNION_NAME;
446	union
447	{
448	uint32_t edx;
449	uint64_t rdx;
450	} CPUM_UNION_NAME;
451	union
452	{
453	uint32_t ecx;
454	uint64_t rcx;
455	} CPUM_UNION_NAME;
456	/** @note We rely on the exact layout, because we use lss esp, [] in the
457	* switcher. */
458	uint32_t esp;
459	RTSEL ss;
460	RTSEL ssPadding;
461	/* Note: no overlap with esp here. */
462	uint64_t rsp_notused;
463
464	RTSEL gs;
465	RTSEL gsPadding;
466	RTSEL fs;
467	RTSEL fsPadding;
468	RTSEL es;
469	RTSEL esPadding;
470	RTSEL ds;
471	RTSEL dsPadding;
472	RTSEL cs;
473	RTSEL csPadding[3]; /*< 3 words to force 8 byte alignment for the remainder. /
474
475	union
476	{
477	X86EFLAGS eflags;
478	X86RFLAGS rflags;
479	} CPUM_UNION_NAME;
480	union
481	{
482	uint32_t eip;
483	uint64_t rip;
484	} CPUM_UNION_NAME;
485
486	uint64_t r8;
487	uint64_t r9;
488	uint64_t r10;
489	uint64_t r11;
490	uint64_t r12;
491	uint64_t r13;
492	uint64_t r14;
493	uint64_t r15;
494
495	/** Hidden selector registers.
496	* @{ */
497	CPUMSELREGHID_VER1_6 esHid;
498	CPUMSELREGHID_VER1_6 csHid;
499	CPUMSELREGHID_VER1_6 ssHid;
500	CPUMSELREGHID_VER1_6 dsHid;
501	CPUMSELREGHID_VER1_6 fsHid;
502	CPUMSELREGHID_VER1_6 gsHid;
503	/** @} */
504
505	/** @} */
506
507	/** Control registers.
508	* @{ */
509	uint64_t cr0;
510	uint64_t cr2;
511	uint64_t cr3;
512	uint64_t cr4;
513	uint64_t cr8;
514	/** @} */
515
516	/** Debug registers.
517	* @{ */
518	uint64_t dr0;
519	uint64_t dr1;
520	uint64_t dr2;
521	uint64_t dr3;
522	uint64_t dr4; /*< @todo remove dr4 and dr5. /
523	uint64_t dr5;
524	uint64_t dr6;
525	uint64_t dr7;
526	/* DR8-15 are currently not supported */
527	/** @} */
528
529	/** Global Descriptor Table register. */
530	VBOXGDTR_VER1_6 gdtr;
531	uint16_t gdtrPadding;
532	uint32_t gdtrPadding64;/** @todo fix this hack */
533	/** Interrupt Descriptor Table register. */
534	VBOXIDTR_VER1_6 idtr;
535	uint16_t idtrPadding;
536	uint32_t idtrPadding64;/** @todo fix this hack */
537	/** The task register.
538	* Only the guest context uses all the members. */
539	RTSEL ldtr;
540	RTSEL ldtrPadding;
541	/** The task register.
542	* Only the guest context uses all the members. */
543	RTSEL tr;
544	RTSEL trPadding;
545
546	/** The sysenter msr registers.
547	* This member is not used by the hypervisor context. */
548	CPUMSYSENTER SysEnter;
549
550	/** System MSRs.
551	* @{ */
552	uint64_t msrEFER;
553	uint64_t msrSTAR;
554	uint64_t msrPAT;
555	uint64_t msrLSTAR;
556	uint64_t msrCSTAR;
557	uint64_t msrSFMASK;
558	uint64_t msrFSBASE;
559	uint64_t msrGSBASE;
560	uint64_t msrKERNELGSBASE;
561	/** @} */
562
563	/** Hidden selector registers.
564	* @{ */
565	CPUMSELREGHID_VER1_6 ldtrHid;
566	CPUMSELREGHID_VER1_6 trHid;
567	/** @} */
568
569	/** padding to get 32byte aligned size. */
570	uint32_t padding[2];
571	} CPUMCTX_VER1_6;
572	# pragma pack()
573
574	#endif /* VBOX_FOR_DTRACE_LIB */
575
576	/**
577	* Additional guest MSRs (i.e. not part of the CPU context structure).
578	*
579	* @remarks Never change the order here because of the saved stated! The size
580	* can in theory be changed, but keep older VBox versions in mind.
581	*/
582	typedef union CPUMCTXMSRS
583	{
584	struct
585	{
586	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
587	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
588	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
589	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
590	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
591	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
592	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
593	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
594	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
595	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
596	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
597	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
598	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
599	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
600	} msr;
601	uint64_t au64[64];
602	} CPUMCTXMSRS;
603	/** Pointer to the guest MSR state. */
604	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
605	/** Pointer to the const guest MSR state. */
606	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
607
608	/**
609	* The register set returned by a CPUID operation.
610	*/
611	typedef struct CPUMCPUID
612	{
613	uint32_t eax;
614	uint32_t ebx;
615	uint32_t ecx;
616	uint32_t edx;
617	} CPUMCPUID;
618	/** Pointer to a CPUID leaf. */
619	typedef CPUMCPUID *PCPUMCPUID;
620	/** Pointer to a const CPUID leaf. */
621	typedef const CPUMCPUID *PCCPUMCPUID;
622
623	/** @} */
624
625	RT_C_DECLS_END
626
627	#endif
628

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 41218

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