VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 42000

Last change on this file since 42000 was 41908, checked in by vboxsync, 12 years ago

Check loaded selector register the GDT changes.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 11.9 KB
Line 
1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/x86.h>
31# include <VBox/types.h>
32#else
33# pragma D depends_on library x86.d
34#endif
35
36
37RT_C_DECLS_BEGIN
38
39/** @addgroup grp_cpum_ctx The CPUM Context Structures
40 * @ingroup grp_cpum
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREG
48{
49 /** The selector register. */
50 RTSEL Sel;
51 /** Padding, don't use. */
52 RTSEL PaddingSel;
53 /** The selector which info resides in u64Base, u32Limit and Attr, provided
54 * that CPUMSELREG_FLAGS_VALID is set. */
55 RTSEL ValidSel;
56 /** Flags, see CPUMSELREG_FLAGS_XXX. */
57 uint16_t fFlags;
58
59 /** Base register.
60 *
61 * Long mode remarks:
62 * - Unused in long mode for CS, DS, ES, SS
63 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
64 * - 64 bits for TR & LDTR
65 */
66 uint64_t u64Base;
67 /** Limit (expanded). */
68 uint32_t u32Limit;
69 /** Flags.
70 * This is the high 32-bit word of the descriptor entry.
71 * Only the flags, dpl and type are used. */
72 X86DESCATTR Attr;
73} CPUMSELREG;
74
75/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
76 * @{ */
77#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
78#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
79/** @} */
80
81/** Old type used for the hidden register part.
82 * @deprecated */
83typedef CPUMSELREG CPUMSELREGHID;
84
85/**
86 * The sysenter register set.
87 */
88typedef struct CPUMSYSENTER
89{
90 /** Ring 0 cs.
91 * This value + 8 is the Ring 0 ss.
92 * This value + 16 is the Ring 3 cs.
93 * This value + 24 is the Ring 3 ss.
94 */
95 uint64_t cs;
96 /** Ring 0 eip. */
97 uint64_t eip;
98 /** Ring 0 esp. */
99 uint64_t esp;
100} CPUMSYSENTER;
101
102/**
103 * For compilers (like DTrace) that does not grok nameless unions, we have a
104 * little hack to make them palatable.
105 */
106#ifdef VBOX_FOR_DTRACE_LIB
107# define CPUM_UNION_NAME(a_Nm) a_Nm
108#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
109# define CPUM_UNION_NAME(a_Nm) a_Nm
110#else
111# define CPUM_UNION_NAME(a_Nm)
112#endif
113
114
115/**
116 * CPU context core.
117 *
118 * @todo eliminate this structure!
119 */
120#pragma pack(1)
121typedef struct CPUMCTXCORE
122{
123 /** @name General Register.
124 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
125 * an array starting a rax.
126 * @{ */
127 union
128 {
129 uint8_t al;
130 uint16_t ax;
131 uint32_t eax;
132 uint64_t rax;
133 } CPUM_UNION_NAME(rax);
134 union
135 {
136 uint8_t cl;
137 uint16_t cx;
138 uint32_t ecx;
139 uint64_t rcx;
140 } CPUM_UNION_NAME(rcx);
141 union
142 {
143 uint8_t dl;
144 uint16_t dx;
145 uint32_t edx;
146 uint64_t rdx;
147 } CPUM_UNION_NAME(rdx);
148 union
149 {
150 uint8_t bl;
151 uint16_t bx;
152 uint32_t ebx;
153 uint64_t rbx;
154 } CPUM_UNION_NAME(rbx);
155 union
156 {
157 uint16_t sp;
158 uint32_t esp;
159 uint64_t rsp;
160 } CPUM_UNION_NAME(rsp);
161 union
162 {
163 uint16_t bp;
164 uint32_t ebp;
165 uint64_t rbp;
166 } CPUM_UNION_NAME(rbp);
167 union
168 {
169 uint8_t sil;
170 uint16_t si;
171 uint32_t esi;
172 uint64_t rsi;
173 } CPUM_UNION_NAME(rsi);
174 union
175 {
176 uint8_t dil;
177 uint16_t di;
178 uint32_t edi;
179 uint64_t rdi;
180 } CPUM_UNION_NAME(rdi);
181 uint64_t r8;
182 uint64_t r9;
183 uint64_t r10;
184 uint64_t r11;
185 uint64_t r12;
186 uint64_t r13;
187 uint64_t r14;
188 uint64_t r15;
189 /** @} */
190
191 /** @name Segment registers.
192 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
193 * an array starting a es.
194 * @{ */
195 CPUMSELREG es;
196 CPUMSELREG cs;
197 CPUMSELREG ss;
198 CPUMSELREG ds;
199 CPUMSELREG fs;
200 CPUMSELREG gs;
201 /** @} */
202
203 /** The program counter. */
204 union
205 {
206 uint16_t ip;
207 uint32_t eip;
208 uint64_t rip;
209 } CPUM_UNION_NAME(rip);
210
211 /** The flags register. */
212 union
213 {
214 X86EFLAGS eflags;
215 X86RFLAGS rflags;
216 } CPUM_UNION_NAME(rflags);
217
218} CPUMCTXCORE;
219#pragma pack()
220
221
222/**
223 * CPU context.
224 */
225#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
226typedef struct CPUMCTX
227{
228 /** FPU state. (16-byte alignment)
229 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
230 * actual format or convert it (waste of time). */
231 X86FXSTATE fpu;
232
233 /** CPUMCTXCORE Part.
234 * @{ */
235
236 /** @name General Register.
237 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
238 * an array starting at rax.
239 * @{ */
240 union
241 {
242 uint8_t al;
243 uint16_t ax;
244 uint32_t eax;
245 uint64_t rax;
246 } CPUM_UNION_NAME(rax);
247 union
248 {
249 uint8_t cl;
250 uint16_t cx;
251 uint32_t ecx;
252 uint64_t rcx;
253 } CPUM_UNION_NAME(rcx);
254 union
255 {
256 uint8_t dl;
257 uint16_t dx;
258 uint32_t edx;
259 uint64_t rdx;
260 } CPUM_UNION_NAME(rdx);
261 union
262 {
263 uint8_t bl;
264 uint16_t bx;
265 uint32_t ebx;
266 uint64_t rbx;
267 } CPUM_UNION_NAME(rbx);
268 union
269 {
270 uint16_t sp;
271 uint32_t esp;
272 uint64_t rsp;
273 } CPUM_UNION_NAME(rsp);
274 union
275 {
276 uint16_t bp;
277 uint32_t ebp;
278 uint64_t rbp;
279 } CPUM_UNION_NAME(rbp);
280 union
281 {
282 uint8_t sil;
283 uint16_t si;
284 uint32_t esi;
285 uint64_t rsi;
286 } CPUM_UNION_NAME(rsi);
287 union
288 {
289 uint8_t dil;
290 uint16_t di;
291 uint32_t edi;
292 uint64_t rdi;
293 } CPUM_UNION_NAME(rdi);
294 uint64_t r8;
295 uint64_t r9;
296 uint64_t r10;
297 uint64_t r11;
298 uint64_t r12;
299 uint64_t r13;
300 uint64_t r14;
301 uint64_t r15;
302 /** @} */
303
304 /** @name Segment registers.
305 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
306 * an array starting at es.
307 * @{ */
308 CPUMSELREG es;
309 CPUMSELREG cs;
310 CPUMSELREG ss;
311 CPUMSELREG ds;
312 CPUMSELREG fs;
313 CPUMSELREG gs;
314 /** @} */
315
316 /** The program counter. */
317 union
318 {
319 uint16_t ip;
320 uint32_t eip;
321 uint64_t rip;
322 } CPUM_UNION_NAME(rip);
323
324 /** The flags register. */
325 union
326 {
327 X86EFLAGS eflags;
328 X86RFLAGS rflags;
329 } CPUM_UNION_NAME(rflags);
330
331 /** @} */ /*(CPUMCTXCORE)*/
332
333
334 /** @name Control registers.
335 * @{ */
336 uint64_t cr0;
337 uint64_t cr2;
338 uint64_t cr3;
339 uint64_t cr4;
340 /** @} */
341
342 /** Debug registers.
343 * @remarks DR4 and DR5 should not be used since they are aliases for
344 * DR6 and DR7 respectively on both AMD and Intel CPUs.
345 * @remarks DR8-15 are currently not supported by AMD or Intel, so
346 * neither do we.
347 */
348 uint64_t dr[8];
349
350 /** Padding before the structure so the 64-bit member is correctly aligned.
351 * @todo fix this structure! */
352 uint16_t gdtrPadding[3];
353 /** Global Descriptor Table register. */
354 VBOXGDTR gdtr;
355
356 /** Padding before the structure so the 64-bit member is correctly aligned.
357 * @todo fix this structure! */
358 uint16_t idtrPadding[3];
359 /** Interrupt Descriptor Table register. */
360 VBOXIDTR idtr;
361
362 /** The task register.
363 * Only the guest context uses all the members. */
364 CPUMSELREG ldtr;
365 /** The task register.
366 * Only the guest context uses all the members. */
367 CPUMSELREG tr;
368
369 /** The sysenter msr registers.
370 * This member is not used by the hypervisor context. */
371 CPUMSYSENTER SysEnter;
372
373 /** @name System MSRs.
374 * @{ */
375 uint64_t msrEFER;
376 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
377 uint64_t msrPAT; /**< Page attribute table. */
378 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
379 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
380 uint64_t msrSFMASK; /**< syscall flag mask. */
381 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
382 /** @} */
383
384 /** Size padding. */
385 uint32_t au32SizePadding[8];
386} CPUMCTX;
387#pragma pack()
388
389#ifndef VBOX_FOR_DTRACE_LIB
390
391/**
392 * Gets the CPUMCTXCORE part of a CPUMCTX.
393 */
394# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
395
396#endif /* VBOX_FOR_DTRACE_LIB */
397
398/**
399 * Additional guest MSRs (i.e. not part of the CPU context structure).
400 *
401 * @remarks Never change the order here because of the saved stated! The size
402 * can in theory be changed, but keep older VBox versions in mind.
403 */
404typedef union CPUMCTXMSRS
405{
406 struct
407 {
408 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
409 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
410 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
411 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
412 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
413 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
414 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
415 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
416 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
417 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
418 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
419 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
420 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
421 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
422 } msr;
423 uint64_t au64[64];
424} CPUMCTXMSRS;
425/** Pointer to the guest MSR state. */
426typedef CPUMCTXMSRS *PCPUMCTXMSRS;
427/** Pointer to the const guest MSR state. */
428typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
429
430/**
431 * The register set returned by a CPUID operation.
432 */
433typedef struct CPUMCPUID
434{
435 uint32_t eax;
436 uint32_t ebx;
437 uint32_t ecx;
438 uint32_t edx;
439} CPUMCPUID;
440/** Pointer to a CPUID leaf. */
441typedef CPUMCPUID *PCPUMCPUID;
442/** Pointer to a const CPUID leaf. */
443typedef const CPUMCPUID *PCCPUMCPUID;
444
445/** @} */
446
447RT_C_DECLS_END
448
449#endif
450
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette