VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 42165

Last change on this file since 42165 was 42165, checked in by vboxsync, 12 years ago

CPUMIsGuestIn64BitCode/CPUMIsGuestIn64BitCodeEx changes together with some early lazily loading of hidden selectors (raw-mode).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 12.1 KB
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1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/x86.h>
31# include <VBox/types.h>
32#else
33# pragma D depends_on library x86.d
34#endif
35
36
37RT_C_DECLS_BEGIN
38
39/** @addgroup grp_cpum_ctx The CPUM Context Structures
40 * @ingroup grp_cpum
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREG
48{
49 /** The selector register. */
50 RTSEL Sel;
51 /** Padding, don't use. */
52 RTSEL PaddingSel;
53 /** The selector which info resides in u64Base, u32Limit and Attr, provided
54 * that CPUMSELREG_FLAGS_VALID is set. */
55 RTSEL ValidSel;
56 /** Flags, see CPUMSELREG_FLAGS_XXX. */
57 uint16_t fFlags;
58
59 /** Base register.
60 *
61 * Long mode remarks:
62 * - Unused in long mode for CS, DS, ES, SS
63 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
64 * - 64 bits for TR & LDTR
65 */
66 uint64_t u64Base;
67 /** Limit (expanded). */
68 uint32_t u32Limit;
69 /** Flags.
70 * This is the high 32-bit word of the descriptor entry.
71 * Only the flags, dpl and type are used. */
72 X86DESCATTR Attr;
73} CPUMSELREG;
74
75/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
76 * @{ */
77#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
78#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
79/** @} */
80
81/** Checks if the hidden parts of the selector register are valid. */
82#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pSelReg) ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
83 && (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
84
85/** Old type used for the hidden register part.
86 * @deprecated */
87typedef CPUMSELREG CPUMSELREGHID;
88
89/**
90 * The sysenter register set.
91 */
92typedef struct CPUMSYSENTER
93{
94 /** Ring 0 cs.
95 * This value + 8 is the Ring 0 ss.
96 * This value + 16 is the Ring 3 cs.
97 * This value + 24 is the Ring 3 ss.
98 */
99 uint64_t cs;
100 /** Ring 0 eip. */
101 uint64_t eip;
102 /** Ring 0 esp. */
103 uint64_t esp;
104} CPUMSYSENTER;
105
106/**
107 * For compilers (like DTrace) that does not grok nameless unions, we have a
108 * little hack to make them palatable.
109 */
110#ifdef VBOX_FOR_DTRACE_LIB
111# define CPUM_UNION_NAME(a_Nm) a_Nm
112#elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
113# define CPUM_UNION_NAME(a_Nm) a_Nm
114#else
115# define CPUM_UNION_NAME(a_Nm)
116#endif
117
118
119/**
120 * CPU context core.
121 *
122 * @todo eliminate this structure!
123 */
124#pragma pack(1)
125typedef struct CPUMCTXCORE
126{
127 /** @name General Register.
128 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
129 * an array starting a rax.
130 * @{ */
131 union
132 {
133 uint8_t al;
134 uint16_t ax;
135 uint32_t eax;
136 uint64_t rax;
137 } CPUM_UNION_NAME(rax);
138 union
139 {
140 uint8_t cl;
141 uint16_t cx;
142 uint32_t ecx;
143 uint64_t rcx;
144 } CPUM_UNION_NAME(rcx);
145 union
146 {
147 uint8_t dl;
148 uint16_t dx;
149 uint32_t edx;
150 uint64_t rdx;
151 } CPUM_UNION_NAME(rdx);
152 union
153 {
154 uint8_t bl;
155 uint16_t bx;
156 uint32_t ebx;
157 uint64_t rbx;
158 } CPUM_UNION_NAME(rbx);
159 union
160 {
161 uint16_t sp;
162 uint32_t esp;
163 uint64_t rsp;
164 } CPUM_UNION_NAME(rsp);
165 union
166 {
167 uint16_t bp;
168 uint32_t ebp;
169 uint64_t rbp;
170 } CPUM_UNION_NAME(rbp);
171 union
172 {
173 uint8_t sil;
174 uint16_t si;
175 uint32_t esi;
176 uint64_t rsi;
177 } CPUM_UNION_NAME(rsi);
178 union
179 {
180 uint8_t dil;
181 uint16_t di;
182 uint32_t edi;
183 uint64_t rdi;
184 } CPUM_UNION_NAME(rdi);
185 uint64_t r8;
186 uint64_t r9;
187 uint64_t r10;
188 uint64_t r11;
189 uint64_t r12;
190 uint64_t r13;
191 uint64_t r14;
192 uint64_t r15;
193 /** @} */
194
195 /** @name Segment registers.
196 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
197 * an array starting a es.
198 * @{ */
199 CPUMSELREG es;
200 CPUMSELREG cs;
201 CPUMSELREG ss;
202 CPUMSELREG ds;
203 CPUMSELREG fs;
204 CPUMSELREG gs;
205 /** @} */
206
207 /** The program counter. */
208 union
209 {
210 uint16_t ip;
211 uint32_t eip;
212 uint64_t rip;
213 } CPUM_UNION_NAME(rip);
214
215 /** The flags register. */
216 union
217 {
218 X86EFLAGS eflags;
219 X86RFLAGS rflags;
220 } CPUM_UNION_NAME(rflags);
221
222} CPUMCTXCORE;
223#pragma pack()
224
225
226/**
227 * CPU context.
228 */
229#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
230typedef struct CPUMCTX
231{
232 /** FPU state. (16-byte alignment)
233 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
234 * actual format or convert it (waste of time). */
235 X86FXSTATE fpu;
236
237 /** CPUMCTXCORE Part.
238 * @{ */
239
240 /** @name General Register.
241 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
242 * an array starting at rax.
243 * @{ */
244 union
245 {
246 uint8_t al;
247 uint16_t ax;
248 uint32_t eax;
249 uint64_t rax;
250 } CPUM_UNION_NAME(rax);
251 union
252 {
253 uint8_t cl;
254 uint16_t cx;
255 uint32_t ecx;
256 uint64_t rcx;
257 } CPUM_UNION_NAME(rcx);
258 union
259 {
260 uint8_t dl;
261 uint16_t dx;
262 uint32_t edx;
263 uint64_t rdx;
264 } CPUM_UNION_NAME(rdx);
265 union
266 {
267 uint8_t bl;
268 uint16_t bx;
269 uint32_t ebx;
270 uint64_t rbx;
271 } CPUM_UNION_NAME(rbx);
272 union
273 {
274 uint16_t sp;
275 uint32_t esp;
276 uint64_t rsp;
277 } CPUM_UNION_NAME(rsp);
278 union
279 {
280 uint16_t bp;
281 uint32_t ebp;
282 uint64_t rbp;
283 } CPUM_UNION_NAME(rbp);
284 union
285 {
286 uint8_t sil;
287 uint16_t si;
288 uint32_t esi;
289 uint64_t rsi;
290 } CPUM_UNION_NAME(rsi);
291 union
292 {
293 uint8_t dil;
294 uint16_t di;
295 uint32_t edi;
296 uint64_t rdi;
297 } CPUM_UNION_NAME(rdi);
298 uint64_t r8;
299 uint64_t r9;
300 uint64_t r10;
301 uint64_t r11;
302 uint64_t r12;
303 uint64_t r13;
304 uint64_t r14;
305 uint64_t r15;
306 /** @} */
307
308 /** @name Segment registers.
309 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
310 * an array starting at es.
311 * @{ */
312 CPUMSELREG es;
313 CPUMSELREG cs;
314 CPUMSELREG ss;
315 CPUMSELREG ds;
316 CPUMSELREG fs;
317 CPUMSELREG gs;
318 /** @} */
319
320 /** The program counter. */
321 union
322 {
323 uint16_t ip;
324 uint32_t eip;
325 uint64_t rip;
326 } CPUM_UNION_NAME(rip);
327
328 /** The flags register. */
329 union
330 {
331 X86EFLAGS eflags;
332 X86RFLAGS rflags;
333 } CPUM_UNION_NAME(rflags);
334
335 /** @} */ /*(CPUMCTXCORE)*/
336
337
338 /** @name Control registers.
339 * @{ */
340 uint64_t cr0;
341 uint64_t cr2;
342 uint64_t cr3;
343 uint64_t cr4;
344 /** @} */
345
346 /** Debug registers.
347 * @remarks DR4 and DR5 should not be used since they are aliases for
348 * DR6 and DR7 respectively on both AMD and Intel CPUs.
349 * @remarks DR8-15 are currently not supported by AMD or Intel, so
350 * neither do we.
351 */
352 uint64_t dr[8];
353
354 /** Padding before the structure so the 64-bit member is correctly aligned.
355 * @todo fix this structure! */
356 uint16_t gdtrPadding[3];
357 /** Global Descriptor Table register. */
358 VBOXGDTR gdtr;
359
360 /** Padding before the structure so the 64-bit member is correctly aligned.
361 * @todo fix this structure! */
362 uint16_t idtrPadding[3];
363 /** Interrupt Descriptor Table register. */
364 VBOXIDTR idtr;
365
366 /** The task register.
367 * Only the guest context uses all the members. */
368 CPUMSELREG ldtr;
369 /** The task register.
370 * Only the guest context uses all the members. */
371 CPUMSELREG tr;
372
373 /** The sysenter msr registers.
374 * This member is not used by the hypervisor context. */
375 CPUMSYSENTER SysEnter;
376
377 /** @name System MSRs.
378 * @{ */
379 uint64_t msrEFER;
380 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
381 uint64_t msrPAT; /**< Page attribute table. */
382 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
383 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
384 uint64_t msrSFMASK; /**< syscall flag mask. */
385 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
386 /** @} */
387
388 /** Size padding. */
389 uint32_t au32SizePadding[8];
390} CPUMCTX;
391#pragma pack()
392
393#ifndef VBOX_FOR_DTRACE_LIB
394
395/**
396 * Gets the CPUMCTXCORE part of a CPUMCTX.
397 */
398# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
399
400#endif /* VBOX_FOR_DTRACE_LIB */
401
402/**
403 * Additional guest MSRs (i.e. not part of the CPU context structure).
404 *
405 * @remarks Never change the order here because of the saved stated! The size
406 * can in theory be changed, but keep older VBox versions in mind.
407 */
408typedef union CPUMCTXMSRS
409{
410 struct
411 {
412 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
413 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
414 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
415 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
416 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
417 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
418 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
419 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
420 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
421 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
422 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
423 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
424 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
425 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
426 } msr;
427 uint64_t au64[64];
428} CPUMCTXMSRS;
429/** Pointer to the guest MSR state. */
430typedef CPUMCTXMSRS *PCPUMCTXMSRS;
431/** Pointer to the const guest MSR state. */
432typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
433
434/**
435 * The register set returned by a CPUID operation.
436 */
437typedef struct CPUMCPUID
438{
439 uint32_t eax;
440 uint32_t ebx;
441 uint32_t ecx;
442 uint32_t edx;
443} CPUMCPUID;
444/** Pointer to a CPUID leaf. */
445typedef CPUMCPUID *PCPUMCPUID;
446/** Pointer to a const CPUID leaf. */
447typedef const CPUMCPUID *PCCPUMCPUID;
448
449/** @} */
450
451RT_C_DECLS_END
452
453#endif
454
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