1 | /** @file
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2 | * CPUM - CPU Monitor(/ Manager), Context Structures.
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2016 Oracle Corporation
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | */
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25 |
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26 | #ifndef ___VBox_vmm_cpumctx_h
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27 | #define ___VBox_vmm_cpumctx_h
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28 |
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29 | #ifndef VBOX_FOR_DTRACE_LIB
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30 | # include <iprt/x86.h>
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31 | # include <VBox/types.h>
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32 | # include <VBox/vmm/hm_svm.h>
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33 | #else
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34 | # pragma D depends_on library x86.d
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35 | #endif
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36 |
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37 |
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38 | RT_C_DECLS_BEGIN
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39 |
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40 | /** @defgroup grp_cpum_ctx The CPUM Context Structures
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41 | * @ingroup grp_cpum
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42 | * @{
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43 | */
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44 |
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45 | /**
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46 | * Selector hidden registers.
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47 | */
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48 | typedef struct CPUMSELREG
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49 | {
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50 | /** The selector register. */
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51 | RTSEL Sel;
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52 | /** Padding, don't use. */
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53 | RTSEL PaddingSel;
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54 | /** The selector which info resides in u64Base, u32Limit and Attr, provided
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55 | * that CPUMSELREG_FLAGS_VALID is set. */
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56 | RTSEL ValidSel;
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57 | /** Flags, see CPUMSELREG_FLAGS_XXX. */
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58 | uint16_t fFlags;
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59 |
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60 | /** Base register.
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61 | *
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62 | * Long mode remarks:
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63 | * - Unused in long mode for CS, DS, ES, SS
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64 | * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
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65 | * - 64 bits for TR & LDTR
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66 | */
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67 | uint64_t u64Base;
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68 | /** Limit (expanded). */
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69 | uint32_t u32Limit;
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70 | /** Flags.
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71 | * This is the high 32-bit word of the descriptor entry.
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72 | * Only the flags, dpl and type are used. */
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73 | X86DESCATTR Attr;
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74 | } CPUMSELREG;
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75 | #ifndef VBOX_FOR_DTRACE_LIB
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76 | AssertCompileSize(CPUMSELREG, 24);
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77 | #endif
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78 |
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79 | /** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
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80 | * @{ */
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81 | #define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
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82 | #define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
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83 | #define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
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84 | /** @} */
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85 |
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86 | /** Checks if the hidden parts of the selector register are valid. */
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87 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
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88 | # define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
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89 | ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
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90 | && ( (a_pSelReg)->ValidSel == (a_pSelReg)->Sel \
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91 | || ( (a_pVCpu) /*!= NULL*/ \
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92 | && (a_pSelReg)->ValidSel == ((a_pSelReg)->Sel & X86_SEL_MASK_OFF_RPL) \
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93 | && ((a_pSelReg)->Sel & X86_SEL_RPL) == 1 \
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94 | && ((a_pSelReg)->ValidSel & X86_SEL_RPL) == 0 \
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95 | && CPUMIsGuestInRawMode(a_pVCpu) \
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96 | ) \
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97 | ) \
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98 | )
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99 | #else
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100 | # define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
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101 | ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
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102 | && (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
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103 | #endif
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104 |
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105 | /** Old type used for the hidden register part.
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106 | * @deprecated */
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107 | typedef CPUMSELREG CPUMSELREGHID;
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108 |
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109 | /**
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110 | * The sysenter register set.
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111 | */
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112 | typedef struct CPUMSYSENTER
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113 | {
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114 | /** Ring 0 cs.
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115 | * This value + 8 is the Ring 0 ss.
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116 | * This value + 16 is the Ring 3 cs.
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117 | * This value + 24 is the Ring 3 ss.
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118 | */
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119 | uint64_t cs;
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120 | /** Ring 0 eip. */
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121 | uint64_t eip;
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122 | /** Ring 0 esp. */
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123 | uint64_t esp;
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124 | } CPUMSYSENTER;
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125 |
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126 | /** @def CPUM_UNION_NM
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127 | * For compilers (like DTrace) that does not grok nameless unions, we have a
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128 | * little hack to make them palatable.
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129 | */
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130 | /** @def CPUM_STRUCT_NM
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131 | * For compilers (like DTrace) that does not grok nameless structs (it is
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132 | * non-standard C++), we have a little hack to make them palatable.
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133 | */
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134 | #ifdef VBOX_FOR_DTRACE_LIB
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135 | # define CPUM_UNION_NM(a_Nm) a_Nm
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136 | # define CPUM_STRUCT_NM(a_Nm) a_Nm
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137 | #elif defined(VBOX_WITHOUT_UNNAMED_UNIONS)
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138 | # define CPUM_UNION_NM(a_Nm) a_Nm
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139 | # define CPUM_STRUCT_NM(a_Nm) a_Nm
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140 | #else
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141 | # define CPUM_UNION_NM(a_Nm)
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142 | # define CPUM_STRUCT_NM(a_Nm)
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143 | #endif
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144 | /** @def CPUM_UNION_STRUCT_NM
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145 | * Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
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146 | * the screen in the compile time assertions.
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147 | */
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148 | #define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
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149 |
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150 | /** A general register (union). */
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151 | typedef union CPUMCTXGREG
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152 | {
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153 | /** Natural unsigned integer view. */
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154 | uint64_t u;
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155 | /** 64-bit view. */
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156 | uint64_t u64;
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157 | /** 32-bit view. */
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158 | uint32_t u32;
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159 | /** 16-bit view. */
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160 | uint16_t u16;
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161 | /** 8-bit view. */
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162 | uint8_t u8;
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163 | /** 8-bit low/high view. */
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164 | RT_GCC_EXTENSION struct
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165 | {
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166 | /** Low byte (al, cl, dl, bl, ++). */
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167 | uint8_t bLo;
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168 | /** High byte in the first word - ah, ch, dh, bh. */
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169 | uint8_t bHi;
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170 | } CPUM_STRUCT_NM(s);
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171 | } CPUMCTXGREG;
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172 | #ifndef VBOX_FOR_DTRACE_LIB
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173 | AssertCompileSize(CPUMCTXGREG, 8);
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174 | AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
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175 | AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
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176 | #endif
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177 |
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178 |
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179 |
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180 | /**
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181 | * CPU context core.
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182 | *
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183 | * @todo Eliminate this structure!
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184 | * @deprecated We don't push any context cores any more in TRPM.
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185 | */
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186 | #pragma pack(1)
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187 | typedef struct CPUMCTXCORE
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188 | {
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189 | /** @name General Register.
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190 | * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
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191 | * an array starting a rax.
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192 | * @{ */
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193 | union
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194 | {
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195 | uint8_t al;
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196 | uint16_t ax;
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197 | uint32_t eax;
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198 | uint64_t rax;
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199 | } CPUM_UNION_NM(rax);
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200 | union
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201 | {
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202 | uint8_t cl;
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203 | uint16_t cx;
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204 | uint32_t ecx;
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205 | uint64_t rcx;
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206 | } CPUM_UNION_NM(rcx);
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207 | union
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208 | {
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209 | uint8_t dl;
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210 | uint16_t dx;
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211 | uint32_t edx;
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212 | uint64_t rdx;
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213 | } CPUM_UNION_NM(rdx);
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214 | union
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215 | {
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216 | uint8_t bl;
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217 | uint16_t bx;
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218 | uint32_t ebx;
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219 | uint64_t rbx;
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220 | } CPUM_UNION_NM(rbx);
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221 | union
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222 | {
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223 | uint16_t sp;
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224 | uint32_t esp;
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225 | uint64_t rsp;
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226 | } CPUM_UNION_NM(rsp);
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227 | union
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228 | {
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229 | uint16_t bp;
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230 | uint32_t ebp;
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231 | uint64_t rbp;
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232 | } CPUM_UNION_NM(rbp);
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233 | union
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234 | {
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235 | uint8_t sil;
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236 | uint16_t si;
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237 | uint32_t esi;
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238 | uint64_t rsi;
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239 | } CPUM_UNION_NM(rsi);
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240 | union
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241 | {
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242 | uint8_t dil;
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243 | uint16_t di;
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244 | uint32_t edi;
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245 | uint64_t rdi;
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246 | } CPUM_UNION_NM(rdi);
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247 | uint64_t r8;
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248 | uint64_t r9;
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249 | uint64_t r10;
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250 | uint64_t r11;
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251 | uint64_t r12;
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252 | uint64_t r13;
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253 | uint64_t r14;
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254 | uint64_t r15;
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255 | /** @} */
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256 |
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257 | /** @name Segment registers.
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258 | * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
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259 | * an array starting a es.
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260 | * @{ */
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261 | CPUMSELREG es;
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262 | CPUMSELREG cs;
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263 | CPUMSELREG ss;
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264 | CPUMSELREG ds;
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265 | CPUMSELREG fs;
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266 | CPUMSELREG gs;
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267 | /** @} */
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268 |
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269 | /** The program counter. */
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270 | union
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271 | {
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272 | uint16_t ip;
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273 | uint32_t eip;
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274 | uint64_t rip;
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275 | } CPUM_UNION_NM(rip);
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276 |
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277 | /** The flags register. */
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278 | union
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279 | {
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280 | X86EFLAGS eflags;
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281 | X86RFLAGS rflags;
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282 | } CPUM_UNION_NM(rflags);
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283 |
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284 | } CPUMCTXCORE;
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285 | #pragma pack()
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286 |
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287 |
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288 | /**
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289 | * SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
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290 | */
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291 | #pragma pack(1)
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292 | typedef struct SVMHOSTSTATE
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293 | {
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294 | uint64_t uEferMsr;
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295 | uint64_t uCr0;
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296 | uint64_t uCr4;
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297 | uint64_t uCr3;
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298 | uint64_t uRip;
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299 | uint64_t uRsp;
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300 | uint64_t uRax;
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301 | X86RFLAGS rflags;
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302 | CPUMSELREG es;
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303 | CPUMSELREG cs;
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304 | CPUMSELREG ss;
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305 | CPUMSELREG ds;
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306 | VBOXGDTR gdtr;
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307 | VBOXIDTR idtr;
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308 | uint8_t abPadding[4];
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309 | } SVMHOSTSTATE;
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310 | #pragma pack()
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311 | /** Pointer to the SVMHOSTSTATE structure. */
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312 | typedef SVMHOSTSTATE *PSVMHOSTSTATE;
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313 | /** Pointer to a const SVMHOSTSTATE structure. */
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314 | typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
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315 | #ifndef VBOX_FOR_DTRACE_LIB
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316 | AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
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317 | AssertCompileSize(SVMHOSTSTATE, 184);
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318 | #endif
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319 |
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320 |
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321 | /**
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322 | * CPU context.
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323 | */
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324 | #pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
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325 | typedef struct CPUMCTX
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326 | {
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327 | /** CPUMCTXCORE Part.
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328 | * @{ */
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329 |
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330 | /** General purpose registers. */
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331 | union /* no tag! */
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332 | {
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333 | /** The general purpose register array view, indexed by X86_GREG_XXX. */
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334 | CPUMCTXGREG aGRegs[16];
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335 |
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336 | /** 64-bit general purpose register view. */
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337 | RT_GCC_EXTENSION struct /* no tag! */
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338 | {
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339 | uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
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340 | } CPUM_STRUCT_NM(qw);
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341 | /** 64-bit general purpose register view. */
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342 | RT_GCC_EXTENSION struct /* no tag! */
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343 | {
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344 | uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
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345 | } CPUM_STRUCT_NM(qw2);
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346 | /** 32-bit general purpose register view. */
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347 | RT_GCC_EXTENSION struct /* no tag! */
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348 | {
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349 | uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
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350 | esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
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351 | r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
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352 | r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
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353 | } CPUM_STRUCT_NM(dw);
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354 | /** 16-bit general purpose register view. */
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355 | RT_GCC_EXTENSION struct /* no tag! */
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356 | {
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357 | uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
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358 | sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
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359 | r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
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360 | r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
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361 | } CPUM_STRUCT_NM(w);
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362 | RT_GCC_EXTENSION struct /* no tag! */
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363 | {
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364 | uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
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365 | spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
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366 | r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
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367 | r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
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368 | } CPUM_STRUCT_NM(b);
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369 | } CPUM_UNION_NM(g);
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370 |
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371 | /** Segment registers. */
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372 | union /* no tag! */
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373 | {
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374 | /** The segment register array view, indexed by X86_SREG_XXX. */
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375 | CPUMSELREG aSRegs[6];
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376 | /** The named segment register view. */
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377 | RT_GCC_EXTENSION struct /* no tag! */
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378 | {
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379 | CPUMSELREG es, cs, ss, ds, fs, gs;
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380 | } CPUM_STRUCT_NM(n);
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381 | } CPUM_UNION_NM(s);
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382 |
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383 | /** The program counter. */
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384 | union
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385 | {
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386 | uint16_t ip;
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387 | uint32_t eip;
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388 | uint64_t rip;
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389 | } CPUM_UNION_NM(rip);
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390 |
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391 | /** The flags register. */
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392 | union
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393 | {
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394 | X86EFLAGS eflags;
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395 | X86RFLAGS rflags;
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396 | } CPUM_UNION_NM(rflags);
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397 |
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398 | /** @} */ /*(CPUMCTXCORE)*/
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399 |
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400 |
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401 | /** @name Control registers.
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402 | * @{ */
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403 | uint64_t cr0;
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404 | uint64_t cr2;
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405 | uint64_t cr3;
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406 | uint64_t cr4;
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407 | /** @} */
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408 |
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409 | /** Debug registers.
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410 | * @remarks DR4 and DR5 should not be used since they are aliases for
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411 | * DR6 and DR7 respectively on both AMD and Intel CPUs.
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412 | * @remarks DR8-15 are currently not supported by AMD or Intel, so
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413 | * neither do we.
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414 | */
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415 | uint64_t dr[8];
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416 |
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417 | /** Padding before the structure so the 64-bit member is correctly aligned.
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418 | * @todo fix this structure! */
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419 | uint16_t gdtrPadding[3];
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420 | /** Global Descriptor Table register. */
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421 | VBOXGDTR gdtr;
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422 |
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423 | /** Padding before the structure so the 64-bit member is correctly aligned.
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424 | * @todo fix this structure! */
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425 | uint16_t idtrPadding[3];
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426 | /** Interrupt Descriptor Table register. */
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427 | VBOXIDTR idtr;
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428 |
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429 | /** The task register.
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430 | * Only the guest context uses all the members. */
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431 | CPUMSELREG ldtr;
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432 | /** The task register.
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433 | * Only the guest context uses all the members. */
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434 | CPUMSELREG tr;
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435 |
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436 | /** The sysenter msr registers.
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437 | * This member is not used by the hypervisor context. */
|
---|
438 | CPUMSYSENTER SysEnter;
|
---|
439 |
|
---|
440 | /** @name System MSRs.
|
---|
441 | * @{ */
|
---|
442 | uint64_t msrEFER;
|
---|
443 | uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
|
---|
444 | uint64_t msrPAT; /**< Page attribute table. */
|
---|
445 | uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
|
---|
446 | uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
|
---|
447 | uint64_t msrSFMASK; /**< syscall flag mask. */
|
---|
448 | uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
|
---|
449 | uint64_t uMsrPadding0; /**< no longer used (used to hold a copy of APIC base MSR). */
|
---|
450 | /** @} */
|
---|
451 |
|
---|
452 | /** The XCR0..XCR1 registers. */
|
---|
453 | uint64_t aXcr[2];
|
---|
454 | /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
|
---|
455 | * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
|
---|
456 | uint64_t fXStateMask;
|
---|
457 |
|
---|
458 | /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
|
---|
459 | R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
|
---|
460 | /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
|
---|
461 | R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
|
---|
462 | /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
|
---|
463 | RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
|
---|
464 | /** State component offsets into pXState, UINT16_MAX if not present. */
|
---|
465 | uint16_t aoffXState[64];
|
---|
466 |
|
---|
467 | /** 724 - Size padding. */
|
---|
468 | uint8_t abPadding[HC_ARCH_BITS == 64 ? 4 : 12];
|
---|
469 |
|
---|
470 | /** 728 - Hardware virtualization state. */
|
---|
471 | struct
|
---|
472 | {
|
---|
473 | union /* no tag! */
|
---|
474 | {
|
---|
475 | struct
|
---|
476 | {
|
---|
477 | /** 728 - MSR holding physical address of the Guest's Host-state. */
|
---|
478 | uint64_t uMsrHSavePa;
|
---|
479 | /** 736 - Guest physical address of the nested-guest VMCB. */
|
---|
480 | RTGCPHYS GCPhysVmcb;
|
---|
481 | /** 744 - Cache of the nested-guest VMCB - R0 ptr. */
|
---|
482 | R0PTRTYPE(PSVMVMCB) pVmcbR0;
|
---|
483 | /** 752 / 748 - Cache of the nested-guest VMCB - R3 ptr. */
|
---|
484 | R3PTRTYPE(PSVMVMCB) pVmcbR3;
|
---|
485 | #if HC_ARCH_BITS == 32
|
---|
486 | /** NA / 752 - Padding. */
|
---|
487 | uint8_t abPadding0[8];
|
---|
488 | #endif
|
---|
489 | /** 760 - Guest's host-state save area. */
|
---|
490 | SVMHOSTSTATE HostState;
|
---|
491 | /** 944 - Global interrupt flag. */
|
---|
492 | uint8_t fGif;
|
---|
493 | /** 945 - Pause filter count. */
|
---|
494 | uint16_t cPauseFilter;
|
---|
495 | /** 947 - Pause filter count. */
|
---|
496 | uint16_t cPauseFilterThreshold;
|
---|
497 | /** 949 - Whether the injected event is subject to event intercepts. */
|
---|
498 | uint8_t fInterceptEvents;
|
---|
499 | /** 950 - Padding. */
|
---|
500 | uint8_t abPadding1[2];
|
---|
501 | /** 952 - MSR permission bitmap - R0 ptr. */
|
---|
502 | R0PTRTYPE(void *) pvMsrBitmapR0;
|
---|
503 | /** 960 / 956 - MSR permission bitmap - R3 ptr. */
|
---|
504 | R3PTRTYPE(void *) pvMsrBitmapR3;
|
---|
505 | /** 968 / 960 - IO permission bitmap - R0 ptr. */
|
---|
506 | R0PTRTYPE(void *) pvIoBitmapR0;
|
---|
507 | /** 976 / 964 - IO permission bitmap - R3 ptr. */
|
---|
508 | R3PTRTYPE(void *) pvIoBitmapR3;
|
---|
509 | #if HC_ARCH_BITS == 32
|
---|
510 | /** NA / 968 - Padding. */
|
---|
511 | uint8_t abPadding2[16];
|
---|
512 | #endif
|
---|
513 | } svm;
|
---|
514 | #if 0
|
---|
515 | struct
|
---|
516 | {
|
---|
517 | } vmx;
|
---|
518 | #endif
|
---|
519 | } CPUM_UNION_NM(s);
|
---|
520 |
|
---|
521 | /** 984 - A subset of force flags that are preserved while running
|
---|
522 | * the nested-guest. */
|
---|
523 | uint32_t fLocalForcedActions;
|
---|
524 | /** 1212 - Padding. */
|
---|
525 | uint8_t abPadding1[36];
|
---|
526 | } hwvirt;
|
---|
527 | /** @} */
|
---|
528 | } CPUMCTX;
|
---|
529 | #pragma pack()
|
---|
530 |
|
---|
531 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
532 | AssertCompileSizeAlignment(CPUMCTX, 64);
|
---|
533 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0);
|
---|
534 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 8);
|
---|
535 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 16);
|
---|
536 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 24);
|
---|
537 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 32);
|
---|
538 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 40);
|
---|
539 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 48);
|
---|
540 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 56);
|
---|
541 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 64);
|
---|
542 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 72);
|
---|
543 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 80);
|
---|
544 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 88);
|
---|
545 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 96);
|
---|
546 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 104);
|
---|
547 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 112);
|
---|
548 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 120);
|
---|
549 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 128);
|
---|
550 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 152);
|
---|
551 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 176);
|
---|
552 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 200);
|
---|
553 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 224);
|
---|
554 | AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 248);
|
---|
555 | AssertCompileMemberOffset(CPUMCTX, rip, 272);
|
---|
556 | AssertCompileMemberOffset(CPUMCTX, rflags, 280);
|
---|
557 | AssertCompileMemberOffset(CPUMCTX, cr0, 288);
|
---|
558 | AssertCompileMemberOffset(CPUMCTX, cr2, 296);
|
---|
559 | AssertCompileMemberOffset(CPUMCTX, cr3, 304);
|
---|
560 | AssertCompileMemberOffset(CPUMCTX, cr4, 312);
|
---|
561 | AssertCompileMemberOffset(CPUMCTX, dr, 320);
|
---|
562 | AssertCompileMemberOffset(CPUMCTX, gdtr, 384+6);
|
---|
563 | AssertCompileMemberOffset(CPUMCTX, idtr, 400+6);
|
---|
564 | AssertCompileMemberOffset(CPUMCTX, ldtr, 416);
|
---|
565 | AssertCompileMemberOffset(CPUMCTX, tr, 440);
|
---|
566 | AssertCompileMemberOffset(CPUMCTX, SysEnter, 464);
|
---|
567 | AssertCompileMemberOffset(CPUMCTX, msrEFER, 488);
|
---|
568 | AssertCompileMemberOffset(CPUMCTX, msrSTAR, 496);
|
---|
569 | AssertCompileMemberOffset(CPUMCTX, msrPAT, 504);
|
---|
570 | AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 512);
|
---|
571 | AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 520);
|
---|
572 | AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 528);
|
---|
573 | AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 536);
|
---|
574 | AssertCompileMemberOffset(CPUMCTX, aXcr, 552);
|
---|
575 | AssertCompileMemberOffset(CPUMCTX, fXStateMask, 568);
|
---|
576 | AssertCompileMemberOffset(CPUMCTX, pXStateR0, 576);
|
---|
577 | AssertCompileMemberOffset(CPUMCTX, pXStateR3, HC_ARCH_BITS == 64 ? 584 : 580);
|
---|
578 | AssertCompileMemberOffset(CPUMCTX, pXStateRC, HC_ARCH_BITS == 64 ? 592 : 584);
|
---|
579 | AssertCompileMemberOffset(CPUMCTX, aoffXState, HC_ARCH_BITS == 64 ? 596 : 588);
|
---|
580 | AssertCompileMemberOffset(CPUMCTX, hwvirt, 728);
|
---|
581 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa, 728);
|
---|
582 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.GCPhysVmcb, 736);
|
---|
583 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0, 744);
|
---|
584 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR3, HC_ARCH_BITS == 64 ? 752 : 748);
|
---|
585 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState, 760);
|
---|
586 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fGif, 944);
|
---|
587 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilter, 945);
|
---|
588 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilterThreshold, 947);
|
---|
589 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 949);
|
---|
590 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0, 952);
|
---|
591 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR3, HC_ARCH_BITS == 64 ? 960 : 956);
|
---|
592 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0, HC_ARCH_BITS == 64 ? 968 : 960);
|
---|
593 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3, HC_ARCH_BITS == 64 ? 976 : 964);
|
---|
594 | AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) fLocalForcedActions, 984);
|
---|
595 | AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0, 8);
|
---|
596 | AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0, 8);
|
---|
597 | AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0, 8);
|
---|
598 |
|
---|
599 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
|
---|
600 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
|
---|
601 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
|
---|
602 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
|
---|
603 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
|
---|
604 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
|
---|
605 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
|
---|
606 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
|
---|
607 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
|
---|
608 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
|
---|
609 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
|
---|
610 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
|
---|
611 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
|
---|
612 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
|
---|
613 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
|
---|
614 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
|
---|
615 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
|
---|
616 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
|
---|
617 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
|
---|
618 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
|
---|
619 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
|
---|
620 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
|
---|
621 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
|
---|
622 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
|
---|
623 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
|
---|
624 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
|
---|
625 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
|
---|
626 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
|
---|
627 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
|
---|
628 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
|
---|
629 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
|
---|
630 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
|
---|
631 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
|
---|
632 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
|
---|
633 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
|
---|
634 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
|
---|
635 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
|
---|
636 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
|
---|
637 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
|
---|
638 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
|
---|
639 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
|
---|
640 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
|
---|
641 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
|
---|
642 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
|
---|
643 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
|
---|
644 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
|
---|
645 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
|
---|
646 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
|
---|
647 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
|
---|
648 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
|
---|
649 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
|
---|
650 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
|
---|
651 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
|
---|
652 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
|
---|
653 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
|
---|
654 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
|
---|
655 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
|
---|
656 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
|
---|
657 | # ifndef _MSC_VER
|
---|
658 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
|
---|
659 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
|
---|
660 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
|
---|
661 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
|
---|
662 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
|
---|
663 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
|
---|
664 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
|
---|
665 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
|
---|
666 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
|
---|
667 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
|
---|
668 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
|
---|
669 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
|
---|
670 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
|
---|
671 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
|
---|
672 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
|
---|
673 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
|
---|
674 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
|
---|
675 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
|
---|
676 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
|
---|
677 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
|
---|
678 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
|
---|
679 | AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
|
---|
680 | # endif
|
---|
681 |
|
---|
682 | /**
|
---|
683 | * Calculates the pointer to the given extended state component.
|
---|
684 | *
|
---|
685 | * @returns Pointer of type @a a_PtrType
|
---|
686 | * @param a_pCtx Pointer to the context.
|
---|
687 | * @param a_iCompBit The extended state component bit number. This bit
|
---|
688 | * must be set in CPUMCTX::fXStateMask.
|
---|
689 | * @param a_PtrType The pointer type of the extended state component.
|
---|
690 | *
|
---|
691 | */
|
---|
692 | #if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
|
---|
693 | # define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
|
---|
694 | ([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
|
---|
695 | { \
|
---|
696 | AssertCompile((a_iCompBit) < 64U); \
|
---|
697 | AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
|
---|
698 | AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
|
---|
699 | return (a_PtrType)((uint8_t *)a_pLambdaCtx->CTX_SUFF(pXState) + a_pLambdaCtx->aoffXState[(a_iCompBit)]); \
|
---|
700 | }(a_pCtx))
|
---|
701 | #elif defined(VBOX_STRICT) && defined(__GNUC__)
|
---|
702 | # define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
|
---|
703 | __extension__ (\
|
---|
704 | { \
|
---|
705 | AssertCompile((a_iCompBit) < 64U); \
|
---|
706 | AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
|
---|
707 | AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
|
---|
708 | (a_PtrType)((uint8_t *)(a_pCtx)->CTX_SUFF(pXState) + (a_pCtx)->aoffXState[(a_iCompBit)]); \
|
---|
709 | })
|
---|
710 | #else
|
---|
711 | # define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
|
---|
712 | ((a_PtrType)((uint8_t *)(a_pCtx)->CTX_SUFF(pXState) + (a_pCtx)->aoffXState[(a_iCompBit)]))
|
---|
713 | #endif
|
---|
714 |
|
---|
715 | /**
|
---|
716 | * Gets the CPUMCTXCORE part of a CPUMCTX.
|
---|
717 | */
|
---|
718 | # define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
|
---|
719 |
|
---|
720 | /**
|
---|
721 | * Gets the CPUMCTX part from a CPUMCTXCORE.
|
---|
722 | */
|
---|
723 | # define CPUMCTX_FROM_CORE(a_pCtxCore) RT_FROM_MEMBER(a_pCtxCore, CPUMCTX, rax)
|
---|
724 |
|
---|
725 | /**
|
---|
726 | * Gets the first selector register of a CPUMCTX.
|
---|
727 | *
|
---|
728 | * Use this with X86_SREG_COUNT to loop thru the selector registers.
|
---|
729 | */
|
---|
730 | # define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
|
---|
731 |
|
---|
732 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
---|
733 |
|
---|
734 | /**
|
---|
735 | * Additional guest MSRs (i.e. not part of the CPU context structure).
|
---|
736 | *
|
---|
737 | * @remarks Never change the order here because of the saved stated! The size
|
---|
738 | * can in theory be changed, but keep older VBox versions in mind.
|
---|
739 | */
|
---|
740 | typedef union CPUMCTXMSRS
|
---|
741 | {
|
---|
742 | struct
|
---|
743 | {
|
---|
744 | uint64_t TscAux; /**< MSR_K8_TSC_AUX */
|
---|
745 | uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
|
---|
746 | uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
|
---|
747 | uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
|
---|
748 | uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
|
---|
749 | uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
|
---|
750 | uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
|
---|
751 | uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
|
---|
752 | uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
|
---|
753 | uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
|
---|
754 | uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
|
---|
755 | uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
|
---|
756 | uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
|
---|
757 | uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
|
---|
758 | uint64_t PkgCStateCfgCtrl; /**< MSR_PKG_CST_CONFIG_CONTROL */
|
---|
759 | } msr;
|
---|
760 | uint64_t au64[64];
|
---|
761 | } CPUMCTXMSRS;
|
---|
762 | /** Pointer to the guest MSR state. */
|
---|
763 | typedef CPUMCTXMSRS *PCPUMCTXMSRS;
|
---|
764 | /** Pointer to the const guest MSR state. */
|
---|
765 | typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
|
---|
766 |
|
---|
767 | /**
|
---|
768 | * The register set returned by a CPUID operation.
|
---|
769 | */
|
---|
770 | typedef struct CPUMCPUID
|
---|
771 | {
|
---|
772 | uint32_t uEax;
|
---|
773 | uint32_t uEbx;
|
---|
774 | uint32_t uEcx;
|
---|
775 | uint32_t uEdx;
|
---|
776 | } CPUMCPUID;
|
---|
777 | /** Pointer to a CPUID leaf. */
|
---|
778 | typedef CPUMCPUID *PCPUMCPUID;
|
---|
779 | /** Pointer to a const CPUID leaf. */
|
---|
780 | typedef const CPUMCPUID *PCCPUMCPUID;
|
---|
781 |
|
---|
782 | /** @} */
|
---|
783 |
|
---|
784 | RT_C_DECLS_END
|
---|
785 |
|
---|
786 | #endif
|
---|
787 |
|
---|