VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 71833

Last change on this file since 71833 was 71833, checked in by vboxsync, 7 years ago

VMM: Nested hw.virt: Implement pause-filter and pause-filter threshold.
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1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_cpumctx_h
27#define ___VBox_vmm_cpumctx_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/x86.h>
31# include <VBox/types.h>
32# include <VBox/vmm/hm_svm.h>
33#else
34# pragma D depends_on library x86.d
35#endif
36
37
38RT_C_DECLS_BEGIN
39
40/** @defgroup grp_cpum_ctx The CPUM Context Structures
41 * @ingroup grp_cpum
42 * @{
43 */
44
45/**
46 * Selector hidden registers.
47 */
48typedef struct CPUMSELREG
49{
50 /** The selector register. */
51 RTSEL Sel;
52 /** Padding, don't use. */
53 RTSEL PaddingSel;
54 /** The selector which info resides in u64Base, u32Limit and Attr, provided
55 * that CPUMSELREG_FLAGS_VALID is set. */
56 RTSEL ValidSel;
57 /** Flags, see CPUMSELREG_FLAGS_XXX. */
58 uint16_t fFlags;
59
60 /** Base register.
61 *
62 * Long mode remarks:
63 * - Unused in long mode for CS, DS, ES, SS
64 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
65 * - 64 bits for TR & LDTR
66 */
67 uint64_t u64Base;
68 /** Limit (expanded). */
69 uint32_t u32Limit;
70 /** Flags.
71 * This is the high 32-bit word of the descriptor entry.
72 * Only the flags, dpl and type are used. */
73 X86DESCATTR Attr;
74} CPUMSELREG;
75#ifndef VBOX_FOR_DTRACE_LIB
76AssertCompileSize(CPUMSELREG, 24);
77#endif
78
79/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
80 * @{ */
81#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
82#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
83#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
84/** @} */
85
86/** Checks if the hidden parts of the selector register are valid. */
87#ifdef VBOX_WITH_RAW_MODE_NOT_R0
88# define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
89 ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
90 && ( (a_pSelReg)->ValidSel == (a_pSelReg)->Sel \
91 || ( (a_pVCpu) /*!= NULL*/ \
92 && (a_pSelReg)->ValidSel == ((a_pSelReg)->Sel & X86_SEL_MASK_OFF_RPL) \
93 && ((a_pSelReg)->Sel & X86_SEL_RPL) == 1 \
94 && ((a_pSelReg)->ValidSel & X86_SEL_RPL) == 0 \
95 && CPUMIsGuestInRawMode(a_pVCpu) \
96 ) \
97 ) \
98 )
99#else
100# define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
101 ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
102 && (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
103#endif
104
105/** Old type used for the hidden register part.
106 * @deprecated */
107typedef CPUMSELREG CPUMSELREGHID;
108
109/**
110 * The sysenter register set.
111 */
112typedef struct CPUMSYSENTER
113{
114 /** Ring 0 cs.
115 * This value + 8 is the Ring 0 ss.
116 * This value + 16 is the Ring 3 cs.
117 * This value + 24 is the Ring 3 ss.
118 */
119 uint64_t cs;
120 /** Ring 0 eip. */
121 uint64_t eip;
122 /** Ring 0 esp. */
123 uint64_t esp;
124} CPUMSYSENTER;
125
126/** @def CPUM_UNION_NM
127 * For compilers (like DTrace) that does not grok nameless unions, we have a
128 * little hack to make them palatable.
129 */
130/** @def CPUM_STRUCT_NM
131 * For compilers (like DTrace) that does not grok nameless structs (it is
132 * non-standard C++), we have a little hack to make them palatable.
133 */
134#ifdef VBOX_FOR_DTRACE_LIB
135# define CPUM_UNION_NM(a_Nm) a_Nm
136# define CPUM_STRUCT_NM(a_Nm) a_Nm
137#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138# define CPUM_UNION_NM(a_Nm) a_Nm
139# define CPUM_STRUCT_NM(a_Nm) a_Nm
140#else
141# define CPUM_UNION_NM(a_Nm)
142# define CPUM_STRUCT_NM(a_Nm)
143#endif
144/** @def CPUM_UNION_STRUCT_NM
145 * Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146 * the screen in the compile time assertions.
147 */
148#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150/** A general register (union). */
151typedef union CPUMCTXGREG
152{
153 /** Natural unsigned integer view. */
154 uint64_t u;
155 /** 64-bit view. */
156 uint64_t u64;
157 /** 32-bit view. */
158 uint32_t u32;
159 /** 16-bit view. */
160 uint16_t u16;
161 /** 8-bit view. */
162 uint8_t u8;
163 /** 8-bit low/high view. */
164 RT_GCC_EXTENSION struct
165 {
166 /** Low byte (al, cl, dl, bl, ++). */
167 uint8_t bLo;
168 /** High byte in the first word - ah, ch, dh, bh. */
169 uint8_t bHi;
170 } CPUM_STRUCT_NM(s);
171} CPUMCTXGREG;
172#ifndef VBOX_FOR_DTRACE_LIB
173AssertCompileSize(CPUMCTXGREG, 8);
174AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176#endif
177
178
179
180/**
181 * CPU context core.
182 *
183 * @todo Eliminate this structure!
184 * @deprecated We don't push any context cores any more in TRPM.
185 */
186#pragma pack(1)
187typedef struct CPUMCTXCORE
188{
189 /** @name General Register.
190 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
191 * an array starting a rax.
192 * @{ */
193 union
194 {
195 uint8_t al;
196 uint16_t ax;
197 uint32_t eax;
198 uint64_t rax;
199 } CPUM_UNION_NM(rax);
200 union
201 {
202 uint8_t cl;
203 uint16_t cx;
204 uint32_t ecx;
205 uint64_t rcx;
206 } CPUM_UNION_NM(rcx);
207 union
208 {
209 uint8_t dl;
210 uint16_t dx;
211 uint32_t edx;
212 uint64_t rdx;
213 } CPUM_UNION_NM(rdx);
214 union
215 {
216 uint8_t bl;
217 uint16_t bx;
218 uint32_t ebx;
219 uint64_t rbx;
220 } CPUM_UNION_NM(rbx);
221 union
222 {
223 uint16_t sp;
224 uint32_t esp;
225 uint64_t rsp;
226 } CPUM_UNION_NM(rsp);
227 union
228 {
229 uint16_t bp;
230 uint32_t ebp;
231 uint64_t rbp;
232 } CPUM_UNION_NM(rbp);
233 union
234 {
235 uint8_t sil;
236 uint16_t si;
237 uint32_t esi;
238 uint64_t rsi;
239 } CPUM_UNION_NM(rsi);
240 union
241 {
242 uint8_t dil;
243 uint16_t di;
244 uint32_t edi;
245 uint64_t rdi;
246 } CPUM_UNION_NM(rdi);
247 uint64_t r8;
248 uint64_t r9;
249 uint64_t r10;
250 uint64_t r11;
251 uint64_t r12;
252 uint64_t r13;
253 uint64_t r14;
254 uint64_t r15;
255 /** @} */
256
257 /** @name Segment registers.
258 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
259 * an array starting a es.
260 * @{ */
261 CPUMSELREG es;
262 CPUMSELREG cs;
263 CPUMSELREG ss;
264 CPUMSELREG ds;
265 CPUMSELREG fs;
266 CPUMSELREG gs;
267 /** @} */
268
269 /** The program counter. */
270 union
271 {
272 uint16_t ip;
273 uint32_t eip;
274 uint64_t rip;
275 } CPUM_UNION_NM(rip);
276
277 /** The flags register. */
278 union
279 {
280 X86EFLAGS eflags;
281 X86RFLAGS rflags;
282 } CPUM_UNION_NM(rflags);
283
284} CPUMCTXCORE;
285#pragma pack()
286
287
288/**
289 * SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
290 */
291#pragma pack(1)
292typedef struct SVMHOSTSTATE
293{
294 uint64_t uEferMsr;
295 uint64_t uCr0;
296 uint64_t uCr4;
297 uint64_t uCr3;
298 uint64_t uRip;
299 uint64_t uRsp;
300 uint64_t uRax;
301 X86RFLAGS rflags;
302 CPUMSELREG es;
303 CPUMSELREG cs;
304 CPUMSELREG ss;
305 CPUMSELREG ds;
306 VBOXGDTR gdtr;
307 VBOXIDTR idtr;
308 uint8_t abPadding[4];
309} SVMHOSTSTATE;
310#pragma pack()
311/** Pointer to the SVMHOSTSTATE structure. */
312typedef SVMHOSTSTATE *PSVMHOSTSTATE;
313/** Pointer to a const SVMHOSTSTATE structure. */
314typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
315#ifndef VBOX_FOR_DTRACE_LIB
316AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
317AssertCompileSize(SVMHOSTSTATE, 184);
318#endif
319
320
321/**
322 * CPU context.
323 */
324#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
325typedef struct CPUMCTX
326{
327 /** CPUMCTXCORE Part.
328 * @{ */
329
330 /** General purpose registers. */
331 union /* no tag! */
332 {
333 /** The general purpose register array view, indexed by X86_GREG_XXX. */
334 CPUMCTXGREG aGRegs[16];
335
336 /** 64-bit general purpose register view. */
337 RT_GCC_EXTENSION struct /* no tag! */
338 {
339 uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
340 } CPUM_STRUCT_NM(qw);
341 /** 64-bit general purpose register view. */
342 RT_GCC_EXTENSION struct /* no tag! */
343 {
344 uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
345 } CPUM_STRUCT_NM(qw2);
346 /** 32-bit general purpose register view. */
347 RT_GCC_EXTENSION struct /* no tag! */
348 {
349 uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
350 esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
351 r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
352 r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
353 } CPUM_STRUCT_NM(dw);
354 /** 16-bit general purpose register view. */
355 RT_GCC_EXTENSION struct /* no tag! */
356 {
357 uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
358 sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
359 r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
360 r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
361 } CPUM_STRUCT_NM(w);
362 RT_GCC_EXTENSION struct /* no tag! */
363 {
364 uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
365 spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
366 r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
367 r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
368 } CPUM_STRUCT_NM(b);
369 } CPUM_UNION_NM(g);
370
371 /** Segment registers. */
372 union /* no tag! */
373 {
374 /** The segment register array view, indexed by X86_SREG_XXX. */
375 CPUMSELREG aSRegs[6];
376 /** The named segment register view. */
377 RT_GCC_EXTENSION struct /* no tag! */
378 {
379 CPUMSELREG es, cs, ss, ds, fs, gs;
380 } CPUM_STRUCT_NM(n);
381 } CPUM_UNION_NM(s);
382
383 /** The program counter. */
384 union
385 {
386 uint16_t ip;
387 uint32_t eip;
388 uint64_t rip;
389 } CPUM_UNION_NM(rip);
390
391 /** The flags register. */
392 union
393 {
394 X86EFLAGS eflags;
395 X86RFLAGS rflags;
396 } CPUM_UNION_NM(rflags);
397
398 /** @} */ /*(CPUMCTXCORE)*/
399
400
401 /** @name Control registers.
402 * @{ */
403 uint64_t cr0;
404 uint64_t cr2;
405 uint64_t cr3;
406 uint64_t cr4;
407 /** @} */
408
409 /** Debug registers.
410 * @remarks DR4 and DR5 should not be used since they are aliases for
411 * DR6 and DR7 respectively on both AMD and Intel CPUs.
412 * @remarks DR8-15 are currently not supported by AMD or Intel, so
413 * neither do we.
414 */
415 uint64_t dr[8];
416
417 /** Padding before the structure so the 64-bit member is correctly aligned.
418 * @todo fix this structure! */
419 uint16_t gdtrPadding[3];
420 /** Global Descriptor Table register. */
421 VBOXGDTR gdtr;
422
423 /** Padding before the structure so the 64-bit member is correctly aligned.
424 * @todo fix this structure! */
425 uint16_t idtrPadding[3];
426 /** Interrupt Descriptor Table register. */
427 VBOXIDTR idtr;
428
429 /** The task register.
430 * Only the guest context uses all the members. */
431 CPUMSELREG ldtr;
432 /** The task register.
433 * Only the guest context uses all the members. */
434 CPUMSELREG tr;
435
436 /** The sysenter msr registers.
437 * This member is not used by the hypervisor context. */
438 CPUMSYSENTER SysEnter;
439
440 /** @name System MSRs.
441 * @{ */
442 uint64_t msrEFER;
443 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
444 uint64_t msrPAT; /**< Page attribute table. */
445 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
446 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
447 uint64_t msrSFMASK; /**< syscall flag mask. */
448 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
449 uint64_t uMsrPadding0; /**< no longer used (used to hold a copy of APIC base MSR). */
450 /** @} */
451
452 /** The XCR0..XCR1 registers. */
453 uint64_t aXcr[2];
454 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
455 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
456 uint64_t fXStateMask;
457
458 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
459 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
460#if HC_ARCH_BITS == 32
461 uint32_t uXStateR0Padding;
462#endif
463 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
464 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
465#if HC_ARCH_BITS == 32
466 uint32_t uXStateR3Padding;
467#endif
468 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
469 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
470 /** State component offsets into pXState, UINT16_MAX if not present. */
471 uint16_t aoffXState[64];
472
473 /** 0x2d4 - World switcher flags, CPUMCTX_WSF_XXX. */
474 uint32_t fWorldSwitcher;
475 /** 0x2d8 - Externalized state tracker, CPUMCTX_EXTRN_XXX.
476 * Currently only used internally in NEM/win. */
477 uint64_t fExtrn;
478
479 /** 0x2e0 - Hardware virtualization state. */
480 struct
481 {
482 union /* no tag! */
483 {
484 struct
485 {
486 /** 0x2e0 - MSR holding physical address of the Guest's Host-state. */
487 uint64_t uMsrHSavePa;
488 /** 0x2e8 - Guest physical address of the nested-guest VMCB. */
489 RTGCPHYS GCPhysVmcb;
490 /** 0x2f0 - Cache of the nested-guest VMCB - R0 ptr. */
491 R0PTRTYPE(PSVMVMCB) pVmcbR0;
492#if HC_ARCH_BITS == 32
493 uint32_t uVmcbR0Padding;
494#endif
495 /** 0x2f8 - Cache of the nested-guest VMCB - R3 ptr. */
496 R3PTRTYPE(PSVMVMCB) pVmcbR3;
497#if HC_ARCH_BITS == 32
498 uint32_t uVmcbR3Padding;
499#endif
500 /** 0x300 - Guest's host-state save area. */
501 SVMHOSTSTATE HostState;
502 /** 0x3b8 - Guest TSC time-stamp of when the previous PAUSE instr. was executed. */
503 uint64_t uPrevPauseTick;
504 /** 0x3c0 - Pause filter count. */
505 uint16_t cPauseFilter;
506 /** 0x3c2 - Pause filter threshold. */
507 uint16_t cPauseFilterThreshold;
508 /** 0x3c4 - Whether the injected event is subject to event intercepts. */
509 bool fInterceptEvents;
510 /** 0x3c5 - Whether parts of the VMCB are cached (and potentially modified) by HM. */
511 bool fHMCachedVmcb;
512 /** 0x3c6 - Padding. */
513 bool afPadding[2];
514 /** 0x3c8 - MSR permission bitmap - R0 ptr. */
515 R0PTRTYPE(void *) pvMsrBitmapR0;
516#if HC_ARCH_BITS == 32
517 uint32_t uvMsrBitmapR0Padding;
518#endif
519 /** 0x3d0 - MSR permission bitmap - R3 ptr. */
520 R3PTRTYPE(void *) pvMsrBitmapR3;
521#if HC_ARCH_BITS == 32
522 uint32_t uvMsrBitmapR3Padding;
523#endif
524 /** 0x3d8 - IO permission bitmap - R0 ptr. */
525 R0PTRTYPE(void *) pvIoBitmapR0;
526#if HC_ARCH_BITS == 32
527 uint32_t uIoBitmapR0Padding;
528#endif
529 /** 0x3e0 - IO permission bitmap - R3 ptr. */
530 R3PTRTYPE(void *) pvIoBitmapR3;
531#if HC_ARCH_BITS == 32
532 uint32_t uIoBitmapR3Padding;
533#endif
534 /** 0x3e8 - Host physical address of the nested-guest VMCB. */
535 RTHCPHYS HCPhysVmcb;
536 } svm;
537#if 0
538 struct
539 {
540 } vmx;
541#endif
542 } CPUM_UNION_NM(s);
543
544 /** 0x3f0 - A subset of force flags that are preserved while running the nested-guest. */
545 uint32_t fLocalForcedActions;
546 /** 0x3f4 - Global interrupt flag (always true on nested VMX). */
547 bool fGif;
548 /** 0x3f5 - Padding. */
549 uint8_t abPadding1[11];
550 } hwvirt;
551 /** @} */
552} CPUMCTX;
553#pragma pack()
554
555#ifndef VBOX_FOR_DTRACE_LIB
556AssertCompileSizeAlignment(CPUMCTX, 64);
557AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0);
558AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 8);
559AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 16);
560AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 24);
561AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 32);
562AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 40);
563AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 48);
564AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 56);
565AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 64);
566AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 72);
567AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 80);
568AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 88);
569AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 96);
570AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 104);
571AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 112);
572AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 120);
573AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 128);
574AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 152);
575AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 176);
576AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 200);
577AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 224);
578AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 248);
579AssertCompileMemberOffset(CPUMCTX, rip, 272);
580AssertCompileMemberOffset(CPUMCTX, rflags, 280);
581AssertCompileMemberOffset(CPUMCTX, cr0, 288);
582AssertCompileMemberOffset(CPUMCTX, cr2, 296);
583AssertCompileMemberOffset(CPUMCTX, cr3, 304);
584AssertCompileMemberOffset(CPUMCTX, cr4, 312);
585AssertCompileMemberOffset(CPUMCTX, dr, 320);
586AssertCompileMemberOffset(CPUMCTX, gdtr, 384+6);
587AssertCompileMemberOffset(CPUMCTX, idtr, 400+6);
588AssertCompileMemberOffset(CPUMCTX, ldtr, 416);
589AssertCompileMemberOffset(CPUMCTX, tr, 440);
590AssertCompileMemberOffset(CPUMCTX, SysEnter, 464);
591AssertCompileMemberOffset(CPUMCTX, msrEFER, 488);
592AssertCompileMemberOffset(CPUMCTX, msrSTAR, 496);
593AssertCompileMemberOffset(CPUMCTX, msrPAT, 504);
594AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 512);
595AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 520);
596AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 528);
597AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 536);
598AssertCompileMemberOffset(CPUMCTX, aXcr, 552);
599AssertCompileMemberOffset(CPUMCTX, fXStateMask, 568);
600AssertCompileMemberOffset(CPUMCTX, pXStateR0, 576);
601AssertCompileMemberOffset(CPUMCTX, pXStateR3, 584);
602AssertCompileMemberOffset(CPUMCTX, pXStateRC, 592);
603AssertCompileMemberOffset(CPUMCTX, aoffXState, 596);
604AssertCompileMemberOffset(CPUMCTX, hwvirt, 0x2e0);
605AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa, 0x2e0);
606AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0, 0x2f0);
607AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR3, 0x2f8);
608AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState, 0x300);
609AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilter, 0x3c0);
610AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0, 0x3c8);
611AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3, 0x3e0);
612AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HCPhysVmcb, 0x3e8);
613AssertCompileMemberOffset(CPUMCTX, hwvirt.fLocalForcedActions, 0x3f0);
614AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0, 8);
615AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0, 8);
616AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0, 8);
617
618AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
619AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
620AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
621AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
622AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
623AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
624AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
625AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
626AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
627AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
628AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
629AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
630AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
631AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
632AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
633AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
634AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
635AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
636AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
637AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
638AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
639AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
640AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
641AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
642AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
643AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
644AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
645AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
646AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
647AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
648AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
649AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
650AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
651AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
652AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
653AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
654AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
655AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
656AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
657AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
658AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
659AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
660AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
661AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
662AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
663AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
664AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
665AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
666AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
667AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
668AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
669AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
670AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
671AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
672AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
673AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
674AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
675AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
676# ifndef _MSC_VER
677AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
678AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
679AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
680AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
681AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
682AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
683AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
684AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
685AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
686AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
687AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
688AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
689AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
690AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
691AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
692AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
693AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
694AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
695AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
696AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
697AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
698AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
699# endif
700
701/**
702 * Calculates the pointer to the given extended state component.
703 *
704 * @returns Pointer of type @a a_PtrType
705 * @param a_pCtx Pointer to the context.
706 * @param a_iCompBit The extended state component bit number. This bit
707 * must be set in CPUMCTX::fXStateMask.
708 * @param a_PtrType The pointer type of the extended state component.
709 *
710 */
711#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
712# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
713 ([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
714 { \
715 AssertCompile((a_iCompBit) < 64U); \
716 AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
717 AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
718 return (a_PtrType)((uint8_t *)a_pLambdaCtx->CTX_SUFF(pXState) + a_pLambdaCtx->aoffXState[(a_iCompBit)]); \
719 }(a_pCtx))
720#elif defined(VBOX_STRICT) && defined(__GNUC__)
721# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
722 __extension__ (\
723 { \
724 AssertCompile((a_iCompBit) < 64U); \
725 AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
726 AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
727 (a_PtrType)((uint8_t *)(a_pCtx)->CTX_SUFF(pXState) + (a_pCtx)->aoffXState[(a_iCompBit)]); \
728 })
729#else
730# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
731 ((a_PtrType)((uint8_t *)(a_pCtx)->CTX_SUFF(pXState) + (a_pCtx)->aoffXState[(a_iCompBit)]))
732#endif
733
734/**
735 * Gets the CPUMCTXCORE part of a CPUMCTX.
736 */
737# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
738
739/**
740 * Gets the CPUMCTX part from a CPUMCTXCORE.
741 */
742# define CPUMCTX_FROM_CORE(a_pCtxCore) RT_FROM_MEMBER(a_pCtxCore, CPUMCTX, rax)
743
744/**
745 * Gets the first selector register of a CPUMCTX.
746 *
747 * Use this with X86_SREG_COUNT to loop thru the selector registers.
748 */
749# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
750
751#endif /* !VBOX_FOR_DTRACE_LIB */
752
753
754/** @name CPUMCTX_WSF_XXX
755 * @{ */
756/** Touch IA32_PRED_CMD.IBPB on VM exit. */
757#define CPUMCTX_WSF_IBPB_EXIT RT_BIT_32(0)
758/** Touch IA32_PRED_CMD.IBPB on VM entry. */
759#define CPUMCTX_WSF_IBPB_ENTRY RT_BIT_32(1)
760/** @} */
761
762/** @name CPUMCTX_EXTRN_XXX
763 * Used to parts of the CPUM state that is externalized and needs fetching
764 * before use.
765 *
766 * @{ */
767/** External state keeper: Invalid. */
768#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
769/** External state keeper: HM. */
770#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
771/** External state keeper: NEM. */
772#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
773/** External state keeper: REM. */
774#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
775/** External state keeper mask. */
776#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
777
778/** The RIP register value is kept externally. */
779#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
780/** The CS register values are kept externally. */
781#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000000008)
782/** The RFLAGS register values are kept externally. */
783#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000010)
784
785/** The RAX register value is kept externally. */
786#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000020)
787/** The RCX register value is kept externally. */
788#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000040)
789/** The RDX register value is kept externally. */
790#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000080)
791/** The RBX register value is kept externally. */
792#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000100)
793/** The RSP register value is kept externally. */
794#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000200)
795/** The RBP register value is kept externally. */
796#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000400)
797/** The RSI register value is kept externally. */
798#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000800)
799/** The RDI register value is kept externally. */
800#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000001000)
801/** The R8 thru R15 register values are kept externally. */
802#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000002000)
803/** General purpose registers mask. */
804#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000003fe0)
805
806/** The SS register values are kept externally. */
807#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000004000)
808/** The DS register values are kept externally. */
809#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000008000)
810/** The ES register values are kept externally. */
811#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000010000)
812/** The FS register values are kept externally. */
813#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
814/** The GS register values are kept externally. */
815#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
816/** Segment registers (includes CS). */
817#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007c008)
818
819/** The GDTR register values are kept externally. */
820#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
821/** The IDTR register values are kept externally. */
822#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
823/** The LDTR register values are kept externally. */
824#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
825/** The TR register values are kept externally. */
826#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
827/** Table register mask. */
828#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
829
830/** The CR0 register value is kept externally. */
831#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
832/** The CR2 register value is kept externally. */
833#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
834/** The CR3 register value is kept externally. */
835#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
836/** The CR4 register value is kept externally. */
837#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
838/** Control register mask. */
839#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
840/** The EFER register value is kept externally. */
841#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000008000000)
842
843/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
844#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000010000000)
845/** The DR6 register value is kept externally. */
846#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000020000000)
847/** The DR7 register value is kept externally. */
848#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000040000000)
849/** Debug register mask. */
850#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x0000000070000000)
851
852/** The XSAVE_C_X87 state is kept externally. */
853#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000080000000)
854/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
855 * XSAVE_C_OPMASK state is kept externally. */
856#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000100000000)
857/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
858 * CPUMCTX_EXTRN_SEE_AVX is kept externally. */
859#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000200000000)
860/** The state of XCR0 and XCR1 register values are kept externally. */
861#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000400000000)
862
863/** The KERNEL GS BASE MSR value is kept externally. */
864#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000000800000000)
865/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
866#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000001000000000)
867/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
868#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000002000000000)
869/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
870#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000004000000000)
871/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
872 * CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
873 * CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
874#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000008000000000)
875
876/** Mask of bits the keepers can use for state tracking. */
877#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
878
879/** NEM/Win: Event injection (known was interruption) pending state. */
880#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
881/** NEM/Win: Mask. */
882#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
883
884/** All CPUM state bits, not including keeper specific ones. */
885#define CPUMCTX_EXTRN_ALL UINT64_C(0x000000fffffffffc)
886/** @} */
887
888
889/**
890 * Additional guest MSRs (i.e. not part of the CPU context structure).
891 *
892 * @remarks Never change the order here because of the saved stated! The size
893 * can in theory be changed, but keep older VBox versions in mind.
894 */
895typedef union CPUMCTXMSRS
896{
897 struct
898 {
899 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
900 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
901 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
902 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
903 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
904 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
905 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
906 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
907 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
908 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
909 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
910 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
911 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
912 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
913 uint64_t PkgCStateCfgCtrl; /**< MSR_PKG_CST_CONFIG_CONTROL */
914 uint64_t SpecCtrl; /**< IA32_SPEC_CTRL */
915 uint64_t ArchCaps; /**< IA32_ARCH_CAPABILITIES */
916 } msr;
917 uint64_t au64[64];
918} CPUMCTXMSRS;
919/** Pointer to the guest MSR state. */
920typedef CPUMCTXMSRS *PCPUMCTXMSRS;
921/** Pointer to the const guest MSR state. */
922typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
923
924/**
925 * The register set returned by a CPUID operation.
926 */
927typedef struct CPUMCPUID
928{
929 uint32_t uEax;
930 uint32_t uEbx;
931 uint32_t uEcx;
932 uint32_t uEdx;
933} CPUMCPUID;
934/** Pointer to a CPUID leaf. */
935typedef CPUMCPUID *PCPUMCPUID;
936/** Pointer to a const CPUID leaf. */
937typedef const CPUMCPUID *PCCPUMCPUID;
938
939/** @} */
940
941RT_C_DECLS_END
942
943#endif
944
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