VirtualBox

source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 92070

Last change on this file since 92070 was 91308, checked in by vboxsync, 3 years ago

VMM/CPUM: Comments/todos for some big CPUMCTX members. bugref:10093
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1/** @file
2 * CPUM - CPU Monitor(/ Manager), Context Structures.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_cpumctx_h
27#define VBOX_INCLUDED_vmm_cpumctx_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#ifndef VBOX_FOR_DTRACE_LIB
33# include <iprt/x86.h>
34# include <VBox/types.h>
35# include <VBox/vmm/hm_svm.h>
36# include <VBox/vmm/hm_vmx.h>
37#else
38# pragma D depends_on library x86.d
39#endif
40
41
42RT_C_DECLS_BEGIN
43
44/** @defgroup grp_cpum_ctx The CPUM Context Structures
45 * @ingroup grp_cpum
46 * @{
47 */
48
49/**
50 * Selector hidden registers.
51 */
52typedef struct CPUMSELREG
53{
54 /** The selector register. */
55 RTSEL Sel;
56 /** Padding, don't use. */
57 RTSEL PaddingSel;
58 /** The selector which info resides in u64Base, u32Limit and Attr, provided
59 * that CPUMSELREG_FLAGS_VALID is set. */
60 RTSEL ValidSel;
61 /** Flags, see CPUMSELREG_FLAGS_XXX. */
62 uint16_t fFlags;
63
64 /** Base register.
65 *
66 * Long mode remarks:
67 * - Unused in long mode for CS, DS, ES, SS
68 * - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
69 * - 64 bits for TR & LDTR
70 */
71 uint64_t u64Base;
72 /** Limit (expanded). */
73 uint32_t u32Limit;
74 /** Flags.
75 * This is the high 32-bit word of the descriptor entry.
76 * Only the flags, dpl and type are used. */
77 X86DESCATTR Attr;
78} CPUMSELREG;
79#ifndef VBOX_FOR_DTRACE_LIB
80AssertCompileSize(CPUMSELREG, 24);
81#endif
82
83/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
84 * @{ */
85#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
86#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
87#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
88/** @} */
89
90/** Checks if the hidden parts of the selector register are valid. */
91#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
92 ( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
93 && (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
94
95/** Old type used for the hidden register part.
96 * @deprecated */
97typedef CPUMSELREG CPUMSELREGHID;
98
99/**
100 * The sysenter register set.
101 */
102typedef struct CPUMSYSENTER
103{
104 /** Ring 0 cs.
105 * This value + 8 is the Ring 0 ss.
106 * This value + 16 is the Ring 3 cs.
107 * This value + 24 is the Ring 3 ss.
108 */
109 uint64_t cs;
110 /** Ring 0 eip. */
111 uint64_t eip;
112 /** Ring 0 esp. */
113 uint64_t esp;
114} CPUMSYSENTER;
115
116/** @def CPUM_UNION_NM
117 * For compilers (like DTrace) that does not grok nameless unions, we have a
118 * little hack to make them palatable.
119 */
120/** @def CPUM_STRUCT_NM
121 * For compilers (like DTrace) that does not grok nameless structs (it is
122 * non-standard C++), we have a little hack to make them palatable.
123 */
124#ifdef VBOX_FOR_DTRACE_LIB
125# define CPUM_UNION_NM(a_Nm) a_Nm
126# define CPUM_STRUCT_NM(a_Nm) a_Nm
127#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
128# define CPUM_UNION_NM(a_Nm) a_Nm
129# define CPUM_STRUCT_NM(a_Nm) a_Nm
130#else
131# define CPUM_UNION_NM(a_Nm)
132# define CPUM_STRUCT_NM(a_Nm)
133#endif
134/** @def CPUM_UNION_STRUCT_NM
135 * Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
136 * the screen in the compile time assertions.
137 */
138#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
139
140/** A general register (union). */
141typedef union CPUMCTXGREG
142{
143 /** Natural unsigned integer view. */
144 uint64_t u;
145 /** 64-bit view. */
146 uint64_t u64;
147 /** 32-bit view. */
148 uint32_t u32;
149 /** 16-bit view. */
150 uint16_t u16;
151 /** 8-bit view. */
152 uint8_t u8;
153 /** 8-bit low/high view. */
154 RT_GCC_EXTENSION struct
155 {
156 /** Low byte (al, cl, dl, bl, ++). */
157 uint8_t bLo;
158 /** High byte in the first word - ah, ch, dh, bh. */
159 uint8_t bHi;
160 } CPUM_STRUCT_NM(s);
161} CPUMCTXGREG;
162#ifndef VBOX_FOR_DTRACE_LIB
163AssertCompileSize(CPUMCTXGREG, 8);
164AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
165AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
166#endif
167
168
169
170/**
171 * CPU context core.
172 *
173 * @todo Eliminate this structure!
174 * @deprecated We don't push any context cores any more in TRPM.
175 */
176#pragma pack(1)
177typedef struct CPUMCTXCORE
178{
179 /** @name General Register.
180 * @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
181 * an array starting a rax.
182 * @{ */
183 union
184 {
185 uint8_t al;
186 uint16_t ax;
187 uint32_t eax;
188 uint64_t rax;
189 } CPUM_UNION_NM(rax);
190 union
191 {
192 uint8_t cl;
193 uint16_t cx;
194 uint32_t ecx;
195 uint64_t rcx;
196 } CPUM_UNION_NM(rcx);
197 union
198 {
199 uint8_t dl;
200 uint16_t dx;
201 uint32_t edx;
202 uint64_t rdx;
203 } CPUM_UNION_NM(rdx);
204 union
205 {
206 uint8_t bl;
207 uint16_t bx;
208 uint32_t ebx;
209 uint64_t rbx;
210 } CPUM_UNION_NM(rbx);
211 union
212 {
213 uint16_t sp;
214 uint32_t esp;
215 uint64_t rsp;
216 } CPUM_UNION_NM(rsp);
217 union
218 {
219 uint16_t bp;
220 uint32_t ebp;
221 uint64_t rbp;
222 } CPUM_UNION_NM(rbp);
223 union
224 {
225 uint8_t sil;
226 uint16_t si;
227 uint32_t esi;
228 uint64_t rsi;
229 } CPUM_UNION_NM(rsi);
230 union
231 {
232 uint8_t dil;
233 uint16_t di;
234 uint32_t edi;
235 uint64_t rdi;
236 } CPUM_UNION_NM(rdi);
237 uint64_t r8;
238 uint64_t r9;
239 uint64_t r10;
240 uint64_t r11;
241 uint64_t r12;
242 uint64_t r13;
243 uint64_t r14;
244 uint64_t r15;
245 /** @} */
246
247 /** @name Segment registers.
248 * @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
249 * an array starting a es.
250 * @{ */
251 CPUMSELREG es;
252 CPUMSELREG cs;
253 CPUMSELREG ss;
254 CPUMSELREG ds;
255 CPUMSELREG fs;
256 CPUMSELREG gs;
257 /** @} */
258
259 /** The program counter. */
260 union
261 {
262 uint16_t ip;
263 uint32_t eip;
264 uint64_t rip;
265 } CPUM_UNION_NM(rip);
266
267 /** The flags register. */
268 union
269 {
270 X86EFLAGS eflags;
271 X86RFLAGS rflags;
272 } CPUM_UNION_NM(rflags);
273
274} CPUMCTXCORE;
275#pragma pack()
276
277
278/**
279 * SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
280 *
281 * @warning Exercise caution while modifying the layout of this struct. It's
282 * part of VM saved states.
283 */
284#pragma pack(1)
285typedef struct SVMHOSTSTATE
286{
287 uint64_t uEferMsr;
288 uint64_t uCr0;
289 uint64_t uCr4;
290 uint64_t uCr3;
291 uint64_t uRip;
292 uint64_t uRsp;
293 uint64_t uRax;
294 X86RFLAGS rflags;
295 CPUMSELREG es;
296 CPUMSELREG cs;
297 CPUMSELREG ss;
298 CPUMSELREG ds;
299 VBOXGDTR gdtr;
300 VBOXIDTR idtr;
301 uint8_t abPadding[4];
302} SVMHOSTSTATE;
303#pragma pack()
304/** Pointer to the SVMHOSTSTATE structure. */
305typedef SVMHOSTSTATE *PSVMHOSTSTATE;
306/** Pointer to a const SVMHOSTSTATE structure. */
307typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
308#ifndef VBOX_FOR_DTRACE_LIB
309AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
310AssertCompileSize(SVMHOSTSTATE, 184);
311#endif
312
313
314/**
315 * CPU hardware virtualization types.
316 */
317typedef enum
318{
319 CPUMHWVIRT_NONE = 0,
320 CPUMHWVIRT_VMX,
321 CPUMHWVIRT_SVM,
322 CPUMHWVIRT_32BIT_HACK = 0x7fffffff
323} CPUMHWVIRT;
324#ifndef VBOX_FOR_DTRACE_LIB
325AssertCompileSize(CPUMHWVIRT, 4);
326#endif
327
328
329/**
330 * CPU context.
331 */
332#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
333typedef struct CPUMCTX
334{
335 /** CPUMCTXCORE Part.
336 * @{ */
337
338 /** General purpose registers. */
339 union /* no tag! */
340 {
341 /** The general purpose register array view, indexed by X86_GREG_XXX. */
342 CPUMCTXGREG aGRegs[16];
343
344 /** 64-bit general purpose register view. */
345 RT_GCC_EXTENSION struct /* no tag! */
346 {
347 uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
348 } CPUM_STRUCT_NM(qw);
349 /** 64-bit general purpose register view. */
350 RT_GCC_EXTENSION struct /* no tag! */
351 {
352 uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
353 } CPUM_STRUCT_NM(qw2);
354 /** 32-bit general purpose register view. */
355 RT_GCC_EXTENSION struct /* no tag! */
356 {
357 uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
358 esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
359 r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
360 r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
361 } CPUM_STRUCT_NM(dw);
362 /** 16-bit general purpose register view. */
363 RT_GCC_EXTENSION struct /* no tag! */
364 {
365 uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
366 sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
367 r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
368 r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
369 } CPUM_STRUCT_NM(w);
370 RT_GCC_EXTENSION struct /* no tag! */
371 {
372 uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
373 spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
374 r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
375 r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
376 } CPUM_STRUCT_NM(b);
377 } CPUM_UNION_NM(g);
378
379 /** Segment registers. */
380 union /* no tag! */
381 {
382 /** The segment register array view, indexed by X86_SREG_XXX. */
383 CPUMSELREG aSRegs[6];
384 /** The named segment register view. */
385 RT_GCC_EXTENSION struct /* no tag! */
386 {
387 CPUMSELREG es, cs, ss, ds, fs, gs;
388 } CPUM_STRUCT_NM(n);
389 } CPUM_UNION_NM(s);
390
391 /** The program counter. */
392 union
393 {
394 uint16_t ip;
395 uint32_t eip;
396 uint64_t rip;
397 } CPUM_UNION_NM(rip);
398
399 /** The flags register. */
400 union
401 {
402 X86EFLAGS eflags;
403 X86RFLAGS rflags;
404 } CPUM_UNION_NM(rflags);
405
406 /** @} */ /*(CPUMCTXCORE)*/
407
408
409 /** @name Control registers.
410 * @{ */
411 uint64_t cr0;
412 uint64_t cr2;
413 uint64_t cr3;
414 /** @todo the 4 PAE PDPE registers. See PGMCPU::aGstPaePdpeRegs. */
415 uint64_t cr4;
416 /** @} */
417
418 /** Debug registers.
419 * @remarks DR4 and DR5 should not be used since they are aliases for
420 * DR6 and DR7 respectively on both AMD and Intel CPUs.
421 * @remarks DR8-15 are currently not supported by AMD or Intel, so
422 * neither do we.
423 */
424 uint64_t dr[8];
425
426 /** Padding before the structure so the 64-bit member is correctly aligned.
427 * @todo fix this structure! */
428 uint16_t gdtrPadding[3];
429 /** Global Descriptor Table register. */
430 VBOXGDTR gdtr;
431
432 /** Padding before the structure so the 64-bit member is correctly aligned.
433 * @todo fix this structure! */
434 uint16_t idtrPadding[3];
435 /** Interrupt Descriptor Table register. */
436 VBOXIDTR idtr;
437
438 /** The task register.
439 * Only the guest context uses all the members. */
440 CPUMSELREG ldtr;
441 /** The task register.
442 * Only the guest context uses all the members. */
443 CPUMSELREG tr;
444
445 /** The sysenter msr registers.
446 * This member is not used by the hypervisor context. */
447 CPUMSYSENTER SysEnter;
448
449 /** @name System MSRs.
450 * @{ */
451 uint64_t msrEFER;
452 uint64_t msrSTAR; /**< Legacy syscall eip, cs & ss. */
453 uint64_t msrPAT; /**< Page attribute table. */
454 uint64_t msrLSTAR; /**< 64 bits mode syscall rip. */
455 uint64_t msrCSTAR; /**< Compatibility mode syscall rip. */
456 uint64_t msrSFMASK; /**< syscall flag mask. */
457 uint64_t msrKERNELGSBASE; /**< swapgs exchange value. */
458 uint64_t uMsrPadding0; /**< no longer used (used to hold a copy of APIC base MSR). */
459 /** @} */
460
461 /** 0x228 - Externalized state tracker, CPUMCTX_EXTRN_XXX.
462 * Currently only used internally in NEM/win. */
463 uint64_t fExtrn;
464
465 uint64_t au64Unused[2];
466
467 /** 0x240 - PAE PDPTEs. */
468 X86PDPE aPaePdpes[4];
469
470 /** 0x260 - The XCR0..XCR1 registers. */
471 uint64_t aXcr[2];
472 /** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
473 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
474 uint64_t fXStateMask;
475 /** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
476 bool fUsedFpuGuest;
477 uint8_t afUnused[7];
478
479 /* ---- Start of members not zeroed at reset. ---- */
480
481 /** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
482 * @note Everything before this member will be memset to zero during reset. */
483 uint16_t aoffXState[64];
484 /** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
485 * Aligned on 256 byte boundrary (min req is currently 64 bytes). */
486 union /* no tag */
487 {
488 X86XSAVEAREA XState;
489 /** Byte view for simple indexing and space allocation. */
490 uint8_t abXState[0x4000 - 0x300];
491 } CPUM_UNION_NM(u);
492
493 /** 0x4000 - Hardware virtualization state.
494 * @note This is page aligned, so an full page member comes first in the
495 * substructures. */
496 struct
497 {
498 union /* no tag! */
499 {
500 struct
501 {
502 /** 0x4000 - Cache of the nested-guest VMCB. */
503 SVMVMCB Vmcb;
504 /** 0x5000 - The MSRPM (MSR Permission bitmap).
505 *
506 * This need not be physically contiguous pages because we use the one from
507 * HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
508 * This one is just used for caching the bitmap from guest physical memory.
509 *
510 * @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
511 * really need to even be page aligned.
512 *
513 * Also, couldn't we just access the guest page directly when we need to,
514 * or do we have to use a cached copy of it? */
515 uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
516 /** 0x7000 - The IOPM (IO Permission bitmap).
517 *
518 * This need not be physically contiguous pages because we re-use the ring-0
519 * allocated IOPM while executing the nested-guest using hardware-assisted SVM
520 * because it's identical (we trap all IO accesses).
521 *
522 * This one is just used for caching the IOPM from guest physical memory in
523 * case the guest hypervisor allows direct access to some IO ports.
524 *
525 * @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
526 * really need to even be page aligned.
527 *
528 * Also, couldn't we just access the guest page directly when we need to,
529 * or do we have to use a cached copy of it? */
530 uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
531
532 /** 0xa000 - MSR holding physical address of the Guest's Host-state. */
533 uint64_t uMsrHSavePa;
534 /** 0xa008 - Guest physical address of the nested-guest VMCB. */
535 RTGCPHYS GCPhysVmcb;
536 /** 0xa010 - Guest's host-state save area. */
537 SVMHOSTSTATE HostState;
538 /** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
539 * executed. */
540 uint64_t uPrevPauseTick;
541 /** 0xa0d0 - Pause filter count. */
542 uint16_t cPauseFilter;
543 /** 0xa0d2 - Pause filter threshold. */
544 uint16_t cPauseFilterThreshold;
545 /** 0xa0d4 - Whether the injected event is subject to event intercepts. */
546 bool fInterceptEvents;
547 /** 0xa0d5 - Padding. */
548 bool afPadding[3];
549 } svm;
550
551 struct
552 {
553 /** 0x4000 - The current VMCS. */
554 VMXVVMCS Vmcs;
555 /** 0X5000 - The shadow VMCS. */
556 VMXVVMCS ShadowVmcs;
557 /** 0x6000 - The VMREAD bitmap.
558 * @todo r=bird: Do we really need to keep copies for these? Couldn't we just
559 * access the guest memory directly as needed? */
560 uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
561 /** 0x7000 - The VMWRITE bitmap.
562 * @todo r=bird: Do we really need to keep copies for these? Couldn't we just
563 * access the guest memory directly as needed? */
564 uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
565 /** 0x8000 - The VM-entry MSR-load area. */
566 VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
567 /** 0xa000 - The VM-exit MSR-store area. */
568 VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
569 /** 0xc000 - The VM-exit MSR-load area. */
570 VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
571 /** 0xe000 - The MSR permission bitmap.
572 * @todo r=bird: Do we really need to keep copies for these? Couldn't we just
573 * access the guest memory directly as needed? */
574 uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
575 /** 0xf000 - The I/O permission bitmap.
576 * @todo r=bird: Do we really need to keep copies for these? Couldn't we just
577 * access the guest memory directly as needed? */
578 uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
579 /** 0x11000 - The virtual-APIC page.
580 * @note This is used by VT-x hardware... */
581 uint8_t abVirtApicPage[VMX_V_VIRT_APIC_SIZE];
582
583 /** 0x12000 - Guest physical address of the VMXON region. */
584 RTGCPHYS GCPhysVmxon;
585 /** 0x12008 - Guest physical address of the current VMCS pointer. */
586 RTGCPHYS GCPhysVmcs;
587 /** 0x12010 - Guest physical address of the shadow VMCS pointer. */
588 RTGCPHYS GCPhysShadowVmcs;
589 /** 0x12018 - Last emulated VMX instruction/VM-exit diagnostic. */
590 VMXVDIAG enmDiag;
591 /** 0x1201c - VMX abort reason. */
592 VMXABORT enmAbort;
593 /** 0x12020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
594 * (mainly used for info. that's not part of the VMCS). */
595 uint64_t uDiagAux;
596 /** 0x12028 - VMX abort auxiliary info. */
597 uint32_t uAbortAux;
598 /** 0x1202c - Whether the guest is in VMX root mode. */
599 bool fInVmxRootMode;
600 /** 0x1202d - Whether the guest is in VMX non-root mode. */
601 bool fInVmxNonRootMode;
602 /** 0x1202e - Whether the injected events are subjected to event intercepts. */
603 bool fInterceptEvents;
604 /** 0x1202f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
605 * non-root mode before execution of IRET. */
606 bool fNmiUnblockingIret;
607 /** 0x12030 - Guest TSC timestamp of the first PAUSE instruction that is
608 * considered to be the first in a loop. */
609 uint64_t uFirstPauseLoopTick;
610 /** 0x12038 - Guest TSC timestamp of the previous PAUSE instruction. */
611 uint64_t uPrevPauseTick;
612 /** 0x12040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
613 * timer). */
614 uint64_t uEntryTick;
615 /** 0x12048 - Virtual-APIC write offset (until trap-like VM-exit). */
616 uint16_t offVirtApicWrite;
617 /** 0x1204a - Whether virtual-NMI blocking is in effect. */
618 bool fVirtNmiBlocking;
619 /** 0x1204b - Padding. */
620 uint8_t abPadding0[5];
621 /** 0x12050 - Guest VMX MSRs. */
622 VMXMSRS Msrs;
623 } vmx;
624 } CPUM_UNION_NM(s);
625
626 /** 0x12130 - Hardware virtualization type currently in use. */
627 CPUMHWVIRT enmHwvirt;
628 /** 0x12134 - Global interrupt flag - AMD only (always true on Intel). */
629 bool fGif;
630 bool afPadding1[3];
631 /** 0x12138 - A subset of guest force flags that are saved while running the
632 * nested-guest. */
633#ifdef VMCPU_WITH_64_BIT_FFS
634 uint64_t fLocalForcedActions;
635#else
636 uint32_t fLocalForcedActions;
637 uint32_t fPadding;
638#endif
639#if 0
640 /** 0x12140 - Pad to 64 byte boundary. */
641 uint8_t abPadding0[8+16+32];
642#endif
643 } hwvirt;
644} CPUMCTX;
645#pragma pack()
646
647#ifndef VBOX_FOR_DTRACE_LIB
648AssertCompileSizeAlignment(CPUMCTX, 64);
649AssertCompileSizeAlignment(CPUMCTX, 32);
650AssertCompileSizeAlignment(CPUMCTX, 16);
651AssertCompileSizeAlignment(CPUMCTX, 8);
652AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0);
653AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 8);
654AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 16);
655AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 24);
656AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 32);
657AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 40);
658AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 48);
659AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 56);
660AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 64);
661AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 72);
662AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 80);
663AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 88);
664AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 96);
665AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 104);
666AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 112);
667AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 120);
668AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 128);
669AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 152);
670AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 176);
671AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 200);
672AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 224);
673AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 248);
674AssertCompileMemberOffset(CPUMCTX, rip, 272);
675AssertCompileMemberOffset(CPUMCTX, rflags, 280);
676AssertCompileMemberOffset(CPUMCTX, cr0, 288);
677AssertCompileMemberOffset(CPUMCTX, cr2, 296);
678AssertCompileMemberOffset(CPUMCTX, cr3, 304);
679AssertCompileMemberOffset(CPUMCTX, cr4, 312);
680AssertCompileMemberOffset(CPUMCTX, dr, 320);
681AssertCompileMemberOffset(CPUMCTX, gdtr, 384+6);
682AssertCompileMemberOffset(CPUMCTX, idtr, 400+6);
683AssertCompileMemberOffset(CPUMCTX, ldtr, 416);
684AssertCompileMemberOffset(CPUMCTX, tr, 440);
685AssertCompileMemberOffset(CPUMCTX, SysEnter, 464);
686AssertCompileMemberOffset(CPUMCTX, msrEFER, 488);
687AssertCompileMemberOffset(CPUMCTX, msrSTAR, 496);
688AssertCompileMemberOffset(CPUMCTX, msrPAT, 504);
689AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 512);
690AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 520);
691AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 528);
692AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 536);
693AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x240);
694AssertCompileMemberOffset(CPUMCTX, aXcr, 0x260);
695AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x270);
696AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x278);
697AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x300);
698AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x300);
699AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x100);
700/* Only do spot checks for hwvirt */
701AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
702AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
703AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
704AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
705AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
706AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
707AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
708AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
709AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
710AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
711AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
712AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
713AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
714AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVirtApicPage, X86_PAGE_SIZE);
715AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
716AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
717AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
718AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
719AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1204a);
720AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x12130);
721AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x12134);
722AssertCompileMemberOffset(CPUMCTX, hwvirt.fLocalForcedActions, 0x12138);
723AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
724AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
725AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
726AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
727AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
728AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
729AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
730AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
731AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
732AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
733AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
734AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
735AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
736AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
737AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
738AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
739AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
740AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
741AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
742AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
743AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
744AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
745AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
746AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
747AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
748AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
749AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
750AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
751AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
752AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
753AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
754AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
755AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
756AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
757AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
758AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
759AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
760AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
761AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
762AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
763AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
764AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
765AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
766AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
767AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
768AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
769AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
770AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
771AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
772AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
773AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
774AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
775AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
776AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
777AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
778AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
779AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
780AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
781# ifndef _MSC_VER
782AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
783AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
784AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
785AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
786AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
787AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
788AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
789AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
790AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
791AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
792AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
793AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
794AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
795AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
796AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
797AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
798AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
799AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
800AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
801AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
802AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
803AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
804# endif
805
806
807/**
808 * Calculates the pointer to the given extended state component.
809 *
810 * @returns Pointer of type @a a_PtrType
811 * @param a_pCtx Pointer to the context.
812 * @param a_iCompBit The extended state component bit number. This bit
813 * must be set in CPUMCTX::fXStateMask.
814 * @param a_PtrType The pointer type of the extended state component.
815 *
816 */
817#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
818# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
819 ([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
820 { \
821 AssertCompile((a_iCompBit) < 64U); \
822 AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
823 AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
824 return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
825 }(a_pCtx))
826#elif defined(VBOX_STRICT) && defined(__GNUC__)
827# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
828 __extension__ (\
829 { \
830 AssertCompile((a_iCompBit) < 64U); \
831 AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
832 AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
833 (a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
834 })
835#else
836# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
837 ((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
838#endif
839
840/**
841 * Gets the CPUMCTXCORE part of a CPUMCTX.
842 */
843# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
844
845/**
846 * Gets the CPUMCTX part from a CPUMCTXCORE.
847 */
848# define CPUMCTX_FROM_CORE(a_pCtxCore) RT_FROM_MEMBER(a_pCtxCore, CPUMCTX, rax)
849
850/**
851 * Gets the first selector register of a CPUMCTX.
852 *
853 * Use this with X86_SREG_COUNT to loop thru the selector registers.
854 */
855# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
856
857#endif /* !VBOX_FOR_DTRACE_LIB */
858
859
860/** @name CPUMCTX_EXTRN_XXX
861 * Used for parts of the CPUM state that is externalized and needs fetching
862 * before use.
863 *
864 * @{ */
865/** External state keeper: Invalid. */
866#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
867/** External state keeper: HM. */
868#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
869/** External state keeper: NEM. */
870#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
871/** External state keeper: REM. */
872#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
873/** External state keeper mask. */
874#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
875
876/** The RIP register value is kept externally. */
877#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
878/** The RFLAGS register values are kept externally. */
879#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
880
881/** The RAX register value is kept externally. */
882#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
883/** The RCX register value is kept externally. */
884#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
885/** The RDX register value is kept externally. */
886#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
887/** The RBX register value is kept externally. */
888#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
889/** The RSP register value is kept externally. */
890#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
891/** The RBP register value is kept externally. */
892#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
893/** The RSI register value is kept externally. */
894#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
895/** The RDI register value is kept externally. */
896#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
897/** The R8 thru R15 register values are kept externally. */
898#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
899/** General purpose registers mask. */
900#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
901
902/** The ES register values are kept externally. */
903#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
904/** The CS register values are kept externally. */
905#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
906/** The SS register values are kept externally. */
907#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
908/** The DS register values are kept externally. */
909#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
910/** The FS register values are kept externally. */
911#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
912/** The GS register values are kept externally. */
913#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
914/** Segment registers (includes CS). */
915#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
916/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
917#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
918#ifndef VBOX_FOR_DTRACE_LIB
919AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
920AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
921AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
922AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
923AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
924#endif
925
926/** The GDTR register values are kept externally. */
927#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
928/** The IDTR register values are kept externally. */
929#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
930/** The LDTR register values are kept externally. */
931#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
932/** The TR register values are kept externally. */
933#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
934/** Table register mask. */
935#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
936
937/** The CR0 register value is kept externally. */
938#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
939/** The CR2 register value is kept externally. */
940#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
941/** The CR3 register value is kept externally. */
942#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
943/** The CR4 register value is kept externally. */
944#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
945/** Control register mask. */
946#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
947/** The TPR/CR8 register value is kept externally. */
948#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
949/** The EFER register value is kept externally. */
950#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
951
952/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
953#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
954/** The DR6 register value is kept externally. */
955#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
956/** The DR7 register value is kept externally. */
957#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
958/** Debug register mask. */
959#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
960
961/** The XSAVE_C_X87 state is kept externally. */
962#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
963/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
964 * XSAVE_C_OPMASK state is kept externally. */
965#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
966/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
967 * CPUMCTX_EXTRN_SEE_AVX is kept externally. */
968#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
969/** The state of XCR0 and XCR1 register values are kept externally. */
970#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
971
972
973/** The KERNEL GS BASE MSR value is kept externally. */
974#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
975/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
976#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
977/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
978#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
979/** The TSC_AUX MSR is kept externally. */
980#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
981/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
982 * CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
983 * CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
984#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
985
986/** Mask of all the MSRs. */
987#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS \
988 | CPUMCTX_EXTRN_SYSENTER_MSRS | CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS)
989
990/** Hardware-virtualization (SVM or VMX) state is kept externally. */
991#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
992
993/** Mask of bits the keepers can use for state tracking. */
994#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
995
996/** NEM/Win: Event injection (known was interruption) pending state. */
997#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
998/** NEM/Win: Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS). */
999#define CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT UINT64_C(0x0002000000000000)
1000/** NEM/Win: Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
1001#define CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI UINT64_C(0x0004000000000000)
1002/** NEM/Win: Mask. */
1003#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0007000000000000)
1004
1005/** HM/SVM: Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS). */
1006#define CPUMCTX_EXTRN_HM_SVM_INT_SHADOW UINT64_C(0x0001000000000000)
1007/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
1008#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0002000000000000)
1009/** HM/SVM: Mask. */
1010#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0003000000000000)
1011
1012/** HM/VMX: Guest-interruptibility state (VMCPU_FF_INHIBIT_INTERRUPTS,
1013 * VMCPU_FF_BLOCK_NMIS). */
1014#define CPUMCTX_EXTRN_HM_VMX_INT_STATE UINT64_C(0x0001000000000000)
1015/** HM/VMX: Mask. */
1016#define CPUMCTX_EXTRN_HM_VMX_MASK UINT64_C(0x0001000000000000)
1017
1018/** All CPUM state bits, not including keeper specific ones. */
1019#define CPUMCTX_EXTRN_ALL UINT64_C(0x000003fffffffffc)
1020/** All CPUM state bits, including keeper specific ones. */
1021#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
1022/** @} */
1023
1024
1025/**
1026 * Additional guest MSRs (i.e. not part of the CPU context structure).
1027 *
1028 * @remarks Never change the order here because of the saved stated! The size
1029 * can in theory be changed, but keep older VBox versions in mind.
1030 */
1031typedef union CPUMCTXMSRS
1032{
1033 struct
1034 {
1035 uint64_t TscAux; /**< MSR_K8_TSC_AUX */
1036 uint64_t MiscEnable; /**< MSR_IA32_MISC_ENABLE */
1037 uint64_t MtrrDefType; /**< IA32_MTRR_DEF_TYPE */
1038 uint64_t MtrrFix64K_00000; /**< IA32_MTRR_FIX16K_80000 */
1039 uint64_t MtrrFix16K_80000; /**< IA32_MTRR_FIX16K_80000 */
1040 uint64_t MtrrFix16K_A0000; /**< IA32_MTRR_FIX16K_A0000 */
1041 uint64_t MtrrFix4K_C0000; /**< IA32_MTRR_FIX4K_C0000 */
1042 uint64_t MtrrFix4K_C8000; /**< IA32_MTRR_FIX4K_C8000 */
1043 uint64_t MtrrFix4K_D0000; /**< IA32_MTRR_FIX4K_D0000 */
1044 uint64_t MtrrFix4K_D8000; /**< IA32_MTRR_FIX4K_D8000 */
1045 uint64_t MtrrFix4K_E0000; /**< IA32_MTRR_FIX4K_E0000 */
1046 uint64_t MtrrFix4K_E8000; /**< IA32_MTRR_FIX4K_E8000 */
1047 uint64_t MtrrFix4K_F0000; /**< IA32_MTRR_FIX4K_F0000 */
1048 uint64_t MtrrFix4K_F8000; /**< IA32_MTRR_FIX4K_F8000 */
1049 uint64_t PkgCStateCfgCtrl; /**< MSR_PKG_CST_CONFIG_CONTROL */
1050 uint64_t SpecCtrl; /**< IA32_SPEC_CTRL */
1051 uint64_t ArchCaps; /**< IA32_ARCH_CAPABILITIES */
1052 } msr;
1053 uint64_t au64[64];
1054} CPUMCTXMSRS;
1055/** Pointer to the guest MSR state. */
1056typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1057/** Pointer to the const guest MSR state. */
1058typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1059
1060/** @} */
1061
1062RT_C_DECLS_END
1063
1064#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
1065
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