cpumctx.h@ 97183

Last change on this file since 97183 was 97178, checked in by vboxsync, 2 years ago
VMM/CPUM,EM,HM,IEM,++: Moved VMCPU_FF_INHIBIT_INTERRUPTS and VMCPU_FF_BLOCK_NMIS to CPUMCTX::fInhibit. Moved ldtr and tr up to the CPUMCTXCORE area in hope for better cache alignment of rip, rflags and crX register fields. bugref:9941
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File size: 53.2 KB

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_h
37	#define VBOX_INCLUDED_vmm_cpumctx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** @def CPUM_UNION_NM
127	* For compilers (like DTrace) that does not grok nameless unions, we have a
128	* little hack to make them palatable.
129	*/
130	/** @def CPUM_STRUCT_NM
131	* For compilers (like DTrace) that does not grok nameless structs (it is
132	* non-standard C++), we have a little hack to make them palatable.
133	*/
134	#ifdef VBOX_FOR_DTRACE_LIB
135	# define CPUM_UNION_NM(a_Nm) a_Nm
136	# define CPUM_STRUCT_NM(a_Nm) a_Nm
137	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138	# define CPUM_UNION_NM(a_Nm) a_Nm
139	# define CPUM_STRUCT_NM(a_Nm) a_Nm
140	#else
141	# define CPUM_UNION_NM(a_Nm)
142	# define CPUM_STRUCT_NM(a_Nm)
143	#endif
144	/** @def CPUM_UNION_STRUCT_NM
145	* Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146	* the screen in the compile time assertions.
147	*/
148	#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150	/** A general register (union). */
151	typedef union CPUMCTXGREG
152	{
153	/** Natural unsigned integer view. */
154	uint64_t u;
155	/** 64-bit view. */
156	uint64_t u64;
157	/** 32-bit view. */
158	uint32_t u32;
159	/** 16-bit view. */
160	uint16_t u16;
161	/** 8-bit view. */
162	uint8_t u8;
163	/** 8-bit low/high view. */
164	RT_GCC_EXTENSION struct
165	{
166	/** Low byte (al, cl, dl, bl, ++). */
167	uint8_t bLo;
168	/** High byte in the first word - ah, ch, dh, bh. */
169	uint8_t bHi;
170	} CPUM_STRUCT_NM(s);
171	} CPUMCTXGREG;
172	#ifndef VBOX_FOR_DTRACE_LIB
173	AssertCompileSize(CPUMCTXGREG, 8);
174	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176	#endif
177
178
179
180	/**
181	* CPU context core.
182	*
183	* @todo Eliminate this structure!
184	* @deprecated We don't push any context cores any more in TRPM.
185	*/
186	#pragma pack(1)
187	typedef struct CPUMCTXCORE
188	{
189	/** @name General Register.
190	* @note These follow the encoding order (X86_GREG_XXX) and can be accessed as
191	* an array starting a rax.
192	* @{ */
193	union
194	{
195	uint8_t al;
196	uint16_t ax;
197	uint32_t eax;
198	uint64_t rax;
199	} CPUM_UNION_NM(rax);
200	union
201	{
202	uint8_t cl;
203	uint16_t cx;
204	uint32_t ecx;
205	uint64_t rcx;
206	} CPUM_UNION_NM(rcx);
207	union
208	{
209	uint8_t dl;
210	uint16_t dx;
211	uint32_t edx;
212	uint64_t rdx;
213	} CPUM_UNION_NM(rdx);
214	union
215	{
216	uint8_t bl;
217	uint16_t bx;
218	uint32_t ebx;
219	uint64_t rbx;
220	} CPUM_UNION_NM(rbx);
221	union
222	{
223	uint16_t sp;
224	uint32_t esp;
225	uint64_t rsp;
226	} CPUM_UNION_NM(rsp);
227	union
228	{
229	uint16_t bp;
230	uint32_t ebp;
231	uint64_t rbp;
232	} CPUM_UNION_NM(rbp);
233	union
234	{
235	uint8_t sil;
236	uint16_t si;
237	uint32_t esi;
238	uint64_t rsi;
239	} CPUM_UNION_NM(rsi);
240	union
241	{
242	uint8_t dil;
243	uint16_t di;
244	uint32_t edi;
245	uint64_t rdi;
246	} CPUM_UNION_NM(rdi);
247	uint64_t r8;
248	uint64_t r9;
249	uint64_t r10;
250	uint64_t r11;
251	uint64_t r12;
252	uint64_t r13;
253	uint64_t r14;
254	uint64_t r15;
255	/** @} */
256
257	/** @name Segment registers.
258	* @note These follow the encoding order (X86_SREG_XXX) and can be accessed as
259	* an array starting a es.
260	* @{ */
261	CPUMSELREG es;
262	CPUMSELREG cs;
263	CPUMSELREG ss;
264	CPUMSELREG ds;
265	CPUMSELREG fs;
266	CPUMSELREG gs;
267	/** @} */
268
269	CPUMSELREG ldtr;
270	CPUMSELREG tr;
271
272	/** The program counter. */
273	union
274	{
275	uint16_t ip;
276	uint32_t eip;
277	uint64_t rip;
278	} CPUM_UNION_NM(rip);
279
280	/** The flags register. */
281	union
282	{
283	X86EFLAGS eflags;
284	X86RFLAGS rflags;
285	} CPUM_UNION_NM(rflags);
286
287	} CPUMCTXCORE;
288	#pragma pack()
289
290
291	/**
292	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
293	*
294	* @warning Exercise caution while modifying the layout of this struct. It's
295	* part of VM saved states.
296	*/
297	#pragma pack(1)
298	typedef struct SVMHOSTSTATE
299	{
300	uint64_t uEferMsr;
301	uint64_t uCr0;
302	uint64_t uCr4;
303	uint64_t uCr3;
304	uint64_t uRip;
305	uint64_t uRsp;
306	uint64_t uRax;
307	X86RFLAGS rflags;
308	CPUMSELREG es;
309	CPUMSELREG cs;
310	CPUMSELREG ss;
311	CPUMSELREG ds;
312	VBOXGDTR gdtr;
313	VBOXIDTR idtr;
314	uint8_t abPadding[4];
315	} SVMHOSTSTATE;
316	#pragma pack()
317	/** Pointer to the SVMHOSTSTATE structure. */
318	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
319	/** Pointer to a const SVMHOSTSTATE structure. */
320	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
321	#ifndef VBOX_FOR_DTRACE_LIB
322	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
323	AssertCompileSize(SVMHOSTSTATE, 184);
324	#endif
325
326
327	/**
328	* CPU hardware virtualization types.
329	*/
330	typedef enum
331	{
332	CPUMHWVIRT_NONE = 0,
333	CPUMHWVIRT_VMX,
334	CPUMHWVIRT_SVM,
335	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
336	} CPUMHWVIRT;
337	#ifndef VBOX_FOR_DTRACE_LIB
338	AssertCompileSize(CPUMHWVIRT, 4);
339	#endif
340
341
342	/**
343	* CPU context.
344	*/
345	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
346	typedef struct CPUMCTX
347	{
348	/** CPUMCTXCORE Part.
349	* @{ */
350
351	/** General purpose registers. */
352	union /* no tag! */
353	{
354	/** The general purpose register array view, indexed by X86_GREG_XXX. */
355	CPUMCTXGREG aGRegs[16];
356
357	/** 64-bit general purpose register view. */
358	RT_GCC_EXTENSION struct /* no tag! */
359	{
360	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
361	} CPUM_STRUCT_NM(qw);
362	/** 64-bit general purpose register view. */
363	RT_GCC_EXTENSION struct /* no tag! */
364	{
365	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
366	} CPUM_STRUCT_NM(qw2);
367	/** 32-bit general purpose register view. */
368	RT_GCC_EXTENSION struct /* no tag! */
369	{
370	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
371	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
372	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
373	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
374	} CPUM_STRUCT_NM(dw);
375	/** 16-bit general purpose register view. */
376	RT_GCC_EXTENSION struct /* no tag! */
377	{
378	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
379	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
380	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
381	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
382	} CPUM_STRUCT_NM(w);
383	RT_GCC_EXTENSION struct /* no tag! */
384	{
385	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
386	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
387	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
388	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
389	} CPUM_STRUCT_NM(b);
390	} CPUM_UNION_NM(g);
391
392	/** Segment registers. */
393	union /* no tag! */
394	{
395	/** The segment register array view, indexed by X86_SREG_XXX. */
396	CPUMSELREG aSRegs[6];
397	/** The named segment register view. */
398	RT_GCC_EXTENSION struct /* no tag! */
399	{
400	CPUMSELREG es, cs, ss, ds, fs, gs;
401	} CPUM_STRUCT_NM(n);
402	} CPUM_UNION_NM(s);
403
404	/** The task register.
405	* Only the guest context uses all the members. */
406	CPUMSELREG ldtr;
407	/** The task register.
408	* Only the guest context uses all the members. */
409	CPUMSELREG tr;
410
411	/** The program counter. */
412	union
413	{
414	uint16_t ip;
415	uint32_t eip;
416	uint64_t rip;
417	} CPUM_UNION_NM(rip);
418
419	/** The flags register. */
420	union
421	{
422	X86EFLAGS eflags;
423	X86RFLAGS rflags;
424	} CPUM_UNION_NM(rflags);
425
426	/** @} / /(CPUMCTXCORE)*/
427
428	/** Interrupt & exception inhibiting (CPUMCTX_INHIBIT_XXX). */
429	uint8_t fInhibit;
430	uint8_t abPadding[7];
431	/** The RIP value fInhibit is/was valid for. */
432	uint64_t uRipInhibitInt;
433
434	/** @name Control registers.
435	* @{ */
436	uint64_t cr0;
437	uint64_t cr2;
438	uint64_t cr3;
439	uint64_t cr4;
440	/** @todo Add the 4 PAE PDPE registers. See PGMCPU::aGstPaePdpeRegs. */
441	/** @} */
442
443	/** Debug registers.
444	* @remarks DR4 and DR5 should not be used since they are aliases for
445	* DR6 and DR7 respectively on both AMD and Intel CPUs.
446	* @remarks DR8-15 are currently not supported by AMD or Intel, so
447	* neither do we.
448	*/
449	uint64_t dr[8];
450
451	/** Padding before the structure so the 64-bit member is correctly aligned.
452	* @todo fix this structure! */
453	uint16_t gdtrPadding[3];
454	/** Global Descriptor Table register. */
455	VBOXGDTR gdtr;
456
457	/** Padding before the structure so the 64-bit member is correctly aligned.
458	* @todo fix this structure! */
459	uint16_t idtrPadding[3];
460	/** Interrupt Descriptor Table register. */
461	VBOXIDTR idtr;
462
463	/** The sysenter msr registers.
464	* This member is not used by the hypervisor context. */
465	CPUMSYSENTER SysEnter;
466
467	/** @name System MSRs.
468	* @{ */
469	uint64_t msrEFER;
470	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
471	uint64_t msrPAT; /*< Page attribute table. /
472	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
473	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
474	uint64_t msrSFMASK; /*< syscall flag mask. /
475	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
476	/** @} */
477
478	/** 0x230 - Externalized state tracker, CPUMCTX_EXTRN_XXX.
479	* @todo Move up after uRipInhibitInt after fInhibit moves into RFLAGS.
480	* That will put this in the same cacheline as RIP, RFLAGS and CR0
481	* which are typically always imported and exported again during an
482	* VM exit. */
483	uint64_t fExtrn;
484
485	uint64_t u64Unused;
486
487	/** 0x240 - PAE PDPTEs. */
488	X86PDPE aPaePdpes[4];
489
490	/** 0x260 - The XCR0..XCR1 registers. */
491	uint64_t aXcr[2];
492	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
493	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
494	uint64_t fXStateMask;
495	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
496	bool fUsedFpuGuest;
497	uint8_t afUnused[7];
498
499	/* ---- Start of members not zeroed at reset. ---- */
500
501	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
502	* @note Everything before this member will be memset to zero during reset. */
503	uint16_t aoffXState[64];
504	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
505	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
506	union /* no tag */
507	{
508	X86XSAVEAREA XState;
509	/** Byte view for simple indexing and space allocation. */
510	uint8_t abXState[0x4000 - 0x300];
511	} CPUM_UNION_NM(u);
512
513	/** 0x4000 - Hardware virtualization state.
514	* @note This is page aligned, so an full page member comes first in the
515	* substructures. */
516	struct
517	{
518	union /* no tag! */
519	{
520	struct
521	{
522	/** 0x4000 - Cache of the nested-guest VMCB. */
523	SVMVMCB Vmcb;
524	/** 0x5000 - The MSRPM (MSR Permission bitmap).
525	*
526	* This need not be physically contiguous pages because we use the one from
527	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
528	* This one is just used for caching the bitmap from guest physical memory.
529	*
530	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
531	* really need to even be page aligned.
532	*
533	* Also, couldn't we just access the guest page directly when we need to,
534	* or do we have to use a cached copy of it? */
535	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
536	/** 0x7000 - The IOPM (IO Permission bitmap).
537	*
538	* This need not be physically contiguous pages because we re-use the ring-0
539	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
540	* because it's identical (we trap all IO accesses).
541	*
542	* This one is just used for caching the IOPM from guest physical memory in
543	* case the guest hypervisor allows direct access to some IO ports.
544	*
545	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
546	* really need to even be page aligned.
547	*
548	* Also, couldn't we just access the guest page directly when we need to,
549	* or do we have to use a cached copy of it? */
550	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
551
552	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
553	uint64_t uMsrHSavePa;
554	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
555	RTGCPHYS GCPhysVmcb;
556	/** 0xa010 - Guest's host-state save area. */
557	SVMHOSTSTATE HostState;
558	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
559	* executed. */
560	uint64_t uPrevPauseTick;
561	/** 0xa0d0 - Pause filter count. */
562	uint16_t cPauseFilter;
563	/** 0xa0d2 - Pause filter threshold. */
564	uint16_t cPauseFilterThreshold;
565	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
566	bool fInterceptEvents;
567	/** 0xa0d5 - Padding. */
568	bool afPadding[3];
569	} svm;
570
571	struct
572	{
573	/** 0x4000 - The current VMCS. */
574	VMXVVMCS Vmcs;
575	/** 0X5000 - The shadow VMCS. */
576	VMXVVMCS ShadowVmcs;
577	/** 0x6000 - The VMREAD bitmap.
578	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
579	* access the guest memory directly as needed? */
580	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
581	/** 0x7000 - The VMWRITE bitmap.
582	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
583	* access the guest memory directly as needed? */
584	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
585	/** 0x8000 - The VM-entry MSR-load area. */
586	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
587	/** 0xa000 - The VM-exit MSR-store area. */
588	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
589	/** 0xc000 - The VM-exit MSR-load area. */
590	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
591	/** 0xe000 - The MSR permission bitmap.
592	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
593	* access the guest memory directly as needed? */
594	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
595	/** 0xf000 - The I/O permission bitmap.
596	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
597	* access the guest memory directly as needed? */
598	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
599
600	/** 0x11000 - Guest physical address of the VMXON region. */
601	RTGCPHYS GCPhysVmxon;
602	/** 0x11008 - Guest physical address of the current VMCS pointer. */
603	RTGCPHYS GCPhysVmcs;
604	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
605	RTGCPHYS GCPhysShadowVmcs;
606	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
607	VMXVDIAG enmDiag;
608	/** 0x1101c - VMX abort reason. */
609	VMXABORT enmAbort;
610	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
611	* (mainly used for info. that's not part of the VMCS). */
612	uint64_t uDiagAux;
613	/** 0x11028 - VMX abort auxiliary info. */
614	uint32_t uAbortAux;
615	/** 0x1102c - Whether the guest is in VMX root mode. */
616	bool fInVmxRootMode;
617	/** 0x1102d - Whether the guest is in VMX non-root mode. */
618	bool fInVmxNonRootMode;
619	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
620	bool fInterceptEvents;
621	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
622	* non-root mode before execution of IRET. */
623	bool fNmiUnblockingIret;
624	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
625	* considered to be the first in a loop. */
626	uint64_t uFirstPauseLoopTick;
627	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
628	uint64_t uPrevPauseTick;
629	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
630	* timer). */
631	uint64_t uEntryTick;
632	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
633	uint16_t offVirtApicWrite;
634	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
635	bool fVirtNmiBlocking;
636	/** 0x1104b - Padding. */
637	uint8_t abPadding0[5];
638	/** 0x11050 - Guest VMX MSRs. */
639	VMXMSRS Msrs;
640	} vmx;
641	} CPUM_UNION_NM(s);
642
643	/** 0x11130 - Hardware virtualization type currently in use. */
644	CPUMHWVIRT enmHwvirt;
645	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
646	bool fGif;
647	/** 0x11135 - Padding. */
648	bool afPadding0[3];
649	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
650	* saved while running the nested-guest. */
651	uint32_t fSavedInhibit;
652	/** 0x1113c - Pad to 64 byte boundary. */
653	uint8_t abPadding1[4];
654	} hwvirt;
655	} CPUMCTX;
656	#pragma pack()
657
658	#ifndef VBOX_FOR_DTRACE_LIB
659	AssertCompileSizeAlignment(CPUMCTX, 64);
660	AssertCompileSizeAlignment(CPUMCTX, 32);
661	AssertCompileSizeAlignment(CPUMCTX, 16);
662	AssertCompileSizeAlignment(CPUMCTX, 8);
663	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
664	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
665	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
666	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
667	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
668	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
669	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
670	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
671	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
672	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
673	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
674	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
675	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
676	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
677	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
678	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
679	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
680	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
681	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
682	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
683	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
684	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
685	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
686	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
687	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
688	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
689	AssertCompileMemberOffset(CPUMCTX, fInhibit, 0x0150);
690	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
691	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
692	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
693	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
694	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
695	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
696	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
697	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
698	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
699	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
700	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
701	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
702	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
703	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
704	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
705	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
706	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
707	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
708	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
709	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
710	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
711	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
712	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
713	/* Only do spot checks for hwvirt */
714	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
715	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
716	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
717	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
718	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
719	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
720	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
721	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
722	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
723	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
724	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
725	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
726	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
727	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
728	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
729	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
730	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
731	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
732	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
733	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
734	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
742	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
759	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
765	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
766	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
767	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
768	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
769	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
770	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
771	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
772	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
773	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
774	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
775	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
776	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
777	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
778	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
779	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
780	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
781	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
782	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
783	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
784	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
785	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
786	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
787	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
788	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
789	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
790	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
791	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
792	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
793	# ifndef _MSC_VER
794	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
795	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
796	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
797	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
798	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
799	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
800	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
801	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
802	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
803	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
804	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
805	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
806	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
807	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
808	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
809	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
810	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
811	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
812	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
813	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
814	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
815	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
816	# endif
817
818
819	/**
820	* Calculates the pointer to the given extended state component.
821	*
822	* @returns Pointer of type @a a_PtrType
823	* @param a_pCtx Pointer to the context.
824	* @param a_iCompBit The extended state component bit number. This bit
825	* must be set in CPUMCTX::fXStateMask.
826	* @param a_PtrType The pointer type of the extended state component.
827	*
828	*/
829	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
830	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
831	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
832	{ \
833	AssertCompile((a_iCompBit) < 64U); \
834	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
835	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
836	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
837	}(a_pCtx))
838	#elif defined(VBOX_STRICT) && defined(__GNUC__)
839	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
840	__extension__ (\
841	{ \
842	AssertCompile((a_iCompBit) < 64U); \
843	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
844	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
845	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
846	})
847	#else
848	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
849	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
850	#endif
851
852	/**
853	* Gets the CPUMCTXCORE part of a CPUMCTX.
854	*/
855	# define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->rax)
856
857	/**
858	* Gets the CPUMCTX part from a CPUMCTXCORE.
859	*/
860	# define CPUMCTX_FROM_CORE(a_pCtxCore) RT_FROM_MEMBER(a_pCtxCore, CPUMCTX, rax)
861
862	/**
863	* Gets the first selector register of a CPUMCTX.
864	*
865	* Use this with X86_SREG_COUNT to loop thru the selector registers.
866	*/
867	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
868
869	#endif /* !VBOX_FOR_DTRACE_LIB */
870
871
872	/** @name CPUMCTX_EXTRN_XXX
873	* Used for parts of the CPUM state that is externalized and needs fetching
874	* before use.
875	*
876	* @{ */
877	/** External state keeper: Invalid. */
878	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
879	/** External state keeper: HM. */
880	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
881	/** External state keeper: NEM. */
882	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
883	/** External state keeper: REM. */
884	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
885	/** External state keeper mask. */
886	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
887
888	/** The RIP register value is kept externally. */
889	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
890	/** The RFLAGS register values are kept externally. */
891	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
892
893	/** The RAX register value is kept externally. */
894	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
895	/** The RCX register value is kept externally. */
896	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
897	/** The RDX register value is kept externally. */
898	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
899	/** The RBX register value is kept externally. */
900	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
901	/** The RSP register value is kept externally. */
902	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
903	/** The RBP register value is kept externally. */
904	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
905	/** The RSI register value is kept externally. */
906	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
907	/** The RDI register value is kept externally. */
908	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
909	/** The R8 thru R15 register values are kept externally. */
910	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
911	/** General purpose registers mask. */
912	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
913
914	/** The ES register values are kept externally. */
915	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
916	/** The CS register values are kept externally. */
917	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
918	/** The SS register values are kept externally. */
919	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
920	/** The DS register values are kept externally. */
921	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
922	/** The FS register values are kept externally. */
923	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
924	/** The GS register values are kept externally. */
925	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
926	/** Segment registers (includes CS). */
927	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
928	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
929	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
930	#ifndef VBOX_FOR_DTRACE_LIB
931	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
932	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
933	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
934	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
935	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
936	#endif
937
938	/** The GDTR register values are kept externally. */
939	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
940	/** The IDTR register values are kept externally. */
941	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
942	/** The LDTR register values are kept externally. */
943	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
944	/** The TR register values are kept externally. */
945	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
946	/** Table register mask. */
947	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
948
949	/** The CR0 register value is kept externally. */
950	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
951	/** The CR2 register value is kept externally. */
952	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
953	/** The CR3 register value is kept externally. */
954	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
955	/** The CR4 register value is kept externally. */
956	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
957	/** Control register mask. */
958	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
959	/** The TPR/CR8 register value is kept externally. */
960	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
961	/** The EFER register value is kept externally. */
962	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
963
964	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
965	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
966	/** The DR6 register value is kept externally. */
967	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
968	/** The DR7 register value is kept externally. */
969	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
970	/** Debug register mask. */
971	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
972
973	/** The XSAVE_C_X87 state is kept externally. */
974	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
975	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
976	* XSAVE_C_OPMASK state is kept externally. */
977	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
978	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
979	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
980	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
981	/** The state of XCR0 and XCR1 register values are kept externally. */
982	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
983
984
985	/** The KERNEL GS BASE MSR value is kept externally. */
986	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
987	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
988	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
989	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
990	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
991	/** The TSC_AUX MSR is kept externally. */
992	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
993	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
994	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
995	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
996	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
997
998	/** Mask of all the MSRs. */
999	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
1000	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
1001
1002	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
1003	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
1004
1005	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
1006	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
1007	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
1008	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
1009
1010	/** Mask of bits the keepers can use for state tracking. */
1011	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
1012
1013	/** NEM/Win: Event injection (known was interruption) pending state. */
1014	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
1015	/** NEM/Win: Mask. */
1016	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
1017
1018	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
1019	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
1020	/** HM/SVM: Mask. */
1021	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
1022
1023	/** All CPUM state bits, not including keeper specific ones. */
1024	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
1025	/** All CPUM state bits, including keeper specific ones. */
1026	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
1027	/** @} */
1028
1029
1030	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
1031	* @{ */
1032	/** Interrupt shadow following MOV SS or POP SS.
1033	*
1034	* When this in effect, both maskable and non-maskable interrupts are blocked
1035	* from delivery for one instruction. Same for certain debug exceptions too,
1036	* unlike the STI variant.
1037	*
1038	* It is implementation specific whether a sequence of two or more of these
1039	* instructions will have any effect on the instruction following the last one
1040	* of them. */
1041	#define CPUMCTX_INHIBIT_SHADOW_SS UINT8_C(0x01)
1042	/** Interrupt shadow following STI.
1043	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
1044	#define CPUMCTX_INHIBIT_SHADOW_STI UINT8_C(0x02)
1045	/** Mask combining STI and SS shadowing. */
1046	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
1047
1048	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
1049	*
1050	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
1051	* "The processor also invokes certain hardware conditions to ensure that no
1052	* other interrupts, including NMI interrupts, are received until the NMI
1053	* handler has completed executing." This flag indicates that these
1054	* conditions are currently active. */
1055	#define CPUMCTX_INHIBIT_NMI UINT8_C(0x04)
1056	/** @} */
1057
1058
1059	/**
1060	* Additional guest MSRs (i.e. not part of the CPU context structure).
1061	*
1062	* @remarks Never change the order here because of the saved stated! The size
1063	* can in theory be changed, but keep older VBox versions in mind.
1064	*/
1065	typedef union CPUMCTXMSRS
1066	{
1067	struct
1068	{
1069	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1070	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1071	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1072	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1073	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1074	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1075	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1076	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1077	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1078	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1079	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1080	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1081	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1082	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1083	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1084	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1085	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1086	} msr;
1087	uint64_t au64[64];
1088	} CPUMCTXMSRS;
1089	/** Pointer to the guest MSR state. */
1090	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1091	/** Pointer to the const guest MSR state. */
1092	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1093
1094	/** @} */
1095
1096	RT_C_DECLS_END
1097
1098	#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
1099

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 97183

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