cpumctx.h@ 97213

Last change on this file since 97213 was 97213, checked in by vboxsync, 2 years ago
VMM,VBox/types.h: Removed the CPUMCTXCORE type.
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Line
1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_h
37	#define VBOX_INCLUDED_vmm_cpumctx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** @def CPUM_UNION_NM
127	* For compilers (like DTrace) that does not grok nameless unions, we have a
128	* little hack to make them palatable.
129	*/
130	/** @def CPUM_STRUCT_NM
131	* For compilers (like DTrace) that does not grok nameless structs (it is
132	* non-standard C++), we have a little hack to make them palatable.
133	*/
134	#ifdef VBOX_FOR_DTRACE_LIB
135	# define CPUM_UNION_NM(a_Nm) a_Nm
136	# define CPUM_STRUCT_NM(a_Nm) a_Nm
137	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138	# define CPUM_UNION_NM(a_Nm) a_Nm
139	# define CPUM_STRUCT_NM(a_Nm) a_Nm
140	#else
141	# define CPUM_UNION_NM(a_Nm)
142	# define CPUM_STRUCT_NM(a_Nm)
143	#endif
144	/** @def CPUM_UNION_STRUCT_NM
145	* Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146	* the screen in the compile time assertions.
147	*/
148	#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150	/** A general register (union). */
151	typedef union CPUMCTXGREG
152	{
153	/** Natural unsigned integer view. */
154	uint64_t u;
155	/** 64-bit view. */
156	uint64_t u64;
157	/** 32-bit view. */
158	uint32_t u32;
159	/** 16-bit view. */
160	uint16_t u16;
161	/** 8-bit view. */
162	uint8_t u8;
163	/** 8-bit low/high view. */
164	RT_GCC_EXTENSION struct
165	{
166	/** Low byte (al, cl, dl, bl, ++). */
167	uint8_t bLo;
168	/** High byte in the first word - ah, ch, dh, bh. */
169	uint8_t bHi;
170	} CPUM_STRUCT_NM(s);
171	} CPUMCTXGREG;
172	#ifndef VBOX_FOR_DTRACE_LIB
173	AssertCompileSize(CPUMCTXGREG, 8);
174	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176	#endif
177
178
179
180	/**
181	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
182	*
183	* @warning Exercise caution while modifying the layout of this struct. It's
184	* part of VM saved states.
185	*/
186	#pragma pack(1)
187	typedef struct SVMHOSTSTATE
188	{
189	uint64_t uEferMsr;
190	uint64_t uCr0;
191	uint64_t uCr4;
192	uint64_t uCr3;
193	uint64_t uRip;
194	uint64_t uRsp;
195	uint64_t uRax;
196	X86RFLAGS rflags;
197	CPUMSELREG es;
198	CPUMSELREG cs;
199	CPUMSELREG ss;
200	CPUMSELREG ds;
201	VBOXGDTR gdtr;
202	VBOXIDTR idtr;
203	uint8_t abPadding[4];
204	} SVMHOSTSTATE;
205	#pragma pack()
206	/** Pointer to the SVMHOSTSTATE structure. */
207	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
208	/** Pointer to a const SVMHOSTSTATE structure. */
209	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
210	#ifndef VBOX_FOR_DTRACE_LIB
211	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
212	AssertCompileSize(SVMHOSTSTATE, 184);
213	#endif
214
215
216	/**
217	* CPU hardware virtualization types.
218	*/
219	typedef enum
220	{
221	CPUMHWVIRT_NONE = 0,
222	CPUMHWVIRT_VMX,
223	CPUMHWVIRT_SVM,
224	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
225	} CPUMHWVIRT;
226	#ifndef VBOX_FOR_DTRACE_LIB
227	AssertCompileSize(CPUMHWVIRT, 4);
228	#endif
229
230
231	/**
232	* CPU context.
233	*/
234	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
235	typedef struct CPUMCTX
236	{
237	/** General purpose registers. */
238	union /* no tag! */
239	{
240	/** The general purpose register array view, indexed by X86_GREG_XXX. */
241	CPUMCTXGREG aGRegs[16];
242
243	/** 64-bit general purpose register view. */
244	RT_GCC_EXTENSION struct /* no tag! */
245	{
246	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
247	} CPUM_STRUCT_NM(qw);
248	/** 64-bit general purpose register view. */
249	RT_GCC_EXTENSION struct /* no tag! */
250	{
251	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
252	} CPUM_STRUCT_NM(qw2);
253	/** 32-bit general purpose register view. */
254	RT_GCC_EXTENSION struct /* no tag! */
255	{
256	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
257	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
258	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
259	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
260	} CPUM_STRUCT_NM(dw);
261	/** 16-bit general purpose register view. */
262	RT_GCC_EXTENSION struct /* no tag! */
263	{
264	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
265	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
266	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
267	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
268	} CPUM_STRUCT_NM(w);
269	RT_GCC_EXTENSION struct /* no tag! */
270	{
271	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
272	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
273	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
274	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
275	} CPUM_STRUCT_NM(b);
276	} CPUM_UNION_NM(g);
277
278	/** Segment registers. */
279	union /* no tag! */
280	{
281	/** The segment register array view, indexed by X86_SREG_XXX. */
282	CPUMSELREG aSRegs[6];
283	/** The named segment register view. */
284	RT_GCC_EXTENSION struct /* no tag! */
285	{
286	CPUMSELREG es, cs, ss, ds, fs, gs;
287	} CPUM_STRUCT_NM(n);
288	} CPUM_UNION_NM(s);
289
290	/** The task register.
291	* Only the guest context uses all the members. */
292	CPUMSELREG ldtr;
293	/** The task register.
294	* Only the guest context uses all the members. */
295	CPUMSELREG tr;
296
297	/** The program counter. */
298	union
299	{
300	uint16_t ip;
301	uint32_t eip;
302	uint64_t rip;
303	} CPUM_UNION_NM(rip);
304
305	/** The flags register. */
306	union
307	{
308	X86EFLAGS eflags;
309	X86RFLAGS rflags;
310	} CPUM_UNION_NM(rflags);
311
312	/** Interrupt & exception inhibiting (CPUMCTX_INHIBIT_XXX). */
313	uint8_t fInhibit;
314	uint8_t abPadding[7];
315	/** The RIP value fInhibit is/was valid for. */
316	uint64_t uRipInhibitInt;
317
318	/** @name Control registers.
319	* @{ */
320	uint64_t cr0;
321	uint64_t cr2;
322	uint64_t cr3;
323	uint64_t cr4;
324	/** @todo Add the 4 PAE PDPE registers. See PGMCPU::aGstPaePdpeRegs. */
325	/** @} */
326
327	/** Debug registers.
328	* @remarks DR4 and DR5 should not be used since they are aliases for
329	* DR6 and DR7 respectively on both AMD and Intel CPUs.
330	* @remarks DR8-15 are currently not supported by AMD or Intel, so
331	* neither do we.
332	*/
333	uint64_t dr[8];
334
335	/** Padding before the structure so the 64-bit member is correctly aligned.
336	* @todo fix this structure! */
337	uint16_t gdtrPadding[3];
338	/** Global Descriptor Table register. */
339	VBOXGDTR gdtr;
340
341	/** Padding before the structure so the 64-bit member is correctly aligned.
342	* @todo fix this structure! */
343	uint16_t idtrPadding[3];
344	/** Interrupt Descriptor Table register. */
345	VBOXIDTR idtr;
346
347	/** The sysenter msr registers.
348	* This member is not used by the hypervisor context. */
349	CPUMSYSENTER SysEnter;
350
351	/** @name System MSRs.
352	* @{ */
353	uint64_t msrEFER;
354	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
355	uint64_t msrPAT; /*< Page attribute table. /
356	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
357	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
358	uint64_t msrSFMASK; /*< syscall flag mask. /
359	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
360	/** @} */
361
362	/** 0x230 - Externalized state tracker, CPUMCTX_EXTRN_XXX.
363	* @todo Move up after uRipInhibitInt after fInhibit moves into RFLAGS.
364	* That will put this in the same cacheline as RIP, RFLAGS and CR0
365	* which are typically always imported and exported again during an
366	* VM exit. */
367	uint64_t fExtrn;
368
369	uint64_t u64Unused;
370
371	/** 0x240 - PAE PDPTEs. */
372	X86PDPE aPaePdpes[4];
373
374	/** 0x260 - The XCR0..XCR1 registers. */
375	uint64_t aXcr[2];
376	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
377	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
378	uint64_t fXStateMask;
379	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
380	bool fUsedFpuGuest;
381	uint8_t afUnused[7];
382
383	/* ---- Start of members not zeroed at reset. ---- */
384
385	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
386	* @note Everything before this member will be memset to zero during reset. */
387	uint16_t aoffXState[64];
388	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
389	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
390	union /* no tag */
391	{
392	X86XSAVEAREA XState;
393	/** Byte view for simple indexing and space allocation. */
394	uint8_t abXState[0x4000 - 0x300];
395	} CPUM_UNION_NM(u);
396
397	/** 0x4000 - Hardware virtualization state.
398	* @note This is page aligned, so an full page member comes first in the
399	* substructures. */
400	struct
401	{
402	union /* no tag! */
403	{
404	struct
405	{
406	/** 0x4000 - Cache of the nested-guest VMCB. */
407	SVMVMCB Vmcb;
408	/** 0x5000 - The MSRPM (MSR Permission bitmap).
409	*
410	* This need not be physically contiguous pages because we use the one from
411	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
412	* This one is just used for caching the bitmap from guest physical memory.
413	*
414	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
415	* really need to even be page aligned.
416	*
417	* Also, couldn't we just access the guest page directly when we need to,
418	* or do we have to use a cached copy of it? */
419	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
420	/** 0x7000 - The IOPM (IO Permission bitmap).
421	*
422	* This need not be physically contiguous pages because we re-use the ring-0
423	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
424	* because it's identical (we trap all IO accesses).
425	*
426	* This one is just used for caching the IOPM from guest physical memory in
427	* case the guest hypervisor allows direct access to some IO ports.
428	*
429	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
430	* really need to even be page aligned.
431	*
432	* Also, couldn't we just access the guest page directly when we need to,
433	* or do we have to use a cached copy of it? */
434	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
435
436	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
437	uint64_t uMsrHSavePa;
438	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
439	RTGCPHYS GCPhysVmcb;
440	/** 0xa010 - Guest's host-state save area. */
441	SVMHOSTSTATE HostState;
442	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
443	* executed. */
444	uint64_t uPrevPauseTick;
445	/** 0xa0d0 - Pause filter count. */
446	uint16_t cPauseFilter;
447	/** 0xa0d2 - Pause filter threshold. */
448	uint16_t cPauseFilterThreshold;
449	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
450	bool fInterceptEvents;
451	/** 0xa0d5 - Padding. */
452	bool afPadding[3];
453	} svm;
454
455	struct
456	{
457	/** 0x4000 - The current VMCS. */
458	VMXVVMCS Vmcs;
459	/** 0X5000 - The shadow VMCS. */
460	VMXVVMCS ShadowVmcs;
461	/** 0x6000 - The VMREAD bitmap.
462	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
463	* access the guest memory directly as needed? */
464	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
465	/** 0x7000 - The VMWRITE bitmap.
466	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
467	* access the guest memory directly as needed? */
468	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
469	/** 0x8000 - The VM-entry MSR-load area. */
470	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
471	/** 0xa000 - The VM-exit MSR-store area. */
472	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
473	/** 0xc000 - The VM-exit MSR-load area. */
474	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
475	/** 0xe000 - The MSR permission bitmap.
476	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
477	* access the guest memory directly as needed? */
478	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
479	/** 0xf000 - The I/O permission bitmap.
480	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
481	* access the guest memory directly as needed? */
482	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
483
484	/** 0x11000 - Guest physical address of the VMXON region. */
485	RTGCPHYS GCPhysVmxon;
486	/** 0x11008 - Guest physical address of the current VMCS pointer. */
487	RTGCPHYS GCPhysVmcs;
488	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
489	RTGCPHYS GCPhysShadowVmcs;
490	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
491	VMXVDIAG enmDiag;
492	/** 0x1101c - VMX abort reason. */
493	VMXABORT enmAbort;
494	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
495	* (mainly used for info. that's not part of the VMCS). */
496	uint64_t uDiagAux;
497	/** 0x11028 - VMX abort auxiliary info. */
498	uint32_t uAbortAux;
499	/** 0x1102c - Whether the guest is in VMX root mode. */
500	bool fInVmxRootMode;
501	/** 0x1102d - Whether the guest is in VMX non-root mode. */
502	bool fInVmxNonRootMode;
503	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
504	bool fInterceptEvents;
505	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
506	* non-root mode before execution of IRET. */
507	bool fNmiUnblockingIret;
508	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
509	* considered to be the first in a loop. */
510	uint64_t uFirstPauseLoopTick;
511	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
512	uint64_t uPrevPauseTick;
513	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
514	* timer). */
515	uint64_t uEntryTick;
516	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
517	uint16_t offVirtApicWrite;
518	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
519	bool fVirtNmiBlocking;
520	/** 0x1104b - Padding. */
521	uint8_t abPadding0[5];
522	/** 0x11050 - Guest VMX MSRs. */
523	VMXMSRS Msrs;
524	} vmx;
525	} CPUM_UNION_NM(s);
526
527	/** 0x11130 - Hardware virtualization type currently in use. */
528	CPUMHWVIRT enmHwvirt;
529	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
530	bool fGif;
531	/** 0x11135 - Padding. */
532	bool afPadding0[3];
533	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
534	* saved while running the nested-guest. */
535	uint32_t fSavedInhibit;
536	/** 0x1113c - Pad to 64 byte boundary. */
537	uint8_t abPadding1[4];
538	} hwvirt;
539	} CPUMCTX;
540	#pragma pack()
541
542	#ifndef VBOX_FOR_DTRACE_LIB
543	AssertCompileSizeAlignment(CPUMCTX, 64);
544	AssertCompileSizeAlignment(CPUMCTX, 32);
545	AssertCompileSizeAlignment(CPUMCTX, 16);
546	AssertCompileSizeAlignment(CPUMCTX, 8);
547	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
548	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
549	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
550	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
551	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
552	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
553	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
554	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
555	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
556	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
557	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
558	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
559	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
560	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
561	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
562	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
563	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
564	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
565	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
566	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
567	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
568	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
569	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
570	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
571	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
572	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
573	AssertCompileMemberOffset(CPUMCTX, fInhibit, 0x0150);
574	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
575	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
576	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
577	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
578	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
579	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
580	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
581	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
582	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
583	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
584	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
585	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
586	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
587	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
588	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
589	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
590	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
591	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
592	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
593	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
594	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
595	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
596	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
597	/* Only do spot checks for hwvirt */
598	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
599	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
600	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
601	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
602	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
603	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
604	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
605	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
606	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
607	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
608	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
609	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
610	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
611	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
612	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
613	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
614	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
615	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
616	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
617	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
618	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
619	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
620	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
621	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
622	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
623	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
624	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
625	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
626	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
627	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
628	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
629	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
630	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
631	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
632	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
633	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
634	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
635	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
636	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
637	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
638	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
639	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
640	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
641	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
642	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
643	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
644	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
645	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
646	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
647	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
648	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
649	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
650	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
651	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
652	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
653	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
654	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
655	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
656	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
657	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
658	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
659	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
660	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
661	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
662	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
663	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
664	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
665	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
666	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
667	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
668	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
669	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
670	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
671	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
672	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
673	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
674	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
675	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
676	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
677	# ifndef _MSC_VER
678	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
679	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
680	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
681	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
682	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
683	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
684	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
685	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
686	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
687	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
688	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
689	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
690	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
691	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
692	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
693	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
694	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
695	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
696	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
697	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
698	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
699	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
700	# endif
701
702
703	/**
704	* Calculates the pointer to the given extended state component.
705	*
706	* @returns Pointer of type @a a_PtrType
707	* @param a_pCtx Pointer to the context.
708	* @param a_iCompBit The extended state component bit number. This bit
709	* must be set in CPUMCTX::fXStateMask.
710	* @param a_PtrType The pointer type of the extended state component.
711	*
712	*/
713	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
714	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
715	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
716	{ \
717	AssertCompile((a_iCompBit) < 64U); \
718	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
719	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
720	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
721	}(a_pCtx))
722	#elif defined(VBOX_STRICT) && defined(__GNUC__)
723	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
724	__extension__ (\
725	{ \
726	AssertCompile((a_iCompBit) < 64U); \
727	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
728	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
729	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
730	})
731	#else
732	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
733	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
734	#endif
735
736	/**
737	* Gets the first selector register of a CPUMCTX.
738	*
739	* Use this with X86_SREG_COUNT to loop thru the selector registers.
740	*/
741	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
742
743	#endif /* !VBOX_FOR_DTRACE_LIB */
744
745
746	/** @name CPUMCTX_EXTRN_XXX
747	* Used for parts of the CPUM state that is externalized and needs fetching
748	* before use.
749	*
750	* @{ */
751	/** External state keeper: Invalid. */
752	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
753	/** External state keeper: HM. */
754	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
755	/** External state keeper: NEM. */
756	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
757	/** External state keeper: REM. */
758	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
759	/** External state keeper mask. */
760	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
761
762	/** The RIP register value is kept externally. */
763	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
764	/** The RFLAGS register values are kept externally. */
765	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
766
767	/** The RAX register value is kept externally. */
768	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
769	/** The RCX register value is kept externally. */
770	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
771	/** The RDX register value is kept externally. */
772	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
773	/** The RBX register value is kept externally. */
774	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
775	/** The RSP register value is kept externally. */
776	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
777	/** The RBP register value is kept externally. */
778	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
779	/** The RSI register value is kept externally. */
780	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
781	/** The RDI register value is kept externally. */
782	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
783	/** The R8 thru R15 register values are kept externally. */
784	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
785	/** General purpose registers mask. */
786	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
787
788	/** The ES register values are kept externally. */
789	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
790	/** The CS register values are kept externally. */
791	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
792	/** The SS register values are kept externally. */
793	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
794	/** The DS register values are kept externally. */
795	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
796	/** The FS register values are kept externally. */
797	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
798	/** The GS register values are kept externally. */
799	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
800	/** Segment registers (includes CS). */
801	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
802	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
803	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
804	#ifndef VBOX_FOR_DTRACE_LIB
805	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
806	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
807	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
808	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
809	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
810	#endif
811
812	/** The GDTR register values are kept externally. */
813	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
814	/** The IDTR register values are kept externally. */
815	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
816	/** The LDTR register values are kept externally. */
817	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
818	/** The TR register values are kept externally. */
819	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
820	/** Table register mask. */
821	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
822
823	/** The CR0 register value is kept externally. */
824	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
825	/** The CR2 register value is kept externally. */
826	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
827	/** The CR3 register value is kept externally. */
828	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
829	/** The CR4 register value is kept externally. */
830	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
831	/** Control register mask. */
832	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
833	/** The TPR/CR8 register value is kept externally. */
834	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
835	/** The EFER register value is kept externally. */
836	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
837
838	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
839	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
840	/** The DR6 register value is kept externally. */
841	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
842	/** The DR7 register value is kept externally. */
843	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
844	/** Debug register mask. */
845	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
846
847	/** The XSAVE_C_X87 state is kept externally. */
848	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
849	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
850	* XSAVE_C_OPMASK state is kept externally. */
851	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
852	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
853	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
854	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
855	/** The state of XCR0 and XCR1 register values are kept externally. */
856	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
857
858
859	/** The KERNEL GS BASE MSR value is kept externally. */
860	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
861	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
862	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
863	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
864	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
865	/** The TSC_AUX MSR is kept externally. */
866	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
867	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
868	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
869	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
870	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
871
872	/** Mask of all the MSRs. */
873	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
874	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
875
876	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
877	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
878
879	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
880	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
881	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
882	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
883
884	/** Mask of bits the keepers can use for state tracking. */
885	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
886
887	/** NEM/Win: Event injection (known was interruption) pending state. */
888	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
889	/** NEM/Win: Mask. */
890	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
891
892	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
893	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
894	/** HM/SVM: Mask. */
895	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
896
897	/** All CPUM state bits, not including keeper specific ones. */
898	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
899	/** All CPUM state bits, including keeper specific ones. */
900	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
901	/** @} */
902
903
904	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
905	* @{ */
906	/** Interrupt shadow following MOV SS or POP SS.
907	*
908	* When this in effect, both maskable and non-maskable interrupts are blocked
909	* from delivery for one instruction. Same for certain debug exceptions too,
910	* unlike the STI variant.
911	*
912	* It is implementation specific whether a sequence of two or more of these
913	* instructions will have any effect on the instruction following the last one
914	* of them. */
915	#define CPUMCTX_INHIBIT_SHADOW_SS UINT8_C(0x01)
916	/** Interrupt shadow following STI.
917	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
918	#define CPUMCTX_INHIBIT_SHADOW_STI UINT8_C(0x02)
919	/** Mask combining STI and SS shadowing. */
920	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
921
922	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
923	*
924	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
925	* "The processor also invokes certain hardware conditions to ensure that no
926	* other interrupts, including NMI interrupts, are received until the NMI
927	* handler has completed executing." This flag indicates that these
928	* conditions are currently active. */
929	#define CPUMCTX_INHIBIT_NMI UINT8_C(0x04)
930	/** @} */
931
932
933	/**
934	* Additional guest MSRs (i.e. not part of the CPU context structure).
935	*
936	* @remarks Never change the order here because of the saved stated! The size
937	* can in theory be changed, but keep older VBox versions in mind.
938	*/
939	typedef union CPUMCTXMSRS
940	{
941	struct
942	{
943	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
944	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
945	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
946	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
947	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
948	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
949	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
950	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
951	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
952	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
953	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
954	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
955	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
956	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
957	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
958	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
959	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
960	} msr;
961	uint64_t au64[64];
962	} CPUMCTXMSRS;
963	/** Pointer to the guest MSR state. */
964	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
965	/** Pointer to the const guest MSR state. */
966	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
967
968	/** @} */
969
970	RT_C_DECLS_END
971
972	#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
973

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 97213

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