cpumctx.h@ 97705

Last change on this file since 97705 was 97705, checked in by vboxsync, 2 years ago
VMM/IEM,DBGF,CPUM: Do debugger I/O breakpoints via the internal EFLAGS bits too. Seems we might need two bits, so had to shift the internal bits down from 24 to 22. bugref:9898
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1	/** @file
2	* CPUM - CPU Monitor(/ Manager), Context Structures.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_cpumctx_h
37	#define VBOX_INCLUDED_vmm_cpumctx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# include <iprt/x86.h>
44	# include <VBox/types.h>
45	# include <VBox/vmm/hm_svm.h>
46	# include <VBox/vmm/hm_vmx.h>
47	#else
48	# pragma D depends_on library x86.d
49	#endif
50
51
52	RT_C_DECLS_BEGIN
53
54	/** @defgroup grp_cpum_ctx The CPUM Context Structures
55	* @ingroup grp_cpum
56	* @{
57	*/
58
59	/**
60	* Selector hidden registers.
61	*/
62	typedef struct CPUMSELREG
63	{
64	/** The selector register. */
65	RTSEL Sel;
66	/** Padding, don't use. */
67	RTSEL PaddingSel;
68	/** The selector which info resides in u64Base, u32Limit and Attr, provided
69	* that CPUMSELREG_FLAGS_VALID is set. */
70	RTSEL ValidSel;
71	/** Flags, see CPUMSELREG_FLAGS_XXX. */
72	uint16_t fFlags;
73
74	/** Base register.
75	*
76	* Long mode remarks:
77	* - Unused in long mode for CS, DS, ES, SS
78	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
79	* - 64 bits for TR & LDTR
80	*/
81	uint64_t u64Base;
82	/** Limit (expanded). */
83	uint32_t u32Limit;
84	/** Flags.
85	* This is the high 32-bit word of the descriptor entry.
86	* Only the flags, dpl and type are used. */
87	X86DESCATTR Attr;
88	} CPUMSELREG;
89	#ifndef VBOX_FOR_DTRACE_LIB
90	AssertCompileSize(CPUMSELREG, 24);
91	#endif
92
93	/** @name CPUMSELREG_FLAGS_XXX - CPUMSELREG::fFlags values.
94	* @{ */
95	#define CPUMSELREG_FLAGS_VALID UINT16_C(0x0001)
96	#define CPUMSELREG_FLAGS_STALE UINT16_C(0x0002)
97	#define CPUMSELREG_FLAGS_VALID_MASK UINT16_C(0x0003)
98	/** @} */
99
100	/** Checks if the hidden parts of the selector register are valid. */
101	#define CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSelReg) \
102	( ((a_pSelReg)->fFlags & CPUMSELREG_FLAGS_VALID) \
103	&& (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
104
105	/** Old type used for the hidden register part.
106	* @deprecated */
107	typedef CPUMSELREG CPUMSELREGHID;
108
109	/**
110	* The sysenter register set.
111	*/
112	typedef struct CPUMSYSENTER
113	{
114	/** Ring 0 cs.
115	* This value + 8 is the Ring 0 ss.
116	* This value + 16 is the Ring 3 cs.
117	* This value + 24 is the Ring 3 ss.
118	*/
119	uint64_t cs;
120	/** Ring 0 eip. */
121	uint64_t eip;
122	/** Ring 0 esp. */
123	uint64_t esp;
124	} CPUMSYSENTER;
125
126	/** @def CPUM_UNION_NM
127	* For compilers (like DTrace) that does not grok nameless unions, we have a
128	* little hack to make them palatable.
129	*/
130	/** @def CPUM_STRUCT_NM
131	* For compilers (like DTrace) that does not grok nameless structs (it is
132	* non-standard C++), we have a little hack to make them palatable.
133	*/
134	#ifdef VBOX_FOR_DTRACE_LIB
135	# define CPUM_UNION_NM(a_Nm) a_Nm
136	# define CPUM_STRUCT_NM(a_Nm) a_Nm
137	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
138	# define CPUM_UNION_NM(a_Nm) a_Nm
139	# define CPUM_STRUCT_NM(a_Nm) a_Nm
140	#else
141	# define CPUM_UNION_NM(a_Nm)
142	# define CPUM_STRUCT_NM(a_Nm)
143	#endif
144	/** @def CPUM_UNION_STRUCT_NM
145	* Combines CPUM_UNION_NM and CPUM_STRUCT_NM to avoid hitting the right side of
146	* the screen in the compile time assertions.
147	*/
148	#define CPUM_UNION_STRUCT_NM(a_UnionNm, a_StructNm) CPUM_UNION_NM(a_UnionNm .) CPUM_STRUCT_NM(a_StructNm)
149
150	/** A general register (union). */
151	typedef union CPUMCTXGREG
152	{
153	/** Natural unsigned integer view. */
154	uint64_t u;
155	/** 64-bit view. */
156	uint64_t u64;
157	/** 32-bit view. */
158	uint32_t u32;
159	/** 16-bit view. */
160	uint16_t u16;
161	/** 8-bit view. */
162	uint8_t u8;
163	/** 8-bit low/high view. */
164	RT_GCC_EXTENSION struct
165	{
166	/** Low byte (al, cl, dl, bl, ++). */
167	uint8_t bLo;
168	/** High byte in the first word - ah, ch, dh, bh. */
169	uint8_t bHi;
170	} CPUM_STRUCT_NM(s);
171	} CPUMCTXGREG;
172	#ifndef VBOX_FOR_DTRACE_LIB
173	AssertCompileSize(CPUMCTXGREG, 8);
174	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bLo, 0);
175	AssertCompileMemberOffset(CPUMCTXGREG, CPUM_STRUCT_NM(s.) bHi, 1);
176	#endif
177
178
179
180	/**
181	* SVM Host-state area (Nested Hw.virt - VirtualBox's layout).
182	*
183	* @warning Exercise caution while modifying the layout of this struct. It's
184	* part of VM saved states.
185	*/
186	#pragma pack(1)
187	typedef struct SVMHOSTSTATE
188	{
189	uint64_t uEferMsr;
190	uint64_t uCr0;
191	uint64_t uCr4;
192	uint64_t uCr3;
193	uint64_t uRip;
194	uint64_t uRsp;
195	uint64_t uRax;
196	X86RFLAGS rflags;
197	CPUMSELREG es;
198	CPUMSELREG cs;
199	CPUMSELREG ss;
200	CPUMSELREG ds;
201	VBOXGDTR gdtr;
202	VBOXIDTR idtr;
203	uint8_t abPadding[4];
204	} SVMHOSTSTATE;
205	#pragma pack()
206	/** Pointer to the SVMHOSTSTATE structure. */
207	typedef SVMHOSTSTATE *PSVMHOSTSTATE;
208	/** Pointer to a const SVMHOSTSTATE structure. */
209	typedef const SVMHOSTSTATE *PCSVMHOSTSTATE;
210	#ifndef VBOX_FOR_DTRACE_LIB
211	AssertCompileSizeAlignment(SVMHOSTSTATE, 8);
212	AssertCompileSize(SVMHOSTSTATE, 184);
213	#endif
214
215
216	/**
217	* CPU hardware virtualization types.
218	*/
219	typedef enum
220	{
221	CPUMHWVIRT_NONE = 0,
222	CPUMHWVIRT_VMX,
223	CPUMHWVIRT_SVM,
224	CPUMHWVIRT_32BIT_HACK = 0x7fffffff
225	} CPUMHWVIRT;
226	#ifndef VBOX_FOR_DTRACE_LIB
227	AssertCompileSize(CPUMHWVIRT, 4);
228	#endif
229
230	/** Number of EFLAGS bits we put aside for the hardware EFLAGS, with the bits
231	* above this we use for storing internal state not visible to the guest.
232	*
233	* Using a value less than 32 here means some code bloat when loading and
234	* fetching the hardware EFLAGS value. Comparing VMMR0.r0 text size when
235	* compiling release build using gcc 11.3.1 on linux:
236	* - 32 bits: 2475709 bytes
237	* - 24 bits: 2482069 bytes; +6360 bytes.
238	* - 22 bits: 2482261 bytes; +6552 bytes.
239	* Same for windows (virtual size of .text):
240	* - 32 bits: 1498502 bytes
241	* - 24 bits: 1502278 bytes; +3776 bytes.
242	* - 22 bits: 1502198 bytes; +3696 bytes.
243	*
244	* In addition we pass pointer the 32-bit EFLAGS to a number of IEM assembly
245	* functions, so it would be safer to not store anything in the lower 32 bits.
246	* OTOH, we'd sooner discover buggy assembly code by doing so, as we've had one
247	* example of accidental EFLAGS trashing by these functions already.
248	*
249	* It would be more efficient for IEM to store the interrupt shadow bit (and
250	* anything else that needs to be cleared at the same time) in the 30:22 bit
251	* range, because that would allow using a simple AND imm32 instruction on x86
252	* and a MOVN imm16,16 instruction to load the constant on ARM64 (assuming the
253	* other flag needing clearing is RF (bit 16)). Putting it in the 63:32 range
254	* means we that on x86 we'll either use a memory variant of AND or require a
255	* separate load instruction for the immediate, whereas on ARM we'll need more
256	* instructions to construct the immediate value.
257	*
258	* Comparing the instruction exit thruput via the bs2-test-1 testcase, there
259	* seems to be little difference between 32 and 24 here (best results out of 9
260	* runs on Linux/VT-x). So, unless the results are really wrong and there is
261	* clear drop in thruput, it would on the whole make the most sense to use 24
262	* here.
263	*
264	* Update: We need more than 8 bits because of DBGF, so using 22 now.
265	*/
266	#define CPUMX86EFLAGS_HW_BITS 22
267	/** Mask for the hardware EFLAGS bits, 64-bit version. */
268	#define CPUMX86EFLAGS_HW_MASK_64 (RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - UINT64_C(1))
269	/** Mask for the hardware EFLAGS bits, 32-bit version. */
270	#if CPUMX86EFLAGS_HW_BITS == 32
271	# define CPUMX86EFLAGS_HW_MASK_32 UINT32_MAX
272	#elif CPUMX86EFLAGS_HW_BITS < 32 && CPUMX86EFLAGS_HW_BITS >= 22
273	# define CPUMX86EFLAGS_HW_MASK_32 (RT_BIT_32(CPUMX86EFLAGS_HW_BITS) - UINT32_C(1))
274	#else
275	# error "Misconfigured CPUMX86EFLAGS_HW_BITS value!"
276	#endif
277
278	/** Mask of internal flags kept with EFLAGS, 64-bit version.
279	* Bits 22-24 are taken by CPUMCTX_INHIBIT_SHADOW_SS, CPUMCTX_INHIBIT_SHADOW_STI
280	* and CPUMCTX_INHIBIT_NMI, bits 25-28 are for CPUMCTX_DBG_HIT_DRX_MASK, and
281	* bits 29-30 are for DBGF events and breakpoints.
282	*
283	* @todo The two DBGF bits could be merged. The NMI inhibiting could move to
284	* bit 32 or higher as it isn't automatically cleared on instruction
285	* completion (except for iret).
286	*/
287	#define CPUMX86EFLAGS_INT_MASK_64 UINT64_C(0x00000000ffc00000)
288	/** Mask of internal flags kept with EFLAGS, 32-bit version. */
289	#define CPUMX86EFLAGS_INT_MASK_32 UINT32_C(0xffc00000)
290
291
292	/**
293	* CPUM EFLAGS.
294	*
295	* This differs from X86EFLAGS in that we could use bits 31:22 for internal
296	* purposes, see CPUMX86EFLAGS_HW_BITS.
297	*/
298	typedef union CPUMX86EFLAGS
299	{
300	/** The full unsigned view, both hardware and VBox bits. */
301	uint32_t uBoth;
302	/** The plain unsigned view of the hardware bits. */
303	#if CPUMX86EFLAGS_HW_BITS == 32
304	uint32_t u;
305	#else
306	uint32_t u : CPUMX86EFLAGS_HW_BITS;
307	#endif
308	#ifndef VBOX_FOR_DTRACE_LIB
309	/** The bitfield view. */
310	X86EFLAGSBITS Bits;
311	#endif
312	} CPUMX86EFLAGS;
313	/** Pointer to CPUM EFLAGS. */
314	typedef CPUMX86EFLAGS *PCPUMX86EFLAGS;
315	/** Pointer to const CPUM EFLAGS. */
316	typedef const CPUMX86EFLAGS *PCCPUMX86EFLAGS;
317
318	/**
319	* CPUM RFLAGS.
320	*
321	* This differs from X86EFLAGS in that we use could be using bits 63:22 for
322	* internal purposes, see CPUMX86EFLAGS_HW_BITS.
323	*/
324	typedef union CPUMX86RFLAGS
325	{
326	/** The full unsigned view, both hardware and VBox bits. */
327	uint64_t uBoth;
328	/** The plain unsigned view of the hardware bits. */
329	#if CPUMX86EFLAGS_HW_BITS == 32
330	uint32_t u;
331	#else
332	uint32_t u : CPUMX86EFLAGS_HW_BITS;
333	#endif
334	#ifndef VBOX_FOR_DTRACE_LIB
335	/** The bitfield view. */
336	X86EFLAGSBITS Bits;
337	#endif
338	} CPUMX86RFLAGS;
339	/** Pointer to CPUM RFLAGS. */
340	typedef CPUMX86RFLAGS *PCPUMX86RFLAGS;
341	/** Pointer to const CPUM RFLAGS. */
342	typedef const CPUMX86RFLAGS *PCCPUMX86RFLAGS;
343
344
345	/**
346	* CPU context.
347	*/
348	#pragma pack(1) /* for VBOXIDTR / VBOXGDTR. */
349	typedef struct CPUMCTX
350	{
351	/** General purpose registers. */
352	union /* no tag! */
353	{
354	/** The general purpose register array view, indexed by X86_GREG_XXX. */
355	CPUMCTXGREG aGRegs[16];
356
357	/** 64-bit general purpose register view. */
358	RT_GCC_EXTENSION struct /* no tag! */
359	{
360	uint64_t rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
361	} CPUM_STRUCT_NM(qw);
362	/** 64-bit general purpose register view. */
363	RT_GCC_EXTENSION struct /* no tag! */
364	{
365	uint64_t r0, r1, r2, r3, r4, r5, r6, r7;
366	} CPUM_STRUCT_NM(qw2);
367	/** 32-bit general purpose register view. */
368	RT_GCC_EXTENSION struct /* no tag! */
369	{
370	uint32_t eax, u32Pad00, ecx, u32Pad01, edx, u32Pad02, ebx, u32Pad03,
371	esp, u32Pad04, ebp, u32Pad05, esi, u32Pad06, edi, u32Pad07,
372	r8d, u32Pad08, r9d, u32Pad09, r10d, u32Pad10, r11d, u32Pad11,
373	r12d, u32Pad12, r13d, u32Pad13, r14d, u32Pad14, r15d, u32Pad15;
374	} CPUM_STRUCT_NM(dw);
375	/** 16-bit general purpose register view. */
376	RT_GCC_EXTENSION struct /* no tag! */
377	{
378	uint16_t ax, au16Pad00[3], cx, au16Pad01[3], dx, au16Pad02[3], bx, au16Pad03[3],
379	sp, au16Pad04[3], bp, au16Pad05[3], si, au16Pad06[3], di, au16Pad07[3],
380	r8w, au16Pad08[3], r9w, au16Pad09[3], r10w, au16Pad10[3], r11w, au16Pad11[3],
381	r12w, au16Pad12[3], r13w, au16Pad13[3], r14w, au16Pad14[3], r15w, au16Pad15[3];
382	} CPUM_STRUCT_NM(w);
383	RT_GCC_EXTENSION struct /* no tag! */
384	{
385	uint8_t al, ah, abPad00[6], cl, ch, abPad01[6], dl, dh, abPad02[6], bl, bh, abPad03[6],
386	spl, abPad04[7], bpl, abPad05[7], sil, abPad06[7], dil, abPad07[7],
387	r8l, abPad08[7], r9l, abPad09[7], r10l, abPad10[7], r11l, abPad11[7],
388	r12l, abPad12[7], r13l, abPad13[7], r14l, abPad14[7], r15l, abPad15[7];
389	} CPUM_STRUCT_NM(b);
390	} CPUM_UNION_NM(g);
391
392	/** Segment registers. */
393	union /* no tag! */
394	{
395	/** The segment register array view, indexed by X86_SREG_XXX. */
396	CPUMSELREG aSRegs[6];
397	/** The named segment register view. */
398	RT_GCC_EXTENSION struct /* no tag! */
399	{
400	CPUMSELREG es, cs, ss, ds, fs, gs;
401	} CPUM_STRUCT_NM(n);
402	} CPUM_UNION_NM(s);
403
404	/** The task register.
405	* Only the guest context uses all the members. */
406	CPUMSELREG ldtr;
407	/** The task register.
408	* Only the guest context uses all the members. */
409	CPUMSELREG tr;
410
411	/** The program counter. */
412	union
413	{
414	uint16_t ip;
415	uint32_t eip;
416	uint64_t rip;
417	} CPUM_UNION_NM(rip);
418
419	/** The flags register. */
420	union
421	{
422	CPUMX86EFLAGS eflags;
423	CPUMX86RFLAGS rflags;
424	} CPUM_UNION_NM(rflags);
425
426	/** 0x150 - Externalized state tracker, CPUMCTX_EXTRN_XXX. */
427	uint64_t fExtrn;
428
429	/** The RIP value an interrupt shadow is/was valid for. */
430	uint64_t uRipInhibitInt;
431
432	/** @name Control registers.
433	* @{ */
434	uint64_t cr0;
435	uint64_t cr2;
436	uint64_t cr3;
437	uint64_t cr4;
438	/** @} */
439
440	/** Debug registers.
441	* @remarks DR4 and DR5 should not be used since they are aliases for
442	* DR6 and DR7 respectively on both AMD and Intel CPUs.
443	* @remarks DR8-15 are currently not supported by AMD or Intel, so
444	* neither do we.
445	*/
446	uint64_t dr[8];
447
448	/** Padding before the structure so the 64-bit member is correctly aligned.
449	* @todo fix this structure! */
450	uint16_t gdtrPadding[3];
451	/** Global Descriptor Table register. */
452	VBOXGDTR gdtr;
453
454	/** Padding before the structure so the 64-bit member is correctly aligned.
455	* @todo fix this structure! */
456	uint16_t idtrPadding[3];
457	/** Interrupt Descriptor Table register. */
458	VBOXIDTR idtr;
459
460	/** The sysenter msr registers.
461	* This member is not used by the hypervisor context. */
462	CPUMSYSENTER SysEnter;
463
464	/** @name System MSRs.
465	* @{ */
466	uint64_t msrEFER; /*< @todo move EFER up to the crX registers for better cacheline mojo /
467	uint64_t msrSTAR; /*< Legacy syscall eip, cs & ss. /
468	uint64_t msrPAT; /*< Page attribute table. /
469	uint64_t msrLSTAR; /*< 64 bits mode syscall rip. /
470	uint64_t msrCSTAR; /*< Compatibility mode syscall rip. /
471	uint64_t msrSFMASK; /*< syscall flag mask. /
472	uint64_t msrKERNELGSBASE; /*< swapgs exchange value. /
473	/** @} */
474
475	uint64_t au64Unused[2];
476
477	/** 0x240 - PAE PDPTEs. */
478	X86PDPE aPaePdpes[4];
479
480	/** 0x260 - The XCR0..XCR1 registers. */
481	uint64_t aXcr[2];
482	/** 0x270 - The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
483	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
484	uint64_t fXStateMask;
485	/** 0x278 - Mirror of CPUMCPU::fUseFlags[CPUM_USED_FPU_GUEST]. */
486	bool fUsedFpuGuest;
487	uint8_t afUnused[7];
488
489	/* ---- Start of members not zeroed at reset. ---- */
490
491	/** 0x280 - State component offsets into pXState, UINT16_MAX if not present.
492	* @note Everything before this member will be memset to zero during reset. */
493	uint16_t aoffXState[64];
494	/** 0x300 - The extended state (FPU/SSE/AVX/AVX-2/XXXX).
495	* Aligned on 256 byte boundrary (min req is currently 64 bytes). */
496	union /* no tag */
497	{
498	X86XSAVEAREA XState;
499	/** Byte view for simple indexing and space allocation. */
500	uint8_t abXState[0x4000 - 0x300];
501	} CPUM_UNION_NM(u);
502
503	/** 0x4000 - Hardware virtualization state.
504	* @note This is page aligned, so an full page member comes first in the
505	* substructures. */
506	struct
507	{
508	union /* no tag! */
509	{
510	struct
511	{
512	/** 0x4000 - Cache of the nested-guest VMCB. */
513	SVMVMCB Vmcb;
514	/** 0x5000 - The MSRPM (MSR Permission bitmap).
515	*
516	* This need not be physically contiguous pages because we use the one from
517	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
518	* This one is just used for caching the bitmap from guest physical memory.
519	*
520	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
521	* really need to even be page aligned.
522	*
523	* Also, couldn't we just access the guest page directly when we need to,
524	* or do we have to use a cached copy of it? */
525	uint8_t abMsrBitmap[SVM_MSRPM_PAGES * X86_PAGE_SIZE];
526	/** 0x7000 - The IOPM (IO Permission bitmap).
527	*
528	* This need not be physically contiguous pages because we re-use the ring-0
529	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
530	* because it's identical (we trap all IO accesses).
531	*
532	* This one is just used for caching the IOPM from guest physical memory in
533	* case the guest hypervisor allows direct access to some IO ports.
534	*
535	* @todo r=bird: This is not used directly by AMD-V hardware, so it doesn't
536	* really need to even be page aligned.
537	*
538	* Also, couldn't we just access the guest page directly when we need to,
539	* or do we have to use a cached copy of it? */
540	uint8_t abIoBitmap[SVM_IOPM_PAGES * X86_PAGE_SIZE];
541
542	/** 0xa000 - MSR holding physical address of the Guest's Host-state. */
543	uint64_t uMsrHSavePa;
544	/** 0xa008 - Guest physical address of the nested-guest VMCB. */
545	RTGCPHYS GCPhysVmcb;
546	/** 0xa010 - Guest's host-state save area. */
547	SVMHOSTSTATE HostState;
548	/** 0xa0c8 - Guest TSC time-stamp of when the previous PAUSE instr. was
549	* executed. */
550	uint64_t uPrevPauseTick;
551	/** 0xa0d0 - Pause filter count. */
552	uint16_t cPauseFilter;
553	/** 0xa0d2 - Pause filter threshold. */
554	uint16_t cPauseFilterThreshold;
555	/** 0xa0d4 - Whether the injected event is subject to event intercepts. */
556	bool fInterceptEvents;
557	/** 0xa0d5 - Padding. */
558	bool afPadding[3];
559	} svm;
560
561	struct
562	{
563	/** 0x4000 - The current VMCS. */
564	VMXVVMCS Vmcs;
565	/** 0X5000 - The shadow VMCS. */
566	VMXVVMCS ShadowVmcs;
567	/** 0x6000 - The VMREAD bitmap.
568	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
569	* access the guest memory directly as needed? */
570	uint8_t abVmreadBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
571	/** 0x7000 - The VMWRITE bitmap.
572	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
573	* access the guest memory directly as needed? */
574	uint8_t abVmwriteBitmap[VMX_V_VMREAD_VMWRITE_BITMAP_SIZE];
575	/** 0x8000 - The VM-entry MSR-load area. */
576	VMXAUTOMSR aEntryMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
577	/** 0xa000 - The VM-exit MSR-store area. */
578	VMXAUTOMSR aExitMsrStoreArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
579	/** 0xc000 - The VM-exit MSR-load area. */
580	VMXAUTOMSR aExitMsrLoadArea[VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR)];
581	/** 0xe000 - The MSR permission bitmap.
582	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
583	* access the guest memory directly as needed? */
584	uint8_t abMsrBitmap[VMX_V_MSR_BITMAP_SIZE];
585	/** 0xf000 - The I/O permission bitmap.
586	* @todo r=bird: Do we really need to keep copies for these? Couldn't we just
587	* access the guest memory directly as needed? */
588	uint8_t abIoBitmap[VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE];
589
590	/** 0x11000 - Guest physical address of the VMXON region. */
591	RTGCPHYS GCPhysVmxon;
592	/** 0x11008 - Guest physical address of the current VMCS pointer. */
593	RTGCPHYS GCPhysVmcs;
594	/** 0x11010 - Guest physical address of the shadow VMCS pointer. */
595	RTGCPHYS GCPhysShadowVmcs;
596	/** 0x11018 - Last emulated VMX instruction/VM-exit diagnostic. */
597	VMXVDIAG enmDiag;
598	/** 0x1101c - VMX abort reason. */
599	VMXABORT enmAbort;
600	/** 0x11020 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info.
601	* (mainly used for info. that's not part of the VMCS). */
602	uint64_t uDiagAux;
603	/** 0x11028 - VMX abort auxiliary info. */
604	uint32_t uAbortAux;
605	/** 0x1102c - Whether the guest is in VMX root mode. */
606	bool fInVmxRootMode;
607	/** 0x1102d - Whether the guest is in VMX non-root mode. */
608	bool fInVmxNonRootMode;
609	/** 0x1102e - Whether the injected events are subjected to event intercepts. */
610	bool fInterceptEvents;
611	/** 0x1102f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX
612	* non-root mode before execution of IRET. */
613	bool fNmiUnblockingIret;
614	/** 0x11030 - Guest TSC timestamp of the first PAUSE instruction that is
615	* considered to be the first in a loop. */
616	uint64_t uFirstPauseLoopTick;
617	/** 0x11038 - Guest TSC timestamp of the previous PAUSE instruction. */
618	uint64_t uPrevPauseTick;
619	/** 0x11040 - Guest TSC timestamp of VM-entry (used for VMX-preemption
620	* timer). */
621	uint64_t uEntryTick;
622	/** 0x11048 - Virtual-APIC write offset (until trap-like VM-exit). */
623	uint16_t offVirtApicWrite;
624	/** 0x1104a - Whether virtual-NMI blocking is in effect. */
625	bool fVirtNmiBlocking;
626	/** 0x1104b - Padding. */
627	uint8_t abPadding0[5];
628	/** 0x11050 - Guest VMX MSRs. */
629	VMXMSRS Msrs;
630	} vmx;
631	} CPUM_UNION_NM(s);
632
633	/** 0x11130 - Hardware virtualization type currently in use. */
634	CPUMHWVIRT enmHwvirt;
635	/** 0x11134 - Global interrupt flag - AMD only (always true on Intel). */
636	bool fGif;
637	/** 0x11135 - Padding. */
638	bool afPadding0[3];
639	/** 0x11138 - A subset of guest inhibit flags (CPUMCTX_INHIBIT_XXX) that are
640	* saved while running the nested-guest. */
641	uint32_t fSavedInhibit;
642	/** 0x1113c - Pad to 64 byte boundary. */
643	uint8_t abPadding1[4];
644	} hwvirt;
645	} CPUMCTX;
646	#pragma pack()
647
648	#ifndef VBOX_FOR_DTRACE_LIB
649	AssertCompileSizeAlignment(CPUMCTX, 64);
650	AssertCompileSizeAlignment(CPUMCTX, 32);
651	AssertCompileSizeAlignment(CPUMCTX, 16);
652	AssertCompileSizeAlignment(CPUMCTX, 8);
653	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rax, 0x0000);
654	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rcx, 0x0008);
655	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdx, 0x0010);
656	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbx, 0x0018);
657	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsp, 0x0020);
658	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rbp, 0x0028);
659	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rsi, 0x0030);
660	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) rdi, 0x0038);
661	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r8, 0x0040);
662	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r9, 0x0048);
663	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r10, 0x0050);
664	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r11, 0x0058);
665	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r12, 0x0060);
666	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r13, 0x0068);
667	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r14, 0x0070);
668	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(g.) CPUM_STRUCT_NM(qw.) r15, 0x0078);
669	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, 0x0080);
670	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) cs, 0x0098);
671	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ss, 0x00b0);
672	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) ds, 0x00c8);
673	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) fs, 0x00e0);
674	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) gs, 0x00f8);
675	AssertCompileMemberOffset(CPUMCTX, ldtr, 0x0110);
676	AssertCompileMemberOffset(CPUMCTX, tr, 0x0128);
677	AssertCompileMemberOffset(CPUMCTX, rip, 0x0140);
678	AssertCompileMemberOffset(CPUMCTX, rflags, 0x0148);
679	AssertCompileMemberOffset(CPUMCTX, fExtrn, 0x0150);
680	AssertCompileMemberOffset(CPUMCTX, uRipInhibitInt, 0x0158);
681	AssertCompileMemberOffset(CPUMCTX, cr0, 0x0160);
682	AssertCompileMemberOffset(CPUMCTX, cr2, 0x0168);
683	AssertCompileMemberOffset(CPUMCTX, cr3, 0x0170);
684	AssertCompileMemberOffset(CPUMCTX, cr4, 0x0178);
685	AssertCompileMemberOffset(CPUMCTX, dr, 0x0180);
686	AssertCompileMemberOffset(CPUMCTX, gdtr, 0x01c0+6);
687	AssertCompileMemberOffset(CPUMCTX, idtr, 0x01d0+6);
688	AssertCompileMemberOffset(CPUMCTX, SysEnter, 0x01e0);
689	AssertCompileMemberOffset(CPUMCTX, msrEFER, 0x01f8);
690	AssertCompileMemberOffset(CPUMCTX, msrSTAR, 0x0200);
691	AssertCompileMemberOffset(CPUMCTX, msrPAT, 0x0208);
692	AssertCompileMemberOffset(CPUMCTX, msrLSTAR, 0x0210);
693	AssertCompileMemberOffset(CPUMCTX, msrCSTAR, 0x0218);
694	AssertCompileMemberOffset(CPUMCTX, msrSFMASK, 0x0220);
695	AssertCompileMemberOffset(CPUMCTX, msrKERNELGSBASE, 0x0228);
696	AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x0240);
697	AssertCompileMemberOffset(CPUMCTX, aXcr, 0x0260);
698	AssertCompileMemberOffset(CPUMCTX, fXStateMask, 0x0270);
699	AssertCompileMemberOffset(CPUMCTX, fUsedFpuGuest, 0x0278);
700	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0300);
701	AssertCompileMemberOffset(CPUMCTX, CPUM_UNION_NM(u.) abXState, 0x0300);
702	AssertCompileMemberAlignment(CPUMCTX, CPUM_UNION_NM(u.) XState, 0x0100);
703	/* Only do spot checks for hwvirt */
704	AssertCompileMemberAlignment(CPUMCTX, hwvirt, 0x1000);
705	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.Vmcb, X86_PAGE_SIZE);
706	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abMsrBitmap, X86_PAGE_SIZE);
707	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, X86_PAGE_SIZE);
708	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Vmcs, X86_PAGE_SIZE);
709	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.ShadowVmcs, X86_PAGE_SIZE);
710	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmreadBitmap, X86_PAGE_SIZE);
711	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abVmwriteBitmap, X86_PAGE_SIZE);
712	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aEntryMsrLoadArea, X86_PAGE_SIZE);
713	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrStoreArea, X86_PAGE_SIZE);
714	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.aExitMsrLoadArea, X86_PAGE_SIZE);
715	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abMsrBitmap, X86_PAGE_SIZE);
716	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, X86_PAGE_SIZE);
717	AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs, 8);
718	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.abIoBitmap, 0x7000);
719	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.fInterceptEvents, 0xa0d4);
720	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.abIoBitmap, 0xf000);
721	AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking, 0x1104a);
722	AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt, 0x11130);
723	AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif, 0x11134);
724	AssertCompileMemberOffset(CPUMCTX, hwvirt.fSavedInhibit, 0x11138);
725	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
726	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r0);
727	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r1);
728	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r2);
729	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r3);
730	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r4);
731	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r5);
732	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r6);
733	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.) r7);
734	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) eax);
735	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ecx);
736	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edx);
737	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebx);
738	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esp);
739	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) ebp);
740	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) esi);
741	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) edi);
742	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r8d);
743	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r9d);
744	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r10d);
745	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r11d);
746	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r12d);
747	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r13d);
748	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r14d);
749	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,dw.) r15d);
750	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) ax);
751	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) cx);
752	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) dx);
753	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bx);
754	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) sp);
755	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) bp);
756	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) si);
757	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) di);
758	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r8w);
759	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r9w);
760	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r10w);
761	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r11w);
762	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r12w);
763	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r13w);
764	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r14w);
765	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,w.) r15w);
766	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) al);
767	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) cl);
768	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dl);
769	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bl);
770	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) spl);
771	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) bpl);
772	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) sil);
773	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) dil);
774	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r8l);
775	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r9l);
776	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r10l);
777	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r11l);
778	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r12l);
779	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r13l);
780	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r14l);
781	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_STRUCT_NM(g,b.) r15l);
782	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_NM(s.) CPUM_STRUCT_NM(n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs);
783	# ifndef _MSC_VER
784	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xAX]);
785	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rcx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xCX]);
786	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDX]);
787	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbx, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBX]);
788	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSP]);
789	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rbp, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xBP]);
790	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rsi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xSI]);
791	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rdi, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_xDI]);
792	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r8, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x8]);
793	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r9, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x9]);
794	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r10, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x10]);
795	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r11, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x11]);
796	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r12, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x12]);
797	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r13, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x13]);
798	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r14, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x14]);
799	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) r15, CPUMCTX, CPUM_UNION_NM(g.) aGRegs[X86_GREG_x15]);
800	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) es, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_ES]);
801	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) cs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_CS]);
802	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ss, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_SS]);
803	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) ds, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_DS]);
804	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) fs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_FS]);
805	AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs, CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
806	# endif
807
808
809	/**
810	* Calculates the pointer to the given extended state component.
811	*
812	* @returns Pointer of type @a a_PtrType
813	* @param a_pCtx Pointer to the context.
814	* @param a_iCompBit The extended state component bit number. This bit
815	* must be set in CPUMCTX::fXStateMask.
816	* @param a_PtrType The pointer type of the extended state component.
817	*
818	*/
819	#if defined(VBOX_STRICT) && defined(RT_COMPILER_SUPPORTS_LAMBDA)
820	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
821	([](PCCPUMCTX a_pLambdaCtx) -> a_PtrType \
822	{ \
823	AssertCompile((a_iCompBit) < 64U); \
824	AssertMsg(a_pLambdaCtx->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
825	AssertMsg(a_pLambdaCtx->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
826	return (a_PtrType)(&a_pLambdaCtx->abXState[a_pLambdaCtx->aoffXState[(a_iCompBit)]]); \
827	}(a_pCtx))
828	#elif defined(VBOX_STRICT) && defined(__GNUC__)
829	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
830	__extension__ (\
831	{ \
832	AssertCompile((a_iCompBit) < 64U); \
833	AssertMsg((a_pCtx)->fXStateMask & RT_BIT_64(a_iCompBit), (#a_iCompBit "\n")); \
834	AssertMsg((a_pCtx)->aoffXState[(a_iCompBit)] != UINT16_MAX, (#a_iCompBit "\n")); \
835	(a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]); \
836	})
837	#else
838	# define CPUMCTX_XSAVE_C_PTR(a_pCtx, a_iCompBit, a_PtrType) \
839	((a_PtrType)(&(a_pCtx)->abXState[(a_pCtx)->aoffXState[(a_iCompBit)]]))
840	#endif
841
842	/**
843	* Gets the first selector register of a CPUMCTX.
844	*
845	* Use this with X86_SREG_COUNT to loop thru the selector registers.
846	*/
847	# define CPUMCTX_FIRST_SREG(a_pCtx) (&(a_pCtx)->es)
848
849	#endif /* !VBOX_FOR_DTRACE_LIB */
850
851
852	/** @name CPUMCTX_EXTRN_XXX
853	* Used for parts of the CPUM state that is externalized and needs fetching
854	* before use.
855	*
856	* @{ */
857	/** External state keeper: Invalid. */
858	#define CPUMCTX_EXTRN_KEEPER_INVALID UINT64_C(0x0000000000000000)
859	/** External state keeper: HM. */
860	#define CPUMCTX_EXTRN_KEEPER_HM UINT64_C(0x0000000000000001)
861	/** External state keeper: NEM. */
862	#define CPUMCTX_EXTRN_KEEPER_NEM UINT64_C(0x0000000000000002)
863	/** External state keeper: REM. */
864	#define CPUMCTX_EXTRN_KEEPER_REM UINT64_C(0x0000000000000003)
865	/** External state keeper mask. */
866	#define CPUMCTX_EXTRN_KEEPER_MASK UINT64_C(0x0000000000000003)
867
868	/** The RIP register value is kept externally. */
869	#define CPUMCTX_EXTRN_RIP UINT64_C(0x0000000000000004)
870	/** The RFLAGS register values are kept externally. */
871	#define CPUMCTX_EXTRN_RFLAGS UINT64_C(0x0000000000000008)
872
873	/** The RAX register value is kept externally. */
874	#define CPUMCTX_EXTRN_RAX UINT64_C(0x0000000000000010)
875	/** The RCX register value is kept externally. */
876	#define CPUMCTX_EXTRN_RCX UINT64_C(0x0000000000000020)
877	/** The RDX register value is kept externally. */
878	#define CPUMCTX_EXTRN_RDX UINT64_C(0x0000000000000040)
879	/** The RBX register value is kept externally. */
880	#define CPUMCTX_EXTRN_RBX UINT64_C(0x0000000000000080)
881	/** The RSP register value is kept externally. */
882	#define CPUMCTX_EXTRN_RSP UINT64_C(0x0000000000000100)
883	/** The RBP register value is kept externally. */
884	#define CPUMCTX_EXTRN_RBP UINT64_C(0x0000000000000200)
885	/** The RSI register value is kept externally. */
886	#define CPUMCTX_EXTRN_RSI UINT64_C(0x0000000000000400)
887	/** The RDI register value is kept externally. */
888	#define CPUMCTX_EXTRN_RDI UINT64_C(0x0000000000000800)
889	/** The R8 thru R15 register values are kept externally. */
890	#define CPUMCTX_EXTRN_R8_R15 UINT64_C(0x0000000000001000)
891	/** General purpose registers mask. */
892	#define CPUMCTX_EXTRN_GPRS_MASK UINT64_C(0x0000000000001ff0)
893
894	/** The ES register values are kept externally. */
895	#define CPUMCTX_EXTRN_ES UINT64_C(0x0000000000002000)
896	/** The CS register values are kept externally. */
897	#define CPUMCTX_EXTRN_CS UINT64_C(0x0000000000004000)
898	/** The SS register values are kept externally. */
899	#define CPUMCTX_EXTRN_SS UINT64_C(0x0000000000008000)
900	/** The DS register values are kept externally. */
901	#define CPUMCTX_EXTRN_DS UINT64_C(0x0000000000010000)
902	/** The FS register values are kept externally. */
903	#define CPUMCTX_EXTRN_FS UINT64_C(0x0000000000020000)
904	/** The GS register values are kept externally. */
905	#define CPUMCTX_EXTRN_GS UINT64_C(0x0000000000040000)
906	/** Segment registers (includes CS). */
907	#define CPUMCTX_EXTRN_SREG_MASK UINT64_C(0x000000000007e000)
908	/** Converts a X86_XREG_XXX index to a CPUMCTX_EXTRN_xS mask. */
909	#define CPUMCTX_EXTRN_SREG_FROM_IDX(a_SRegIdx) RT_BIT_64((a_SRegIdx) + 13)
910	#ifndef VBOX_FOR_DTRACE_LIB
911	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_ES) == CPUMCTX_EXTRN_ES);
912	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_CS) == CPUMCTX_EXTRN_CS);
913	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_DS) == CPUMCTX_EXTRN_DS);
914	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_FS) == CPUMCTX_EXTRN_FS);
915	AssertCompile(CPUMCTX_EXTRN_SREG_FROM_IDX(X86_SREG_GS) == CPUMCTX_EXTRN_GS);
916	#endif
917
918	/** The GDTR register values are kept externally. */
919	#define CPUMCTX_EXTRN_GDTR UINT64_C(0x0000000000080000)
920	/** The IDTR register values are kept externally. */
921	#define CPUMCTX_EXTRN_IDTR UINT64_C(0x0000000000100000)
922	/** The LDTR register values are kept externally. */
923	#define CPUMCTX_EXTRN_LDTR UINT64_C(0x0000000000200000)
924	/** The TR register values are kept externally. */
925	#define CPUMCTX_EXTRN_TR UINT64_C(0x0000000000400000)
926	/** Table register mask. */
927	#define CPUMCTX_EXTRN_TABLE_MASK UINT64_C(0x0000000000780000)
928
929	/** The CR0 register value is kept externally. */
930	#define CPUMCTX_EXTRN_CR0 UINT64_C(0x0000000000800000)
931	/** The CR2 register value is kept externally. */
932	#define CPUMCTX_EXTRN_CR2 UINT64_C(0x0000000001000000)
933	/** The CR3 register value is kept externally. */
934	#define CPUMCTX_EXTRN_CR3 UINT64_C(0x0000000002000000)
935	/** The CR4 register value is kept externally. */
936	#define CPUMCTX_EXTRN_CR4 UINT64_C(0x0000000004000000)
937	/** Control register mask. */
938	#define CPUMCTX_EXTRN_CR_MASK UINT64_C(0x0000000007800000)
939	/** The TPR/CR8 register value is kept externally. */
940	#define CPUMCTX_EXTRN_APIC_TPR UINT64_C(0x0000000008000000)
941	/** The EFER register value is kept externally. */
942	#define CPUMCTX_EXTRN_EFER UINT64_C(0x0000000010000000)
943
944	/** The DR0, DR1, DR2 and DR3 register values are kept externally. */
945	#define CPUMCTX_EXTRN_DR0_DR3 UINT64_C(0x0000000020000000)
946	/** The DR6 register value is kept externally. */
947	#define CPUMCTX_EXTRN_DR6 UINT64_C(0x0000000040000000)
948	/** The DR7 register value is kept externally. */
949	#define CPUMCTX_EXTRN_DR7 UINT64_C(0x0000000080000000)
950	/** Debug register mask. */
951	#define CPUMCTX_EXTRN_DR_MASK UINT64_C(0x00000000e0000000)
952
953	/** The XSAVE_C_X87 state is kept externally. */
954	#define CPUMCTX_EXTRN_X87 UINT64_C(0x0000000100000000)
955	/** The XSAVE_C_SSE, XSAVE_C_YMM, XSAVE_C_ZMM_HI256, XSAVE_C_ZMM_16HI and
956	* XSAVE_C_OPMASK state is kept externally. */
957	#define CPUMCTX_EXTRN_SSE_AVX UINT64_C(0x0000000200000000)
958	/** The state of XSAVE components not covered by CPUMCTX_EXTRN_X87 and
959	* CPUMCTX_EXTRN_SEE_AVX is kept externally. */
960	#define CPUMCTX_EXTRN_OTHER_XSAVE UINT64_C(0x0000000400000000)
961	/** The state of XCR0 and XCR1 register values are kept externally. */
962	#define CPUMCTX_EXTRN_XCRx UINT64_C(0x0000000800000000)
963
964
965	/** The KERNEL GS BASE MSR value is kept externally. */
966	#define CPUMCTX_EXTRN_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
967	/** The STAR, LSTAR, CSTAR and SFMASK MSR values are kept externally. */
968	#define CPUMCTX_EXTRN_SYSCALL_MSRS UINT64_C(0x0000002000000000)
969	/** The SYSENTER_CS, SYSENTER_EIP and SYSENTER_ESP MSR values are kept externally. */
970	#define CPUMCTX_EXTRN_SYSENTER_MSRS UINT64_C(0x0000004000000000)
971	/** The TSC_AUX MSR is kept externally. */
972	#define CPUMCTX_EXTRN_TSC_AUX UINT64_C(0x0000008000000000)
973	/** All other stateful MSRs not covered by CPUMCTX_EXTRN_EFER,
974	* CPUMCTX_EXTRN_KERNEL_GS_BASE, CPUMCTX_EXTRN_SYSCALL_MSRS,
975	* CPUMCTX_EXTRN_SYSENTER_MSRS, and CPUMCTX_EXTRN_TSC_AUX. */
976	#define CPUMCTX_EXTRN_OTHER_MSRS UINT64_C(0x0000010000000000)
977
978	/** Mask of all the MSRs. */
979	#define CPUMCTX_EXTRN_ALL_MSRS ( CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \
980	\| CPUMCTX_EXTRN_SYSENTER_MSRS \| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS)
981
982	/** Hardware-virtualization (SVM or VMX) state is kept externally. */
983	#define CPUMCTX_EXTRN_HWVIRT UINT64_C(0x0000020000000000)
984
985	/** Inhibit maskable interrupts (VMCPU_FF_INHIBIT_INTERRUPTS) */
986	#define CPUMCTX_EXTRN_INHIBIT_INT UINT64_C(0x0000040000000000)
987	/** Inhibit non-maskable interrupts (VMCPU_FF_BLOCK_NMIS). */
988	#define CPUMCTX_EXTRN_INHIBIT_NMI UINT64_C(0x0000080000000000)
989
990	/** Mask of bits the keepers can use for state tracking. */
991	#define CPUMCTX_EXTRN_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
992
993	/** NEM/Win: Event injection (known was interruption) pending state. */
994	#define CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT UINT64_C(0x0001000000000000)
995	/** NEM/Win: Mask. */
996	#define CPUMCTX_EXTRN_NEM_WIN_MASK UINT64_C(0x0001000000000000)
997
998	/** HM/SVM: Nested-guest interrupt pending (VMCPU_FF_INTERRUPT_NESTED_GUEST). */
999	#define CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ UINT64_C(0x0001000000000000)
1000	/** HM/SVM: Mask. */
1001	#define CPUMCTX_EXTRN_HM_SVM_MASK UINT64_C(0x0001000000000000)
1002
1003	/** All CPUM state bits, not including keeper specific ones. */
1004	#define CPUMCTX_EXTRN_ALL UINT64_C(0x00000ffffffffffc)
1005	/** All CPUM state bits, including keeper specific ones. */
1006	#define CPUMCTX_EXTRN_ABSOLUTELY_ALL UINT64_C(0xfffffffffffffffc)
1007	/** @} */
1008
1009
1010	/** @name CPUMCTX_INHIBIT_XXX - Interrupt inhibiting flags.
1011	* @{ */
1012	/** Interrupt shadow following MOV SS or POP SS.
1013	*
1014	* When this in effect, both maskable and non-maskable interrupts are blocked
1015	* from delivery for one instruction. Same for certain debug exceptions too,
1016	* unlike the STI variant.
1017	*
1018	* It is implementation specific whether a sequence of two or more of these
1019	* instructions will have any effect on the instruction following the last one
1020	* of them. */
1021	#define CPUMCTX_INHIBIT_SHADOW_SS RT_BIT_32(0 + CPUMX86EFLAGS_HW_BITS)
1022	/** Interrupt shadow following STI.
1023	* Same as CPUMCTX_INHIBIT_SHADOW_SS but without blocking any debug exceptions. */
1024	#define CPUMCTX_INHIBIT_SHADOW_STI RT_BIT_32(1 + CPUMX86EFLAGS_HW_BITS)
1025	/** Mask combining STI and SS shadowing. */
1026	#define CPUMCTX_INHIBIT_SHADOW (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI)
1027
1028	/** Interrupts blocked by NMI delivery. This condition is cleared by IRET.
1029	*
1030	* Section "6.7 NONMASKABLE INTERRUPT (NMI)" in Intel SDM Vol 3A states that
1031	* "The processor also invokes certain hardware conditions to ensure that no
1032	* other interrupts, including NMI interrupts, are received until the NMI
1033	* handler has completed executing." This flag indicates that these
1034	* conditions are currently active.
1035	*
1036	* @todo this does not really need to be in the lower 32-bits of EFLAGS.
1037	*/
1038	#define CPUMCTX_INHIBIT_NMI RT_BIT_32(2 + CPUMX86EFLAGS_HW_BITS)
1039
1040	/** Mask containing all the interrupt inhibit bits. */
1041	#define CPUMCTX_INHIBIT_ALL_MASK (CPUMCTX_INHIBIT_SHADOW_SS \| CPUMCTX_INHIBIT_SHADOW_STI \| CPUMCTX_INHIBIT_NMI)
1042	AssertCompile(CPUMCTX_INHIBIT_ALL_MASK < UINT32_MAX);
1043	/** @} */
1044
1045	/** @name CPUMCTX_DBG_XXX - Pending debug events.
1046	* @{ */
1047	/** Hit guest DR0 breakpoint. */
1048	#define CPUMCTX_DBG_HIT_DR0 RT_BIT_32(CPUMCTX_DBG_HIT_DR0_BIT)
1049	#define CPUMCTX_DBG_HIT_DR0_BIT (3 + CPUMX86EFLAGS_HW_BITS)
1050	/** Hit guest DR1 breakpoint. */
1051	#define CPUMCTX_DBG_HIT_DR1 RT_BIT_32(CPUMCTX_DBG_HIT_DR1_BIT)
1052	#define CPUMCTX_DBG_HIT_DR1_BIT (4 + CPUMX86EFLAGS_HW_BITS)
1053	/** Hit guest DR2 breakpoint. */
1054	#define CPUMCTX_DBG_HIT_DR2 RT_BIT_32(CPUMCTX_DBG_HIT_DR2_BIT)
1055	#define CPUMCTX_DBG_HIT_DR2_BIT (5 + CPUMX86EFLAGS_HW_BITS)
1056	/** Hit guest DR3 breakpoint. */
1057	#define CPUMCTX_DBG_HIT_DR3 RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
1058	#define CPUMCTX_DBG_HIT_DR3_BIT (6 + CPUMX86EFLAGS_HW_BITS)
1059	/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
1060	#define CPUMCTX_DBG_HIT_DRX_SHIFT CPUMCTX_DBG_HIT_DR0_BIT
1061	/** Mask of all guest pending DR0-DR3 breakpoint indicators. */
1062	#define CPUMCTX_DBG_HIT_DRX_MASK (CPUMCTX_DBG_HIT_DR0 \| CPUMCTX_DBG_HIT_DR1 \| CPUMCTX_DBG_HIT_DR2 \| CPUMCTX_DBG_HIT_DR3)
1063	/** DBGF event/breakpoint pending. */
1064	#define CPUMCTX_DBG_DBGF_EVENT RT_BIT_32(CPUMCTX_DBG_DBGF_EVENT_BIT)
1065	#define CPUMCTX_DBG_DBGF_EVENT_BIT (7 + CPUMX86EFLAGS_HW_BITS)
1066	/** DBGF event/breakpoint pending. */
1067	#define CPUMCTX_DBG_DBGF_BP RT_BIT_32(CPUMCTX_DBG_DBGF_BP_BIT)
1068	#define CPUMCTX_DBG_DBGF_BP_BIT (8 + CPUMX86EFLAGS_HW_BITS)
1069	/** Mask of all DBGF indicators. */
1070	#define CPUMCTX_DBG_DBGF_MASK (CPUMCTX_DBG_DBGF_EVENT \| CPUMCTX_DBG_DBGF_BP)
1071	AssertCompile((CPUMCTX_DBG_HIT_DRX_MASK \| CPUMCTX_DBG_DBGF_MASK) < UINT32_MAX);
1072	/** @} */
1073
1074
1075
1076	/**
1077	* Additional guest MSRs (i.e. not part of the CPU context structure).
1078	*
1079	* @remarks Never change the order here because of the saved stated! The size
1080	* can in theory be changed, but keep older VBox versions in mind.
1081	*/
1082	typedef union CPUMCTXMSRS
1083	{
1084	struct
1085	{
1086	uint64_t TscAux; /*< MSR_K8_TSC_AUX /
1087	uint64_t MiscEnable; /*< MSR_IA32_MISC_ENABLE /
1088	uint64_t MtrrDefType; /*< IA32_MTRR_DEF_TYPE /
1089	uint64_t MtrrFix64K_00000; /*< IA32_MTRR_FIX16K_80000 /
1090	uint64_t MtrrFix16K_80000; /*< IA32_MTRR_FIX16K_80000 /
1091	uint64_t MtrrFix16K_A0000; /*< IA32_MTRR_FIX16K_A0000 /
1092	uint64_t MtrrFix4K_C0000; /*< IA32_MTRR_FIX4K_C0000 /
1093	uint64_t MtrrFix4K_C8000; /*< IA32_MTRR_FIX4K_C8000 /
1094	uint64_t MtrrFix4K_D0000; /*< IA32_MTRR_FIX4K_D0000 /
1095	uint64_t MtrrFix4K_D8000; /*< IA32_MTRR_FIX4K_D8000 /
1096	uint64_t MtrrFix4K_E0000; /*< IA32_MTRR_FIX4K_E0000 /
1097	uint64_t MtrrFix4K_E8000; /*< IA32_MTRR_FIX4K_E8000 /
1098	uint64_t MtrrFix4K_F0000; /*< IA32_MTRR_FIX4K_F0000 /
1099	uint64_t MtrrFix4K_F8000; /*< IA32_MTRR_FIX4K_F8000 /
1100	uint64_t PkgCStateCfgCtrl; /*< MSR_PKG_CST_CONFIG_CONTROL /
1101	uint64_t SpecCtrl; /*< IA32_SPEC_CTRL /
1102	uint64_t ArchCaps; /*< IA32_ARCH_CAPABILITIES /
1103	} msr;
1104	uint64_t au64[64];
1105	} CPUMCTXMSRS;
1106	/** Pointer to the guest MSR state. */
1107	typedef CPUMCTXMSRS *PCPUMCTXMSRS;
1108	/** Pointer to the const guest MSR state. */
1109	typedef const CPUMCTXMSRS *PCCPUMCTXMSRS;
1110
1111	/** @} */
1112
1113	RT_C_DECLS_END
1114
1115	#endif /* !VBOX_INCLUDED_vmm_cpumctx_h */
1116

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source: vbox/trunk/include/VBox/vmm/cpumctx.h@ 97705

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