VirtualBox

source: vbox/trunk/include/VBox/vmm/em.h@ 44375

Last change on this file since 44375 was 44375, checked in by vboxsync, 12 years ago

EM: pVM -> pUVM for main, mark as many as possible interfaces module internal.
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File size: 11.9 KB
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1/** @file
2 * EM - Execution Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_em_h
27#define ___VBox_vmm_em_h
28
29#include <VBox/types.h>
30#include <VBox/vmm/trpm.h>
31
32
33RT_C_DECLS_BEGIN
34
35/** @defgroup grp_em The Execution Monitor / Manager API
36 * @{
37 */
38
39/** Enable to allow V86 code to run in raw mode. */
40#define VBOX_RAW_V86
41
42/**
43 * The Execution Manager State.
44 *
45 * @remarks This is used in the saved state!
46 */
47typedef enum EMSTATE
48{
49 /** Not yet started. */
50 EMSTATE_NONE = 1,
51 /** Raw-mode execution. */
52 EMSTATE_RAW,
53 /** Hardware accelerated raw-mode execution. */
54 EMSTATE_HM,
55 /** Value reserved for future use (used to be PARAV). */
56 EMSTATE_RESERVED,
57 /** Recompiled mode execution. */
58 EMSTATE_REM,
59 /** Execution is halted. (waiting for interrupt) */
60 EMSTATE_HALTED,
61 /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
62 EMSTATE_WAIT_SIPI,
63 /** Execution is suspended. */
64 EMSTATE_SUSPENDED,
65 /** The VM is terminating. */
66 EMSTATE_TERMINATING,
67 /** Guest debug event from raw-mode is being processed. */
68 EMSTATE_DEBUG_GUEST_RAW,
69 /** Guest debug event from hardware accelerated mode is being processed. */
70 EMSTATE_DEBUG_GUEST_HM,
71 /** Guest debug event from recompiled-mode is being processed. */
72 EMSTATE_DEBUG_GUEST_REM,
73 /** Hypervisor debug event being processed. */
74 EMSTATE_DEBUG_HYPER,
75 /** The VM has encountered a fatal error. (And everyone is panicing....) */
76 EMSTATE_GURU_MEDITATION,
77 /** Just a hack to ensure that we get a 32-bit integer. */
78 EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
79} EMSTATE;
80
81
82/**
83 * EMInterpretInstructionCPU execution modes.
84 */
85typedef enum
86{
87 /** Only supervisor code (CPL=0). */
88 EMCODETYPE_SUPERVISOR,
89 /** User-level code only. */
90 EMCODETYPE_USER,
91 /** Supervisor and user-level code (use with great care!). */
92 EMCODETYPE_ALL,
93 /** Just a hack to ensure that we get a 32-bit integer. */
94 EMCODETYPE_32BIT_HACK = 0x7fffffff
95} EMCODETYPE;
96
97VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu);
98VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
99
100/** @name Callback handlers for instruction emulation functions.
101 * These are placed here because IOM wants to use them as well.
102 * @{
103 */
104typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
105typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
106typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
107typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
108typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
109typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
110typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
111typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
112typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
113typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
114/** @} */
115
116
117/**
118 * Checks if raw ring-3 execute mode is enabled.
119 *
120 * @returns true if enabled.
121 * @returns false if disabled.
122 * @param pVM The VM to operate on.
123 */
124#define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser)
125
126/**
127 * Checks if raw ring-0 execute mode is enabled.
128 *
129 * @returns true if enabled.
130 * @returns false if disabled.
131 * @param pVM The VM to operate on.
132 */
133#define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor)
134
135/**
136 * Checks if execution with hardware assisted virtualization is enabled.
137 *
138 * @returns true if enabled.
139 * @returns false if disabled.
140 * @param pVM The VM to operate on.
141 */
142#define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser)
143
144/**
145 * Checks if execution of supervisor code should be done in the
146 * recompiler or not.
147 *
148 * @returns true if enabled.
149 * @returns false if disabled.
150 * @param pVM The VM to operate on.
151 */
152#define EMIsSupervisorCodeRecompiled(pVM) ((pVM)->fRecompileSupervisor)
153
154VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
155VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
156VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
157VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
158 PDISCPUSTATE pDISState, unsigned *pcbInstr);
159VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
160VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
161VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
162 RTGCPTR pvFault, EMCODETYPE enmCodeType);
163
164#ifdef IN_RC
165VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
166#endif
167
168VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
169VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
170VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
171VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
172VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
173VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
174VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
175VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
176VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
177VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
178VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
179VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
180VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
181#ifndef VBOX_WITH_IEM
182VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
183VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
184#endif /* !VBOX_WITH_IEM */
185VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
186VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx);
187VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
188
189/** @name Assembly routines
190 * @{ */
191VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
192VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
193VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
194VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
195VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
196VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
197VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
198VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
199VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
200VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
201VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
202VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
203VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
204VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
205VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
206VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
207VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
208VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
209VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
210VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
211VMMDECL(uint32_t) EMEmulateXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
212VMMDECL(uint32_t) EMEmulateLockXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
213/** @} */
214
215/** @name REM locking routines
216 * @{ */
217VMMDECL(void) EMRemUnlock(PVM pVM);
218VMMDECL(void) EMRemLock(PVM pVM);
219VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
220VMM_INT_DECL(int) EMRemTryLock(PVM pVM);
221/** @} */
222
223#ifdef IN_RING3
224/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
225 * @ingroup grp_em
226 * @{
227 */
228
229/**
230 * Command argument for EMR3RawSetMode().
231 *
232 * It's possible to extend this interface to change several
233 * execution modes at once should the need arise.
234 */
235typedef enum EMEXECPOLICY
236{
237 /** The customary invalid zero entry. */
238 EMEXECPOLICY_INVALID = 0,
239 /** Whether to recompile ring-0 code or execute it in raw/hm. */
240 EMEXECPOLICY_RECOMPILE_RING0,
241 /** Whether to recompile ring-3 code or execute it in raw/hm. */
242 EMEXECPOLICY_RECOMPILE_RING3,
243 /** End of valid value (not included). */
244 EMEXECPOLICY_END,
245 /** The customary 32-bit type blowup. */
246 EMEXECPOLICY_32BIT_HACK = 0x7fffffff
247} EMEXECPOLICY;
248VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce);
249VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM);
250VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM);
251
252VMMR3_INT_DECL(int) EMR3Init(PVM pVM);
253VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM);
254VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
255VMMR3_INT_DECL(void) EMR3Reset(PVM pVM);
256VMMR3_INT_DECL(int) EMR3Term(PVM pVM);
257VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
258VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
259VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
260VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM);
261VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM);
262VMMR3_INT_DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu);
263/** @} */
264#endif /* IN_RING3 */
265
266/** @} */
267
268RT_C_DECLS_END
269
270#endif
271
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