VirtualBox

source: vbox/trunk/include/VBox/vmm/hm.h@ 75440

Last change on this file since 75440 was 75440, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Separate the VMX/SVM CPU spec. functions into CPUM as they can be called from IEM/REM/CPUM as well as HM.
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1/** @file
2 * HM - Intel/AMD VM Hardware Assisted Virtualization Manager (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_hm_h
27#define ___VBox_vmm_hm_h
28
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/cpum.h>
31#include <VBox/vmm/vmm.h>
32#include <VBox/vmm/hm_svm.h>
33#include <VBox/vmm/hm_vmx.h>
34#include <VBox/vmm/trpm.h>
35#include <iprt/mp.h>
36
37
38/** @defgroup grp_hm The Hardware Assisted Virtualization Manager API
39 * @ingroup grp_vmm
40 * @{
41 */
42
43RT_C_DECLS_BEGIN
44
45/**
46 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
47 *
48 * @retval true if used.
49 * @retval false if software virtualization (raw-mode) or NEM is used.
50 *
51 * @param a_pVM The cross context VM structure.
52 * @deprecated Please use VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED, or
53 * VM_IS_HM_ENABLED instead.
54 * @internal
55 */
56#if defined(VBOX_STRICT) && defined(IN_RING3)
57# define HMIsEnabled(a_pVM) HMIsEnabledNotMacro(a_pVM)
58#else
59# define HMIsEnabled(a_pVM) ((a_pVM)->fHMEnabled)
60#endif
61
62/**
63 * Checks whether raw-mode context is required for HM purposes
64 *
65 * @retval true if required by HM for doing switching the cpu to 64-bit mode.
66 * @retval false if not required by HM.
67 *
68 * @param a_pVM The cross context VM structure.
69 * @internal
70 */
71#if HC_ARCH_BITS == 64
72# define HMIsRawModeCtxNeeded(a_pVM) (false)
73#else
74# define HMIsRawModeCtxNeeded(a_pVM) ((a_pVM)->fHMNeedRawModeCtx)
75#endif
76
77/**
78 * Checks whether we're in the special hardware virtualization context.
79 * @returns true / false.
80 * @param a_pVCpu The caller's cross context virtual CPU structure.
81 * @thread EMT
82 */
83#ifdef IN_RING0
84# define HMIsInHwVirtCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_HM)
85#else
86# define HMIsInHwVirtCtx(a_pVCpu) (false)
87#endif
88
89/**
90 * Checks whether we're in the special hardware virtualization context and we
91 * cannot perform long jump without guru meditating and possibly messing up the
92 * host and/or guest state.
93 *
94 * This is after we've turned interrupts off and such.
95 *
96 * @returns true / false.
97 * @param a_pVCpu The caller's cross context virtual CPU structure.
98 * @thread EMT
99 */
100#ifdef IN_RING0
101# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (VMCPU_GET_STATE(a_pVCpu) == VMCPUSTATE_STARTED_EXEC)
102#else
103# define HMIsInHwVirtNoLongJmpCtx(a_pVCpu) (false)
104#endif
105
106/**
107 * 64-bit raw-mode (intermediate memory context) operations.
108 *
109 * These are special hypervisor eip values used when running 64-bit guests on
110 * 32-bit hosts. Each operation corresponds to a routine.
111 *
112 * @note Duplicated in the assembly code!
113 */
114typedef enum HM64ON32OP
115{
116 HM64ON32OP_INVALID = 0,
117 HM64ON32OP_VMXRCStartVM64,
118 HM64ON32OP_SVMRCVMRun64,
119 HM64ON32OP_HMRCSaveGuestFPU64,
120 HM64ON32OP_HMRCSaveGuestDebug64,
121 HM64ON32OP_HMRCTestSwitcher64,
122 HM64ON32OP_END,
123 HM64ON32OP_32BIT_HACK = 0x7fffffff
124} HM64ON32OP;
125
126/** @name All-context HM API.
127 * @{ */
128VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM);
129VMMDECL(bool) HMCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx);
130VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
131VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM);
132VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu);
133VMM_INT_DECL(bool) HMSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable);
134VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM);
135VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM);
136VMM_INT_DECL(bool) HMIsVmxSupported(PVM pVM);
137VMM_INT_DECL(const char *) HMVmxGetDiagDesc(VMXVDIAG enmDiag);
138VMM_INT_DECL(const char *) HMVmxGetAbortDesc(VMXABORT enmAbort);
139VMM_INT_DECL(void) HMHCPagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
140/** @} */
141
142/** @name All-context VMX helpers.
143 *
144 * These are hardware-assisted VMX functions (used by IEM/REM/CPUM and HM). Helpers
145 * based purely on the Intel VT-x specification (used by IEM/REM and HM) can be
146 * found in CPUM.
147 * @{ */
148VMM_INT_DECL(int) HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs);
149VMM_INT_DECL(int) HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue);
150VMM_INT_DECL(bool) HMVmxCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx);
151VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode,
152 uint32_t cbInstr, RTGCUINTPTR GCPtrFaultAddress);
153/** @} */
154
155/** @name All-context SVM helpers.
156 *
157 * These are hardware-assisted SVM functions (used by IEM/REM/CPUM and HM). Helpers
158 * based purely on the AMD SVM specification (used by IEM/REM and HM) can be found
159 * in CPUM.
160 * @{ */
161VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pSvmEvent);
162/** @} */
163
164#ifndef IN_RC
165
166/** @name R0, R3 HM (VMX/SVM agnostic) handlers.
167 * @{ */
168VMM_INT_DECL(int) HMFlushTLB(PVMCPU pVCpu);
169VMM_INT_DECL(int) HMFlushTLBOnAllVCpus(PVM pVM);
170VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
171VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
172VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM);
173VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM);
174VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM);
175VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM);
176/** @} */
177
178/** @name R0, R3 SVM handlers.
179 * @{ */
180VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM);
181VMM_INT_DECL(uint64_t) HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks);
182# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
183VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx);
184# endif
185VMM_INT_DECL(int) HMSvmIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
186VMM_INT_DECL(int) HMHCSvmMaybeMovTprHypercall(PVMCPU pVCpu);
187/** @} */
188
189#else /* Nops in RC: */
190
191/** @name RC HM (VMX/SVM agnostic) handlers.
192 * @{ */
193# define HMFlushTLB(pVCpu) do { } while (0)
194# define HMFlushTLBOnAllVCpus(pVM) do { } while (0)
195# define HMInvalidatePageOnAllVCpus(pVM, GCVirt) do { } while (0)
196# define HMInvalidatePhysPage(pVM, GCVirt) do { } while (0)
197# define HMAreNestedPagingAndFullGuestExecEnabled(pVM) false
198# define HMIsLongModeAllowed(pVM) false
199# define HMIsNestedPagingActive(pVM) false
200# define HMIsMsrBitmapsActive(pVM) false
201/** @} */
202
203/** @name RC SVM handlers.
204 * @{ */
205# define HMSvmIsVGifActive(pVM) false
206# define HMSvmNstGstApplyTscOffset(pVCpu, uTicks) (uTicks)
207# define HMSvmNstGstVmExitNotify(pVCpu, pCtx) do { } while (0)
208# define HMSvmIsSubjectToErratum170(puFamily, puModel, puStepping) false
209# define HMHCSvmMaybeMovTprHypercall(pVCpu) do { } while (0)
210/** @} */
211
212#endif
213
214#ifdef IN_RING0
215/** @defgroup grp_hm_r0 The HM ring-0 Context API
216 * @{
217 */
218VMMR0_INT_DECL(int) HMR0Init(void);
219VMMR0_INT_DECL(int) HMR0Term(void);
220VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM);
221VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM);
222VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM);
223# ifdef VBOX_WITH_RAW_MODE
224VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled);
225VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled);
226# endif
227
228VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM);
229VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu);
230VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu);
231VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu);
232VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser);
233VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU VCpu);
234VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU VCpu);
235VMMR0_INT_DECL(bool) HMR0SuspendPending(void);
236VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
237VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
238
239# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
240VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
241VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
242VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM);
243# endif
244
245/** @} */
246#endif /* IN_RING0 */
247
248
249#ifdef IN_RING3
250/** @defgroup grp_hm_r3 The HM ring-3 Context API
251 * @{
252 */
253VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM);
254VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM);
255VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM);
256VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM);
257VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM);
258VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM);
259VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM);
260VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM);
261
262VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu);
263VMMR3_INT_DECL(int) HMR3Init(PVM pVM);
264VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
265VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM);
266VMMR3_INT_DECL(int) HMR3Term(PVM pVM);
267VMMR3_INT_DECL(void) HMR3Reset(PVM pVM);
268VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu);
269VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode);
270VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM);
271VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu);
272VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu);
273VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
274VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem);
275VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu);
276VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx);
277VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM);
278VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit);
279VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit);
280/** @} */
281#endif /* IN_RING3 */
282
283/** @} */
284RT_C_DECLS_END
285
286
287#endif
288
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