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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 100855

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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_hm_svm_h
37#define VBOX_INCLUDED_vmm_hm_svm_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#include <VBox/types.h>
43#include <iprt/assert.h>
44#include <iprt/asm.h>
45
46#ifdef RT_OS_SOLARIS
47# undef ES
48# undef CS
49# undef DS
50# undef SS
51# undef FS
52# undef GS
53#endif
54
55/** @defgroup grp_hm_svm SVM (AMD-V) Types and Definitions
56 * @ingroup grp_hm
57 * @{
58 */
59
60/** @name SVM generic / convenient defines.
61 * @{
62 */
63/** Number of pages required for the VMCB. */
64#define SVM_VMCB_PAGES 1
65/** Number of pages required for the MSR permission bitmap. */
66#define SVM_MSRPM_PAGES 2
67/** Number of pages required for the IO permission bitmap. */
68#define SVM_IOPM_PAGES 3
69/** @} */
70
71/*
72 * Ugly!
73 * When compiling the recompiler, its own svm.h defines clash with
74 * the following defines. Avoid just the duplicates here as we still
75 * require other definitions and structures in this header.
76 */
77#ifndef IN_REM_R3
78/** @name SVM_EXIT_XXX - SVM Basic Exit Reasons.
79 * @{
80 */
81/** Invalid guest state in VMCB. */
82# define SVM_EXIT_INVALID (uint64_t)(-1)
83/** Read from CR0-CR15. */
84# define SVM_EXIT_READ_CR0 0x0
85# define SVM_EXIT_READ_CR1 0x1
86# define SVM_EXIT_READ_CR2 0x2
87# define SVM_EXIT_READ_CR3 0x3
88# define SVM_EXIT_READ_CR4 0x4
89# define SVM_EXIT_READ_CR5 0x5
90# define SVM_EXIT_READ_CR6 0x6
91# define SVM_EXIT_READ_CR7 0x7
92# define SVM_EXIT_READ_CR8 0x8
93# define SVM_EXIT_READ_CR9 0x9
94# define SVM_EXIT_READ_CR10 0xa
95# define SVM_EXIT_READ_CR11 0xb
96# define SVM_EXIT_READ_CR12 0xc
97# define SVM_EXIT_READ_CR13 0xd
98# define SVM_EXIT_READ_CR14 0xe
99# define SVM_EXIT_READ_CR15 0xf
100/** Writes to CR0-CR15. */
101# define SVM_EXIT_WRITE_CR0 0x10
102# define SVM_EXIT_WRITE_CR1 0x11
103# define SVM_EXIT_WRITE_CR2 0x12
104# define SVM_EXIT_WRITE_CR3 0x13
105# define SVM_EXIT_WRITE_CR4 0x14
106# define SVM_EXIT_WRITE_CR5 0x15
107# define SVM_EXIT_WRITE_CR6 0x16
108# define SVM_EXIT_WRITE_CR7 0x17
109# define SVM_EXIT_WRITE_CR8 0x18
110# define SVM_EXIT_WRITE_CR9 0x19
111# define SVM_EXIT_WRITE_CR10 0x1a
112# define SVM_EXIT_WRITE_CR11 0x1b
113# define SVM_EXIT_WRITE_CR12 0x1c
114# define SVM_EXIT_WRITE_CR13 0x1d
115# define SVM_EXIT_WRITE_CR14 0x1e
116# define SVM_EXIT_WRITE_CR15 0x1f
117/** Read from DR0-DR15. */
118# define SVM_EXIT_READ_DR0 0x20
119# define SVM_EXIT_READ_DR1 0x21
120# define SVM_EXIT_READ_DR2 0x22
121# define SVM_EXIT_READ_DR3 0x23
122# define SVM_EXIT_READ_DR4 0x24
123# define SVM_EXIT_READ_DR5 0x25
124# define SVM_EXIT_READ_DR6 0x26
125# define SVM_EXIT_READ_DR7 0x27
126# define SVM_EXIT_READ_DR8 0x28
127# define SVM_EXIT_READ_DR9 0x29
128# define SVM_EXIT_READ_DR10 0x2a
129# define SVM_EXIT_READ_DR11 0x2b
130# define SVM_EXIT_READ_DR12 0x2c
131# define SVM_EXIT_READ_DR13 0x2d
132# define SVM_EXIT_READ_DR14 0x2e
133# define SVM_EXIT_READ_DR15 0x2f
134/** Writes to DR0-DR15. */
135# define SVM_EXIT_WRITE_DR0 0x30
136# define SVM_EXIT_WRITE_DR1 0x31
137# define SVM_EXIT_WRITE_DR2 0x32
138# define SVM_EXIT_WRITE_DR3 0x33
139# define SVM_EXIT_WRITE_DR4 0x34
140# define SVM_EXIT_WRITE_DR5 0x35
141# define SVM_EXIT_WRITE_DR6 0x36
142# define SVM_EXIT_WRITE_DR7 0x37
143# define SVM_EXIT_WRITE_DR8 0x38
144# define SVM_EXIT_WRITE_DR9 0x39
145# define SVM_EXIT_WRITE_DR10 0x3a
146# define SVM_EXIT_WRITE_DR11 0x3b
147# define SVM_EXIT_WRITE_DR12 0x3c
148# define SVM_EXIT_WRITE_DR13 0x3d
149# define SVM_EXIT_WRITE_DR14 0x3e
150# define SVM_EXIT_WRITE_DR15 0x3f
151/* Exception 0-31. */
152# define SVM_EXIT_XCPT_0 0x40
153# define SVM_EXIT_XCPT_1 0x41
154# define SVM_EXIT_XCPT_2 0x42
155# define SVM_EXIT_XCPT_3 0x43
156# define SVM_EXIT_XCPT_4 0x44
157# define SVM_EXIT_XCPT_5 0x45
158# define SVM_EXIT_XCPT_6 0x46
159# define SVM_EXIT_XCPT_7 0x47
160# define SVM_EXIT_XCPT_8 0x48
161# define SVM_EXIT_XCPT_9 0x49
162# define SVM_EXIT_XCPT_10 0x4a
163# define SVM_EXIT_XCPT_11 0x4b
164# define SVM_EXIT_XCPT_12 0x4c
165# define SVM_EXIT_XCPT_13 0x4d
166# define SVM_EXIT_XCPT_14 0x4e
167# define SVM_EXIT_XCPT_15 0x4f
168# define SVM_EXIT_XCPT_16 0x50
169# define SVM_EXIT_XCPT_17 0x51
170# define SVM_EXIT_XCPT_18 0x52
171# define SVM_EXIT_XCPT_19 0x53
172# define SVM_EXIT_XCPT_20 0x54
173# define SVM_EXIT_XCPT_21 0x55
174# define SVM_EXIT_XCPT_22 0x56
175# define SVM_EXIT_XCPT_23 0x57
176# define SVM_EXIT_XCPT_24 0x58
177# define SVM_EXIT_XCPT_25 0x59
178# define SVM_EXIT_XCPT_26 0x5a
179# define SVM_EXIT_XCPT_27 0x5b
180# define SVM_EXIT_XCPT_28 0x5c
181# define SVM_EXIT_XCPT_29 0x5d
182# define SVM_EXIT_XCPT_30 0x5e
183# define SVM_EXIT_XCPT_31 0x5f
184/* Exception (more readable) */
185# define SVM_EXIT_XCPT_DE SVM_EXIT_XCPT_0
186# define SVM_EXIT_XCPT_DB SVM_EXIT_XCPT_1
187# define SVM_EXIT_XCPT_NMI SVM_EXIT_XCPT_2
188# define SVM_EXIT_XCPT_BP SVM_EXIT_XCPT_3
189# define SVM_EXIT_XCPT_OF SVM_EXIT_XCPT_4
190# define SVM_EXIT_XCPT_BR SVM_EXIT_XCPT_5
191# define SVM_EXIT_XCPT_UD SVM_EXIT_XCPT_6
192# define SVM_EXIT_XCPT_NM SVM_EXIT_XCPT_7
193# define SVM_EXIT_XCPT_DF SVM_EXIT_XCPT_8
194# define SVM_EXIT_XCPT_CO_SEG_OVERRUN SVM_EXIT_XCPT_9
195# define SVM_EXIT_XCPT_TS SVM_EXIT_XCPT_10
196# define SVM_EXIT_XCPT_NP SVM_EXIT_XCPT_11
197# define SVM_EXIT_XCPT_SS SVM_EXIT_XCPT_12
198# define SVM_EXIT_XCPT_GP SVM_EXIT_XCPT_13
199# define SVM_EXIT_XCPT_PF SVM_EXIT_XCPT_14
200# define SVM_EXIT_XCPT_MF SVM_EXIT_XCPT_16
201# define SVM_EXIT_XCPT_AC SVM_EXIT_XCPT_17
202# define SVM_EXIT_XCPT_MC SVM_EXIT_XCPT_18
203# define SVM_EXIT_XCPT_XF SVM_EXIT_XCPT_19
204# define SVM_EXIT_XCPT_VE SVM_EXIT_XCPT_20
205# define SVM_EXIT_XCPT_SX SVM_EXIT_XCPT_30
206/** Physical maskable interrupt. */
207# define SVM_EXIT_INTR 0x60
208/** Non-maskable interrupt. */
209# define SVM_EXIT_NMI 0x61
210/** System Management interrupt. */
211# define SVM_EXIT_SMI 0x62
212/** Physical INIT signal. */
213# define SVM_EXIT_INIT 0x63
214/** Virtual interrupt. */
215# define SVM_EXIT_VINTR 0x64
216/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
217# define SVM_EXIT_CR0_SEL_WRITE 0x65
218/** IDTR read. */
219# define SVM_EXIT_IDTR_READ 0x66
220/** GDTR read. */
221# define SVM_EXIT_GDTR_READ 0x67
222/** LDTR read. */
223# define SVM_EXIT_LDTR_READ 0x68
224/** TR read. */
225# define SVM_EXIT_TR_READ 0x69
226/** IDTR write. */
227# define SVM_EXIT_IDTR_WRITE 0x6a
228/** GDTR write. */
229# define SVM_EXIT_GDTR_WRITE 0x6b
230/** LDTR write. */
231# define SVM_EXIT_LDTR_WRITE 0x6c
232/** TR write. */
233# define SVM_EXIT_TR_WRITE 0x6d
234/** RDTSC instruction. */
235# define SVM_EXIT_RDTSC 0x6e
236/** RDPMC instruction. */
237# define SVM_EXIT_RDPMC 0x6f
238/** PUSHF instruction. */
239# define SVM_EXIT_PUSHF 0x70
240/** POPF instruction. */
241# define SVM_EXIT_POPF 0x71
242/** CPUID instruction. */
243# define SVM_EXIT_CPUID 0x72
244/** RSM instruction. */
245# define SVM_EXIT_RSM 0x73
246/** IRET instruction. */
247# define SVM_EXIT_IRET 0x74
248/** Software interrupt (INTn instructions). */
249# define SVM_EXIT_SWINT 0x75
250/** INVD instruction. */
251# define SVM_EXIT_INVD 0x76
252/** PAUSE instruction. */
253# define SVM_EXIT_PAUSE 0x77
254/** HLT instruction. */
255# define SVM_EXIT_HLT 0x78
256/** INVLPG instructions. */
257# define SVM_EXIT_INVLPG 0x79
258/** INVLPGA instruction. */
259# define SVM_EXIT_INVLPGA 0x7a
260/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
261# define SVM_EXIT_IOIO 0x7b
262/** RDMSR or WRMSR access to protected MSR. */
263# define SVM_EXIT_MSR 0x7c
264/** task switch. */
265# define SVM_EXIT_TASK_SWITCH 0x7d
266/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
267# define SVM_EXIT_FERR_FREEZE 0x7e
268/** Shutdown. */
269# define SVM_EXIT_SHUTDOWN 0x7f
270/** VMRUN instruction. */
271# define SVM_EXIT_VMRUN 0x80
272/** VMMCALL instruction. */
273# define SVM_EXIT_VMMCALL 0x81
274/** VMLOAD instruction. */
275# define SVM_EXIT_VMLOAD 0x82
276/** VMSAVE instruction. */
277# define SVM_EXIT_VMSAVE 0x83
278/** STGI instruction. */
279# define SVM_EXIT_STGI 0x84
280/** CLGI instruction. */
281# define SVM_EXIT_CLGI 0x85
282/** SKINIT instruction. */
283# define SVM_EXIT_SKINIT 0x86
284/** RDTSCP instruction. */
285# define SVM_EXIT_RDTSCP 0x87
286/** ICEBP instruction. */
287# define SVM_EXIT_ICEBP 0x88
288/** WBINVD instruction. */
289# define SVM_EXIT_WBINVD 0x89
290/** MONITOR instruction. */
291# define SVM_EXIT_MONITOR 0x8a
292/** MWAIT instruction. */
293# define SVM_EXIT_MWAIT 0x8b
294/** MWAIT instruction, when armed. */
295# define SVM_EXIT_MWAIT_ARMED 0x8c
296/** XSETBV instruction. */
297# define SVM_EXIT_XSETBV 0x8d
298/** RDPRU instruction. */
299# define SVM_EXIT_RDPRU 0x8e
300/** Write to EFER (after guest instruction completes). */
301# define SVM_EXIT_WRITE_EFER_TRAP 0x8f
302/** Write to CR0-CR15 (after guest instruction completes). */
303# define SVM_EXIT_WRITE_CR0_TRAP 0x90
304# define SVM_EXIT_WRITE_CR1_TRAP 0x91
305# define SVM_EXIT_WRITE_CR2_TRAP 0x92
306# define SVM_EXIT_WRITE_CR3_TRAP 0x93
307# define SVM_EXIT_WRITE_CR4_TRAP 0x94
308# define SVM_EXIT_WRITE_CR5_TRAP 0x95
309# define SVM_EXIT_WRITE_CR6_TRAP 0x96
310# define SVM_EXIT_WRITE_CR7_TRAP 0x97
311# define SVM_EXIT_WRITE_CR8_TRAP 0x98
312# define SVM_EXIT_WRITE_CR9_TRAP 0x99
313# define SVM_EXIT_WRITE_CR10_TRAP 0x9a
314# define SVM_EXIT_WRITE_CR11_TRAP 0x9b
315# define SVM_EXIT_WRITE_CR12_TRAP 0x9c
316# define SVM_EXIT_WRITE_CR13_TRAP 0x9d
317# define SVM_EXIT_WRITE_CR14_TRAP 0x9e
318# define SVM_EXIT_WRITE_CR15_TRAP 0x9f
319/** MCOMMIT instruction. */
320# define SVM_EXIT_MCOMMIT 0xa3
321
322/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
323# define SVM_EXIT_NPF 0x400
324/** AVIC: Virtual IPI delivery not completed. */
325# define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
326/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
327 * hardware. */
328# define SVM_EXIT_AVIC_NOACCEL 0x402
329/** The maximum possible exit value. */
330# define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
331/** @} */
332#endif /* !IN_REM_R3*/
333
334
335/** @name SVMVMCB.u64ExitInfo2 for task switches
336 * @{
337 */
338/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
339#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
340/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
341#define SVM_EXIT2_TASK_SWITCH_JUMP RT_BIT_64(38)
342/** Set to 1 if the task switch has an error code; else cleared to 0. */
343#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
344/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
345#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
346/** @} */
347
348/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
349 * @{
350 */
351/** The access was a read MSR. */
352#define SVM_EXIT1_MSR_READ 0x0
353/** The access was a write MSR. */
354#define SVM_EXIT1_MSR_WRITE 0x1
355/** @} */
356
357/** @name SVMVMCB.u64ExitInfo1 for Mov CRx accesses.
358 * @{
359 */
360/** The mask of whether the access was via a Mov CRx instruction. */
361#define SVM_EXIT1_MOV_CRX_MASK RT_BIT_64(63)
362/** The mask for the GPR number of the Mov CRx instruction. */
363#define SVM_EXIT1_MOV_CRX_GPR_NUMBER 0xf
364/** @} */
365
366/** @name SVMVMCB.u64ExitInfo1 for Mov DRx accesses.
367 * @{
368 */
369/** The mask for the GPR number of the Mov DRx instruction. */
370#define SVM_EXIT1_MOV_DRX_GPR_NUMBER 0xf
371/** @} */
372
373/** @name SVMVMCB.ctrl.u64InterceptCtrl
374 * @{
375 */
376/** Intercept INTR (physical maskable interrupt). */
377#define SVM_CTRL_INTERCEPT_INTR RT_BIT_64(0)
378/** Intercept NMI. */
379#define SVM_CTRL_INTERCEPT_NMI RT_BIT_64(1)
380/** Intercept SMI. */
381#define SVM_CTRL_INTERCEPT_SMI RT_BIT_64(2)
382/** Intercept INIT. */
383#define SVM_CTRL_INTERCEPT_INIT RT_BIT_64(3)
384/** Intercept VINTR (virtual maskable interrupt). */
385#define SVM_CTRL_INTERCEPT_VINTR RT_BIT_64(4)
386/** Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
387#define SVM_CTRL_INTERCEPT_CR0_SEL_WRITE RT_BIT_64(5)
388/** Intercept reads of IDTR. */
389#define SVM_CTRL_INTERCEPT_IDTR_READS RT_BIT_64(6)
390/** Intercept reads of GDTR. */
391#define SVM_CTRL_INTERCEPT_GDTR_READS RT_BIT_64(7)
392/** Intercept reads of LDTR. */
393#define SVM_CTRL_INTERCEPT_LDTR_READS RT_BIT_64(8)
394/** Intercept reads of TR. */
395#define SVM_CTRL_INTERCEPT_TR_READS RT_BIT_64(9)
396/** Intercept writes of IDTR. */
397#define SVM_CTRL_INTERCEPT_IDTR_WRITES RT_BIT_64(10)
398/** Intercept writes of GDTR. */
399#define SVM_CTRL_INTERCEPT_GDTR_WRITES RT_BIT_64(11)
400/** Intercept writes of LDTR. */
401#define SVM_CTRL_INTERCEPT_LDTR_WRITES RT_BIT_64(12)
402/** Intercept writes of TR. */
403#define SVM_CTRL_INTERCEPT_TR_WRITES RT_BIT_64(13)
404/** Intercept RDTSC instruction. */
405#define SVM_CTRL_INTERCEPT_RDTSC RT_BIT_64(14)
406/** Intercept RDPMC instruction. */
407#define SVM_CTRL_INTERCEPT_RDPMC RT_BIT_64(15)
408/** Intercept PUSHF instruction. */
409#define SVM_CTRL_INTERCEPT_PUSHF RT_BIT_64(16)
410/** Intercept POPF instruction. */
411#define SVM_CTRL_INTERCEPT_POPF RT_BIT_64(17)
412/** Intercept CPUID instruction. */
413#define SVM_CTRL_INTERCEPT_CPUID RT_BIT_64(18)
414/** Intercept RSM instruction. */
415#define SVM_CTRL_INTERCEPT_RSM RT_BIT_64(19)
416/** Intercept IRET instruction. */
417#define SVM_CTRL_INTERCEPT_IRET RT_BIT_64(20)
418/** Intercept INTn instruction. */
419#define SVM_CTRL_INTERCEPT_INTN RT_BIT_64(21)
420/** Intercept INVD instruction. */
421#define SVM_CTRL_INTERCEPT_INVD RT_BIT_64(22)
422/** Intercept PAUSE instruction. */
423#define SVM_CTRL_INTERCEPT_PAUSE RT_BIT_64(23)
424/** Intercept HLT instruction. */
425#define SVM_CTRL_INTERCEPT_HLT RT_BIT_64(24)
426/** Intercept INVLPG instruction. */
427#define SVM_CTRL_INTERCEPT_INVLPG RT_BIT_64(25)
428/** Intercept INVLPGA instruction. */
429#define SVM_CTRL_INTERCEPT_INVLPGA RT_BIT_64(26)
430/** IOIO_PROT Intercept IN/OUT accesses to selected ports. */
431#define SVM_CTRL_INTERCEPT_IOIO_PROT RT_BIT_64(27)
432/** MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
433#define SVM_CTRL_INTERCEPT_MSR_PROT RT_BIT_64(28)
434/** Intercept task switches. */
435#define SVM_CTRL_INTERCEPT_TASK_SWITCH RT_BIT_64(29)
436/** FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
437#define SVM_CTRL_INTERCEPT_FERR_FREEZE RT_BIT_64(30)
438/** Intercept shutdown events. */
439#define SVM_CTRL_INTERCEPT_SHUTDOWN RT_BIT_64(31)
440/** Intercept VMRUN instruction. */
441#define SVM_CTRL_INTERCEPT_VMRUN RT_BIT_64(32 + 0)
442/** Intercept VMMCALL instruction. */
443#define SVM_CTRL_INTERCEPT_VMMCALL RT_BIT_64(32 + 1)
444/** Intercept VMLOAD instruction. */
445#define SVM_CTRL_INTERCEPT_VMLOAD RT_BIT_64(32 + 2)
446/** Intercept VMSAVE instruction. */
447#define SVM_CTRL_INTERCEPT_VMSAVE RT_BIT_64(32 + 3)
448/** Intercept STGI instruction. */
449#define SVM_CTRL_INTERCEPT_STGI RT_BIT_64(32 + 4)
450/** Intercept CLGI instruction. */
451#define SVM_CTRL_INTERCEPT_CLGI RT_BIT_64(32 + 5)
452/** Intercept SKINIT instruction. */
453#define SVM_CTRL_INTERCEPT_SKINIT RT_BIT_64(32 + 6)
454/** Intercept RDTSCP instruction. */
455#define SVM_CTRL_INTERCEPT_RDTSCP RT_BIT_64(32 + 7)
456/** Intercept ICEBP instruction. */
457#define SVM_CTRL_INTERCEPT_ICEBP RT_BIT_64(32 + 8)
458/** Intercept WBINVD instruction. */
459#define SVM_CTRL_INTERCEPT_WBINVD RT_BIT_64(32 + 9)
460/** Intercept MONITOR instruction. */
461#define SVM_CTRL_INTERCEPT_MONITOR RT_BIT_64(32 + 10)
462/** Intercept MWAIT instruction unconditionally. */
463#define SVM_CTRL_INTERCEPT_MWAIT RT_BIT_64(32 + 11)
464/** Intercept MWAIT instruction when armed. */
465#define SVM_CTRL_INTERCEPT_MWAIT_ARMED RT_BIT_64(32 + 12)
466/** Intercept XSETBV instruction. */
467#define SVM_CTRL_INTERCEPT_XSETBV RT_BIT_64(32 + 13)
468/** Intercept RDPRU instruction. */
469#define SVM_CTRL_INTERCEPT_RDPRU RT_BIT_64(32 + 14)
470/** Intercept EFER writes after guest instruction finishes. */
471#define SVM_CTRL_INTERCEPT_EFER_WRITES_TRAP RT_BIT_64(32 + 15)
472/** Intercept CR0 writes after guest instruction finishes. */
473#define SVM_CTRL_INTERCEPT_CR0_WRITES_TRAP RT_BIT_64(32 + 16)
474/** Intercept CR0 writes after guest instruction finishes. */
475#define SVM_CTRL_INTERCEPT_CR1_WRITES_TRAP RT_BIT_64(32 + 17)
476/** Intercept CR0 writes after guest instruction finishes. */
477#define SVM_CTRL_INTERCEPT_CR2_WRITES_TRAP RT_BIT_64(32 + 18)
478/** Intercept CR0 writes after guest instruction finishes. */
479#define SVM_CTRL_INTERCEPT_CR3_WRITES_TRAP RT_BIT_64(32 + 19)
480/** Intercept CR0 writes after guest instruction finishes. */
481#define SVM_CTRL_INTERCEPT_CR4_WRITES_TRAP RT_BIT_64(32 + 20)
482/** Intercept CR0 writes after guest instruction finishes. */
483#define SVM_CTRL_INTERCEPT_CR5_WRITES_TRAP RT_BIT_64(32 + 21)
484/** Intercept CR0 writes after guest instruction finishes. */
485#define SVM_CTRL_INTERCEPT_CR6_WRITES_TRAP RT_BIT_64(32 + 22)
486/** Intercept CR0 writes after guest instruction finishes. */
487#define SVM_CTRL_INTERCEPT_CR7_WRITES_TRAP RT_BIT_64(32 + 23)
488/** Intercept CR0 writes after guest instruction finishes. */
489#define SVM_CTRL_INTERCEPT_CR8_WRITES_TRAP RT_BIT_64(32 + 24)
490/** Intercept CR0 writes after guest instruction finishes. */
491#define SVM_CTRL_INTERCEPT_CR9_WRITES_TRAP RT_BIT_64(32 + 25)
492/** Intercept CR0 writes after guest instruction finishes. */
493#define SVM_CTRL_INTERCEPT_CR10_WRITES_TRAP RT_BIT_64(32 + 26)
494/** Intercept CR0 writes after guest instruction finishes. */
495#define SVM_CTRL_INTERCEPT_CR11_WRITES_TRAP RT_BIT_64(32 + 27)
496/** Intercept CR0 writes after guest instruction finishes. */
497#define SVM_CTRL_INTERCEPT_CR12_WRITES_TRAP RT_BIT_64(32 + 28)
498/** Intercept CR0 writes after guest instruction finishes. */
499#define SVM_CTRL_INTERCEPT_CR13_WRITES_TRAP RT_BIT_64(32 + 29)
500/** Intercept CR0 writes after guest instruction finishes. */
501#define SVM_CTRL_INTERCEPT_CR14_WRITES_TRAP RT_BIT_64(32 + 30)
502/** Intercept CR0 writes after guest instruction finishes. */
503#define SVM_CTRL_INTERCEPT_CR15_WRITES_TRAP RT_BIT_64(32 + 31)
504/** @} */
505
506/** @name SVMINTCTRL.u3Type
507 * @{
508 */
509/** External or virtual interrupt. */
510#define SVM_EVENT_EXTERNAL_IRQ 0
511/** Non-maskable interrupt. */
512#define SVM_EVENT_NMI 2
513/** Exception; fault or trap. */
514#define SVM_EVENT_EXCEPTION 3
515/** Software interrupt. */
516#define SVM_EVENT_SOFTWARE_INT 4
517/** @} */
518
519/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
520 * @{
521 */
522/** Flush nothing. */
523#define SVM_TLB_FLUSH_NOTHING 0
524/** Flush entire TLB (host+guest entries) */
525#define SVM_TLB_FLUSH_ENTIRE 1
526/** Flush this guest's TLB entries (by ASID) */
527#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
528/** Flush this guest's non-global TLB entries (by ASID) */
529#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
530/** @} */
531
532/**
533 * SVM selector/segment register type.
534 */
535typedef struct
536{
537 uint16_t u16Sel;
538 uint16_t u16Attr;
539 uint32_t u32Limit;
540 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
541} SVMSELREG;
542AssertCompileSize(SVMSELREG, 16);
543/** Pointer to the SVMSELREG struct. */
544typedef SVMSELREG *PSVMSELREG;
545/** Pointer to a const SVMSELREG struct. */
546typedef const SVMSELREG *PCSVMSELREG;
547
548/**
549 * SVM GDTR/IDTR type.
550 */
551typedef struct
552{
553 uint16_t u16Reserved0;
554 uint16_t u16Reserved1;
555 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
556 uint64_t u64Base;
557} SVMXDTR;
558AssertCompileSize(SVMXDTR, 16);
559typedef SVMXDTR SVMIDTR;
560typedef SVMXDTR SVMGDTR;
561/** Pointer to the SVMXDTR struct. */
562typedef SVMXDTR *PSVMXDTR;
563/** Pointer to a const SVMXDTR struct. */
564typedef const SVMXDTR *PCSVMXDTR;
565
566/**
567 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
568 */
569typedef union
570{
571 struct
572 {
573 uint32_t u8Vector : 8;
574 uint32_t u3Type : 3;
575 uint32_t u1ErrorCodeValid : 1;
576 uint32_t u19Reserved : 19;
577 uint32_t u1Valid : 1;
578 uint32_t u32ErrorCode : 32;
579 } n;
580 uint64_t u;
581} SVMEVENT;
582/** Pointer to the SVMEVENT union. */
583typedef SVMEVENT *PSVMEVENT;
584/** Pointer to a const SVMEVENT union. */
585typedef const SVMEVENT *PCSVMEVENT;
586
587/** Gets the event type given an SVMEVENT parameter. */
588#define SVM_EVENT_GET_TYPE(a_SvmEvent) (((a_SvmEvent) >> 8) & 7)
589
590/**
591 * SVM Interrupt control structure (Virtual Interrupt Control).
592 */
593typedef union
594{
595 struct
596 {
597 uint32_t u8VTPR : 8; /* V_TPR */
598 uint32_t u1VIrqPending : 1; /* V_IRQ */
599 uint32_t u1VGif : 1; /* VGIF */
600 uint32_t u6Reserved : 6;
601 uint32_t u4VIntrPrio : 4; /* V_INTR_PRIO */
602 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
603 uint32_t u3Reserved : 3;
604 uint32_t u1VIntrMasking : 1; /* V_INTR_MASKING */
605 uint32_t u1VGifEnable : 1; /* VGIF enable */
606 uint32_t u5Reserved : 5;
607 uint32_t u1AvicEnable : 1; /* AVIC enable */
608 uint32_t u8VIntrVector : 8; /* V_INTR_VECTOR */
609 uint32_t u24Reserved : 24;
610 } n;
611 uint64_t u;
612} SVMINTCTRL;
613/** Pointer to an SVMINTCTRL structure. */
614typedef SVMINTCTRL *PSVMINTCTRL;
615/** Pointer to a const SVMINTCTRL structure. */
616typedef const SVMINTCTRL *PCSVMINTCTRL;
617
618/**
619 * SVM TLB control structure.
620 */
621typedef union
622{
623 struct
624 {
625 uint32_t u32ASID : 32;
626 uint32_t u8TLBFlush : 8;
627 uint32_t u24Reserved : 24;
628 } n;
629 uint64_t u;
630} SVMTLBCTRL;
631
632/**
633 * SVM IOIO exit info. structure (EXITINFO1 for IOIO intercepts).
634 */
635typedef union
636{
637 struct
638 {
639 uint32_t u1Type : 1; /**< Bit 0: 0 = out, 1 = in */
640 uint32_t u1Reserved : 1; /**< Bit 1: Reserved */
641 uint32_t u1Str : 1; /**< Bit 2: String I/O (1) or not (0). */
642 uint32_t u1Rep : 1; /**< Bit 3: Repeat prefixed string I/O. */
643 uint32_t u1Op8 : 1; /**< Bit 4: 8-bit operand. */
644 uint32_t u1Op16 : 1; /**< Bit 5: 16-bit operand. */
645 uint32_t u1Op32 : 1; /**< Bit 6: 32-bit operand. */
646 uint32_t u1Addr16 : 1; /**< Bit 7: 16-bit address size. */
647 uint32_t u1Addr32 : 1; /**< Bit 8: 32-bit address size. */
648 uint32_t u1Addr64 : 1; /**< Bit 9: 64-bit address size. */
649 uint32_t u3Seg : 3; /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
650 uint32_t u3Reserved : 3;
651 uint32_t u16Port : 16; /**< Bits 31:16: Port number. */
652 } n;
653 uint32_t u;
654} SVMIOIOEXITINFO;
655/** Pointer to an SVM IOIO exit info. structure. */
656typedef SVMIOIOEXITINFO *PSVMIOIOEXITINFO;
657/** Pointer to a const SVM IOIO exit info. structure. */
658typedef const SVMIOIOEXITINFO *PCSVMIOIOEXITINFO;
659
660/** 8-bit IO transfer. */
661#define SVM_IOIO_8_BIT_OP RT_BIT_32(4)
662/** 16-bit IO transfer. */
663#define SVM_IOIO_16_BIT_OP RT_BIT_32(5)
664/** 32-bit IO transfer. */
665#define SVM_IOIO_32_BIT_OP RT_BIT_32(6)
666/** Number of bits to shift right to get the operand sizes. */
667#define SVM_IOIO_OP_SIZE_SHIFT 4
668/** Mask of all possible IO transfer sizes. */
669#define SVM_IOIO_OP_SIZE_MASK (SVM_IOIO_8_BIT_OP | SVM_IOIO_16_BIT_OP | SVM_IOIO_32_BIT_OP)
670/** 16-bit address for the IO buffer. */
671#define SVM_IOIO_16_BIT_ADDR RT_BIT_32(7)
672/** 32-bit address for the IO buffer. */
673#define SVM_IOIO_32_BIT_ADDR RT_BIT_32(8)
674/** 64-bit address for the IO buffer. */
675#define SVM_IOIO_64_BIT_ADDR RT_BIT_32(9)
676/** Number of bits to shift right to get the address sizes. */
677#define SVM_IOIO_ADDR_SIZE_SHIFT 7
678/** Mask of all the IO address sizes. */
679#define SVM_IOIO_ADDR_SIZE_MASK (SVM_IOIO_16_BIT_ADDR | SVM_IOIO_32_BIT_ADDR | SVM_IOIO_64_BIT_ADDR)
680/** Number of bits to shift right to get the IO port number. */
681#define SVM_IOIO_PORT_SHIFT 16
682/** IO write. */
683#define SVM_IOIO_WRITE 0
684/** IO read. */
685#define SVM_IOIO_READ 1
686/**
687 * SVM IOIO transfer type.
688 */
689typedef enum
690{
691 SVMIOIOTYPE_OUT = SVM_IOIO_WRITE,
692 SVMIOIOTYPE_IN = SVM_IOIO_READ
693} SVMIOIOTYPE;
694
695/**
696 * SVM AVIC.
697 */
698typedef union
699{
700 struct
701 {
702 RT_GCC_EXTENSION uint64_t u12Reserved0 : 12;
703 RT_GCC_EXTENSION uint64_t u40Addr : 40;
704 RT_GCC_EXTENSION uint64_t u12Reserved1 : 12;
705 } n;
706 uint64_t u;
707} SVMAVIC;
708AssertCompileSize(SVMAVIC, 8);
709
710/**
711 * SVM AVIC PHYSICAL_TABLE pointer.
712 */
713typedef union
714{
715 struct
716 {
717 RT_GCC_EXTENSION uint64_t u8LastGuestCoreId : 8;
718 RT_GCC_EXTENSION uint64_t u4Reserved : 4;
719 RT_GCC_EXTENSION uint64_t u40Addr : 40;
720 RT_GCC_EXTENSION uint64_t u12Reserved : 12;
721 } n;
722 uint64_t u;
723} SVMAVICPHYS;
724AssertCompileSize(SVMAVICPHYS, 8);
725
726/**
727 * SVM Nested Paging struct.
728 */
729typedef union
730{
731 struct
732 {
733 uint32_t u1NestedPaging : 1;
734 uint32_t u1Sev : 1;
735 uint32_t u1SevEs : 1;
736 uint32_t u29Reserved : 29;
737 } n;
738 uint64_t u;
739} SVMNP;
740AssertCompileSize(SVMNP, 8);
741
742/**
743 * SVM Interrupt shadow struct.
744 */
745typedef union
746{
747 struct
748 {
749 uint32_t u1IntShadow : 1;
750 uint32_t u1GuestIntMask : 1;
751 uint32_t u30Reserved : 30;
752 } n;
753 uint64_t u;
754} SVMINTSHADOW;
755AssertCompileSize(SVMINTSHADOW, 8);
756
757/**
758 * SVM LBR virtualization struct.
759 */
760typedef union
761{
762 struct
763 {
764 uint32_t u1LbrVirt : 1;
765 uint32_t u1VirtVmsaveVmload : 1;
766 uint32_t u30Reserved : 30;
767 } n;
768 uint64_t u;
769} SVMLBRVIRT;
770AssertCompileSize(SVMLBRVIRT, 8);
771
772/** Maximum number of bytes in the Guest-instruction bytes field. */
773#define SVM_CTRL_GUEST_INSTR_BYTES_MAX 15
774
775/**
776 * SVM VMCB control area.
777 */
778#pragma pack(1)
779typedef struct
780{
781 /** Offset 0x00 - Intercept reads of CR0-CR15. */
782 uint16_t u16InterceptRdCRx;
783 /** Offset 0x02 - Intercept writes to CR0-CR15. */
784 uint16_t u16InterceptWrCRx;
785 /** Offset 0x04 - Intercept reads of DR0-DR15. */
786 uint16_t u16InterceptRdDRx;
787 /** Offset 0x06 - Intercept writes to DR0-DR15. */
788 uint16_t u16InterceptWrDRx;
789 /** Offset 0x08 - Intercept exception vectors 0-31. */
790 uint32_t u32InterceptXcpt;
791 /** Offset 0x0c - Intercept control. */
792 uint64_t u64InterceptCtrl;
793 /** Offset 0x14-0x3f - Reserved. */
794 uint8_t u8Reserved0[0x3c - 0x14];
795 /** Offset 0x3c - PAUSE filter threshold. */
796 uint16_t u16PauseFilterThreshold;
797 /** Offset 0x3e - PAUSE intercept filter count. */
798 uint16_t u16PauseFilterCount;
799 /** Offset 0x40 - Physical address of IOPM. */
800 uint64_t u64IOPMPhysAddr;
801 /** Offset 0x48 - Physical address of MSRPM. */
802 uint64_t u64MSRPMPhysAddr;
803 /** Offset 0x50 - TSC Offset. */
804 uint64_t u64TSCOffset;
805 /** Offset 0x58 - TLB control field. */
806 SVMTLBCTRL TLBCtrl;
807 /** Offset 0x60 - Interrupt control field. */
808 SVMINTCTRL IntCtrl;
809 /** Offset 0x68 - Interrupt shadow. */
810 SVMINTSHADOW IntShadow;
811 /** Offset 0x70 - Exit code. */
812 uint64_t u64ExitCode;
813 /** Offset 0x78 - Exit info 1. */
814 uint64_t u64ExitInfo1;
815 /** Offset 0x80 - Exit info 2. */
816 uint64_t u64ExitInfo2;
817 /** Offset 0x88 - Exit Interrupt info. */
818 SVMEVENT ExitIntInfo;
819 /** Offset 0x90 - Nested Paging control. */
820 SVMNP NestedPagingCtrl;
821 /** Offset 0x98 - AVIC APIC BAR. */
822 SVMAVIC AvicBar;
823 /** Offset 0xa0-0xa7 - Reserved. */
824 uint8_t u8Reserved1[0xa8 - 0xa0];
825 /** Offset 0xa8 - Event injection. */
826 SVMEVENT EventInject;
827 /** Offset 0xb0 - Host CR3 for nested paging. */
828 uint64_t u64NestedPagingCR3;
829 /** Offset 0xb8 - LBR Virtualization. */
830 SVMLBRVIRT LbrVirt;
831 /** Offset 0xc0 - VMCB Clean Bits. */
832 uint32_t u32VmcbCleanBits;
833 uint32_t u32Reserved0;
834 /** Offset 0xc8 - Next sequential instruction pointer. */
835 uint64_t u64NextRIP;
836 /** Offset 0xd0 - Number of bytes fetched. */
837 uint8_t cbInstrFetched;
838 /** Offset 0xd1 - Guest instruction bytes. */
839 uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
840 /** Offset 0xe0 - AVIC APIC_BACKING_PAGE pointer. */
841 SVMAVIC AvicBackingPagePtr;
842 /** Offset 0xe8-0xef - Reserved. */
843 uint8_t u8Reserved2[0xf0 - 0xe8];
844 /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
845 SVMAVIC AvicLogicalTablePtr;
846 /** Offset 0xf8 - AVIC PHYSICAL_TABLE pointer. */
847 SVMAVICPHYS AvicPhysicalTablePtr;
848} SVMVMCBCTRL;
849#pragma pack()
850/** Pointer to the SVMVMCBSTATESAVE structure. */
851typedef SVMVMCBCTRL *PSVMVMCBCTRL;
852/** Pointer to a const SVMVMCBSTATESAVE structure. */
853typedef const SVMVMCBCTRL *PCSVMVMCBCTRL;
854AssertCompileSize(SVMVMCBCTRL, 0x100);
855AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdCRx, 0x00);
856AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrCRx, 0x02);
857AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptRdDRx, 0x04);
858AssertCompileMemberOffset(SVMVMCBCTRL, u16InterceptWrDRx, 0x06);
859AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt, 0x08);
860AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl, 0x0c);
861AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0, 0x14);
862AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
863AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount, 0x3e);
864AssertCompileMemberOffset(SVMVMCBCTRL, u64IOPMPhysAddr, 0x40);
865AssertCompileMemberOffset(SVMVMCBCTRL, u64MSRPMPhysAddr, 0x48);
866AssertCompileMemberOffset(SVMVMCBCTRL, u64TSCOffset, 0x50);
867AssertCompileMemberOffset(SVMVMCBCTRL, TLBCtrl, 0x58);
868AssertCompileMemberOffset(SVMVMCBCTRL, IntCtrl, 0x60);
869AssertCompileMemberOffset(SVMVMCBCTRL, IntShadow, 0x68);
870AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitCode, 0x70);
871AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo1, 0x78);
872AssertCompileMemberOffset(SVMVMCBCTRL, u64ExitInfo2, 0x80);
873AssertCompileMemberOffset(SVMVMCBCTRL, ExitIntInfo, 0x88);
874AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl, 0x90);
875AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar, 0x98);
876AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1, 0xa0);
877AssertCompileMemberOffset(SVMVMCBCTRL, EventInject, 0xa8);
878AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3, 0xb0);
879AssertCompileMemberOffset(SVMVMCBCTRL, LbrVirt, 0xb8);
880AssertCompileMemberOffset(SVMVMCBCTRL, u32VmcbCleanBits, 0xc0);
881AssertCompileMemberOffset(SVMVMCBCTRL, u64NextRIP, 0xc8);
882AssertCompileMemberOffset(SVMVMCBCTRL, cbInstrFetched, 0xd0);
883AssertCompileMemberOffset(SVMVMCBCTRL, abInstr, 0xd1);
884AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr, 0xe0);
885AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2, 0xe8);
886AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr, 0xf0);
887AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr, 0xf8);
888AssertCompileMemberSize(SVMVMCBCTRL, abInstr, 0x0f);
889
890/**
891 * SVM VMCB state save area.
892 */
893#pragma pack(1)
894typedef struct
895{
896 /** Offset 0x400 - Guest ES register + hidden parts. */
897 SVMSELREG ES;
898 /** Offset 0x410 - Guest CS register + hidden parts. */
899 SVMSELREG CS;
900 /** Offset 0x420 - Guest SS register + hidden parts. */
901 SVMSELREG SS;
902 /** Offset 0x430 - Guest DS register + hidden parts. */
903 SVMSELREG DS;
904 /** Offset 0x440 - Guest FS register + hidden parts. */
905 SVMSELREG FS;
906 /** Offset 0x450 - Guest GS register + hidden parts. */
907 SVMSELREG GS;
908 /** Offset 0x460 - Guest GDTR register. */
909 SVMGDTR GDTR;
910 /** Offset 0x470 - Guest LDTR register + hidden parts. */
911 SVMSELREG LDTR;
912 /** Offset 0x480 - Guest IDTR register. */
913 SVMIDTR IDTR;
914 /** Offset 0x490 - Guest TR register + hidden parts. */
915 SVMSELREG TR;
916 /** Offset 0x4A0-0x4CA - Reserved. */
917 uint8_t u8Reserved0[0x4cb - 0x4a0];
918 /** Offset 0x4CB - CPL. */
919 uint8_t u8CPL;
920 /** Offset 0x4CC-0x4CF - Reserved. */
921 uint8_t u8Reserved1[0x4d0 - 0x4cc];
922 /** Offset 0x4D0 - EFER. */
923 uint64_t u64EFER;
924 /** Offset 0x4D8-0x547 - Reserved. */
925 uint8_t u8Reserved2[0x548 - 0x4d8];
926 /** Offset 0x548 - CR4. */
927 uint64_t u64CR4;
928 /** Offset 0x550 - CR3. */
929 uint64_t u64CR3;
930 /** Offset 0x558 - CR0. */
931 uint64_t u64CR0;
932 /** Offset 0x560 - DR7. */
933 uint64_t u64DR7;
934 /** Offset 0x568 - DR6. */
935 uint64_t u64DR6;
936 /** Offset 0x570 - RFLAGS. */
937 uint64_t u64RFlags;
938 /** Offset 0x578 - RIP. */
939 uint64_t u64RIP;
940 /** Offset 0x580-0x5D7 - Reserved. */
941 uint8_t u8Reserved3[0x5d8 - 0x580];
942 /** Offset 0x5D8 - RSP. */
943 uint64_t u64RSP;
944 /** Offset 0x5E0-0x5F7 - Reserved. */
945 uint8_t u8Reserved4[0x5f8 - 0x5e0];
946 /** Offset 0x5F8 - RAX. */
947 uint64_t u64RAX;
948 /** Offset 0x600 - STAR. */
949 uint64_t u64STAR;
950 /** Offset 0x608 - LSTAR. */
951 uint64_t u64LSTAR;
952 /** Offset 0x610 - CSTAR. */
953 uint64_t u64CSTAR;
954 /** Offset 0x618 - SFMASK. */
955 uint64_t u64SFMASK;
956 /** Offset 0x620 - KernelGSBase. */
957 uint64_t u64KernelGSBase;
958 /** Offset 0x628 - SYSENTER_CS. */
959 uint64_t u64SysEnterCS;
960 /** Offset 0x630 - SYSENTER_ESP. */
961 uint64_t u64SysEnterESP;
962 /** Offset 0x638 - SYSENTER_EIP. */
963 uint64_t u64SysEnterEIP;
964 /** Offset 0x640 - CR2. */
965 uint64_t u64CR2;
966 /** Offset 0x648-0x667 - Reserved. */
967 uint8_t u8Reserved5[0x668 - 0x648];
968 /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
969 uint64_t u64PAT;
970 /** Offset 0x670 - DBGCTL. */
971 uint64_t u64DBGCTL;
972 /** Offset 0x678 - BR_FROM. */
973 uint64_t u64BR_FROM;
974 /** Offset 0x680 - BR_TO. */
975 uint64_t u64BR_TO;
976 /** Offset 0x688 - LASTEXCPFROM. */
977 uint64_t u64LASTEXCPFROM;
978 /** Offset 0x690 - LASTEXCPTO. */
979 uint64_t u64LASTEXCPTO;
980} SVMVMCBSTATESAVE;
981#pragma pack()
982/** Pointer to the SVMVMCBSTATESAVE structure. */
983typedef SVMVMCBSTATESAVE *PSVMVMCBSTATESAVE;
984/** Pointer to a const SVMVMCBSTATESAVE structure. */
985typedef const SVMVMCBSTATESAVE *PCSVMVMCBSTATESAVE;
986AssertCompileSize(SVMVMCBSTATESAVE, 0x298);
987AssertCompileMemberOffset(SVMVMCBSTATESAVE, ES, 0x400 - 0x400);
988AssertCompileMemberOffset(SVMVMCBSTATESAVE, CS, 0x410 - 0x400);
989AssertCompileMemberOffset(SVMVMCBSTATESAVE, SS, 0x420 - 0x400);
990AssertCompileMemberOffset(SVMVMCBSTATESAVE, DS, 0x430 - 0x400);
991AssertCompileMemberOffset(SVMVMCBSTATESAVE, FS, 0x440 - 0x400);
992AssertCompileMemberOffset(SVMVMCBSTATESAVE, GS, 0x450 - 0x400);
993AssertCompileMemberOffset(SVMVMCBSTATESAVE, GDTR, 0x460 - 0x400);
994AssertCompileMemberOffset(SVMVMCBSTATESAVE, LDTR, 0x470 - 0x400);
995AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR, 0x480 - 0x400);
996AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR, 0x490 - 0x400);
997AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0, 0x4a0 - 0x400);
998AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL, 0x4cb - 0x400);
999AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1, 0x4cc - 0x400);
1000AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER, 0x4d0 - 0x400);
1001AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2, 0x4d8 - 0x400);
1002AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4, 0x548 - 0x400);
1003AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3, 0x550 - 0x400);
1004AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR0, 0x558 - 0x400);
1005AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR7, 0x560 - 0x400);
1006AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DR6, 0x568 - 0x400);
1007AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags, 0x570 - 0x400);
1008AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP, 0x578 - 0x400);
1009AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3, 0x580 - 0x400);
1010AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP, 0x5d8 - 0x400);
1011AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4, 0x5e0 - 0x400);
1012AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX, 0x5f8 - 0x400);
1013AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR, 0x600 - 0x400);
1014AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LSTAR, 0x608 - 0x400);
1015AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CSTAR, 0x610 - 0x400);
1016AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SFMASK, 0x618 - 0x400);
1017AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64KernelGSBase, 0x620 - 0x400);
1018AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterCS, 0x628 - 0x400);
1019AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterESP, 0x630 - 0x400);
1020AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP, 0x638 - 0x400);
1021AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2, 0x640 - 0x400);
1022AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5, 0x648 - 0x400);
1023AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT, 0x668 - 0x400);
1024AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL, 0x670 - 0x400);
1025AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_FROM, 0x678 - 0x400);
1026AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64BR_TO, 0x680 - 0x400);
1027AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPFROM, 0x688 - 0x400);
1028AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64LASTEXCPTO, 0x690 - 0x400);
1029
1030/**
1031 * SVM VM Control Block. (VMCB)
1032 */
1033#pragma pack(1)
1034typedef struct SVMVMCB
1035{
1036 /** Offset 0x00 - Control area. */
1037 SVMVMCBCTRL ctrl;
1038 /** Offset 0x100-0x3FF - Reserved. */
1039 uint8_t u8Reserved0[0x400 - 0x100];
1040 /** Offset 0x400 - State save area. */
1041 SVMVMCBSTATESAVE guest;
1042 /** Offset 0x698-0xFFF- Reserved. */
1043 uint8_t u8Reserved1[0x1000 - 0x698];
1044} SVMVMCB;
1045#pragma pack()
1046/** Pointer to the SVMVMCB structure. */
1047typedef SVMVMCB *PSVMVMCB;
1048/** Pointer to a const SVMVMCB structure. */
1049typedef const SVMVMCB *PCSVMVMCB;
1050AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
1051AssertCompileMemberOffset(SVMVMCB, u8Reserved0, 0x100);
1052AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
1053AssertCompileMemberOffset(SVMVMCB, u8Reserved1, 0x698);
1054AssertCompileSize(SVMVMCB, 0x1000);
1055
1056/**
1057 * SVM MSRs.
1058 */
1059typedef struct SVMMSRS
1060{
1061 /** HWCR MSR. */
1062 uint64_t u64MsrHwcr;
1063 /** Reserved for future. */
1064 uint64_t u64Padding[27];
1065} SVMMSRS;
1066AssertCompileSizeAlignment(SVMMSRS, 8);
1067AssertCompileSize(SVMMSRS, 224);
1068/** Pointer to a SVMMSRS struct. */
1069typedef SVMMSRS *PSVMMSRS;
1070/** Pointer to a const SVMMSRS struct. */
1071typedef const SVMMSRS *PCSVMMSRS;
1072
1073/**
1074 * SVM VM-exit auxiliary information.
1075 *
1076 * This includes information that isn't necessarily stored in the guest-CPU
1077 * context but provided as part of \#VMEXITs.
1078 */
1079typedef struct
1080{
1081 uint64_t u64ExitCode;
1082 uint64_t u64ExitInfo1;
1083 uint64_t u64ExitInfo2;
1084 SVMEVENT ExitIntInfo;
1085} SVMEXITAUX;
1086/** Pointer to a SVMEXITAUX struct. */
1087typedef SVMEXITAUX *PSVMEXITAUX;
1088/** Pointer to a const SVMEXITAUX struct. */
1089typedef const SVMEXITAUX *PCSVMEXITAUX;
1090
1091/**
1092 * Segment attribute conversion between CPU and AMD-V VMCB format.
1093 *
1094 * The CPU format of the segment attribute is described in X86DESCATTRBITS
1095 * which is 16-bits (i.e. includes 4 bits of the segment limit).
1096 *
1097 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
1098 * only the attribute bits and nothing else). Upper 4-bits are unused.
1099 */
1100#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
1101#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
1102
1103/** @def HMSVM_SEG_REG_COPY_TO_VMCB
1104 * Copies the specified segment register to a VMCB from a virtual CPU context.
1105 *
1106 * @param a_pCtx The virtual-CPU context.
1107 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1108 * @param a_REG The segment register in the VMCB state-save
1109 * struct (ES/CS/SS/DS).
1110 * @param a_reg The segment register in the virtual CPU struct
1111 * (es/cs/ss/ds).
1112 */
1113#define HMSVM_SEG_REG_COPY_TO_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1114 do \
1115 { \
1116 Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID); \
1117 Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel); \
1118 (a_pVmcbStateSave)->a_REG.u16Sel = (a_pCtx)->a_reg.Sel; \
1119 (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
1120 (a_pVmcbStateSave)->a_REG.u64Base = (a_pCtx)->a_reg.u64Base; \
1121 (a_pVmcbStateSave)->a_REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
1122 } while (0)
1123
1124/** @def HMSVM_SEG_REG_COPY_FROM_VMCB
1125 * Copies the specified segment register from the VMCB to a virtual CPU
1126 * context.
1127 *
1128 * @param a_pCtx The virtual-CPU context.
1129 * @param a_pVmcbStateSave Pointer to the VMCB state-save area.
1130 * @param a_REG The segment register in the VMCB state-save
1131 * struct (ES/CS/SS/DS).
1132 * @param a_reg The segment register in the virtual CPU struct
1133 * (es/ds/ss/ds).
1134 */
1135#define HMSVM_SEG_REG_COPY_FROM_VMCB(a_pCtx, a_pVmcbStateSave, a_REG, a_reg) \
1136 do \
1137 { \
1138 (a_pCtx)->a_reg.Sel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1139 (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel; \
1140 (a_pCtx)->a_reg.fFlags = CPUMSELREG_FLAGS_VALID; \
1141 (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
1142 (a_pCtx)->a_reg.u64Base = (a_pVmcbStateSave)->a_REG.u64Base; \
1143 (a_pCtx)->a_reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
1144 } while (0)
1145
1146
1147/** @defgroup grp_hm_svm_hwexec SVM Hardware-assisted execution Helpers
1148 *
1149 * These functions are only here because the inline functions in cpum.h calls them.
1150 * Don't add any more functions here unless there is no other option.
1151 * @{
1152 */
1153VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts);
1154VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1155VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1156VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1157VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts);
1158VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts);
1159VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking);
1160VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPagingCtrl);
1161VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount);
1162VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset);
1163/** @} */
1164
1165
1166/** @} */
1167
1168#endif /* !VBOX_INCLUDED_vmm_hm_svm_h */
1169
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