hm_svm.h@ 46314

Last change on this file since 46314 was 46314, checked in by vboxsync, 12 years ago
VMM/HM: AMD-V bits. Get rid of unnecessary pragma packs and use 'u' instead of 'au64[1]' of the structure sizing.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 28.8 KB

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1	/** @file
2	* HM - SVM Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2013 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_svm_h
27	#define ___VBox_vmm_svm_h
28
29	#include <VBox/types.h>
30	#include <VBox/err.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33
34	/** @defgroup grp_svm svm Types and Definitions
35	* @ingroup grp_hm
36	* @{
37	*/
38
39	/** @name SVM features for cpuid 0x8000000a
40	* @{
41	*/
42	/** Bit 0 - NP - Nested Paging supported. */
43	#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
44	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
45	#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
46	/** Bit 2 - SVML - SVM locking bit supported. */
47	#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
48	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
49	#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
50	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
51	#define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
52	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
53	#define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
54	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
55	* VMCB.TLB_Control is supported. */
56	#define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
57	/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
58	#define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
59	/** Where did we get this from? */
60	#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
61	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
62	#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
63	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
64	* intercept filter cycle count threshold. */
65	#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
66	/** @} */
67
68
69	/** @name SVM Basic Exit Reasons.
70	* @{
71	*/
72	/** Invalid guest state in VMCB. */
73	#define SVM_EXIT_INVALID -1
74	/** Read from CR0-CR15. */
75	#define SVM_EXIT_READ_CR0 0x0
76	#define SVM_EXIT_READ_CR1 0x1
77	#define SVM_EXIT_READ_CR2 0x2
78	#define SVM_EXIT_READ_CR3 0x3
79	#define SVM_EXIT_READ_CR4 0x4
80	#define SVM_EXIT_READ_CR5 0x5
81	#define SVM_EXIT_READ_CR6 0x6
82	#define SVM_EXIT_READ_CR7 0x7
83	#define SVM_EXIT_READ_CR8 0x8
84	#define SVM_EXIT_READ_CR9 0x9
85	#define SVM_EXIT_READ_CR10 0xA
86	#define SVM_EXIT_READ_CR11 0xB
87	#define SVM_EXIT_READ_CR12 0xC
88	#define SVM_EXIT_READ_CR13 0xD
89	#define SVM_EXIT_READ_CR14 0xE
90	#define SVM_EXIT_READ_CR15 0xF
91	/** Writes to CR0-CR15. */
92	#define SVM_EXIT_WRITE_CR0 0x10
93	#define SVM_EXIT_WRITE_CR1 0x11
94	#define SVM_EXIT_WRITE_CR2 0x12
95	#define SVM_EXIT_WRITE_CR3 0x13
96	#define SVM_EXIT_WRITE_CR4 0x14
97	#define SVM_EXIT_WRITE_CR5 0x15
98	#define SVM_EXIT_WRITE_CR6 0x16
99	#define SVM_EXIT_WRITE_CR7 0x17
100	#define SVM_EXIT_WRITE_CR8 0x18
101	#define SVM_EXIT_WRITE_CR9 0x19
102	#define SVM_EXIT_WRITE_CR10 0x1A
103	#define SVM_EXIT_WRITE_CR11 0x1B
104	#define SVM_EXIT_WRITE_CR12 0x1C
105	#define SVM_EXIT_WRITE_CR13 0x1D
106	#define SVM_EXIT_WRITE_CR14 0x1E
107	#define SVM_EXIT_WRITE_CR15 0x1F
108	/** Read from DR0-DR15. */
109	#define SVM_EXIT_READ_DR0 0x20
110	#define SVM_EXIT_READ_DR1 0x21
111	#define SVM_EXIT_READ_DR2 0x22
112	#define SVM_EXIT_READ_DR3 0x23
113	#define SVM_EXIT_READ_DR4 0x24
114	#define SVM_EXIT_READ_DR5 0x25
115	#define SVM_EXIT_READ_DR6 0x26
116	#define SVM_EXIT_READ_DR7 0x27
117	#define SVM_EXIT_READ_DR8 0x28
118	#define SVM_EXIT_READ_DR9 0x29
119	#define SVM_EXIT_READ_DR10 0x2A
120	#define SVM_EXIT_READ_DR11 0x2B
121	#define SVM_EXIT_READ_DR12 0x2C
122	#define SVM_EXIT_READ_DR13 0x2D
123	#define SVM_EXIT_READ_DR14 0x2E
124	#define SVM_EXIT_READ_DR15 0x2F
125	/** Writes to DR0-DR15. */
126	#define SVM_EXIT_WRITE_DR0 0x30
127	#define SVM_EXIT_WRITE_DR1 0x31
128	#define SVM_EXIT_WRITE_DR2 0x32
129	#define SVM_EXIT_WRITE_DR3 0x33
130	#define SVM_EXIT_WRITE_DR4 0x34
131	#define SVM_EXIT_WRITE_DR5 0x35
132	#define SVM_EXIT_WRITE_DR6 0x36
133	#define SVM_EXIT_WRITE_DR7 0x37
134	#define SVM_EXIT_WRITE_DR8 0x38
135	#define SVM_EXIT_WRITE_DR9 0x39
136	#define SVM_EXIT_WRITE_DR10 0x3A
137	#define SVM_EXIT_WRITE_DR11 0x3B
138	#define SVM_EXIT_WRITE_DR12 0x3C
139	#define SVM_EXIT_WRITE_DR13 0x3D
140	#define SVM_EXIT_WRITE_DR14 0x3E
141	#define SVM_EXIT_WRITE_DR15 0x3F
142	/* Exception 0-31. */
143	#define SVM_EXIT_EXCEPTION_0 0x40
144	#define SVM_EXIT_EXCEPTION_1 0x41
145	#define SVM_EXIT_EXCEPTION_2 0x42
146	#define SVM_EXIT_EXCEPTION_3 0x43
147	#define SVM_EXIT_EXCEPTION_4 0x44
148	#define SVM_EXIT_EXCEPTION_5 0x45
149	#define SVM_EXIT_EXCEPTION_6 0x46
150	#define SVM_EXIT_EXCEPTION_7 0x47
151	#define SVM_EXIT_EXCEPTION_8 0x48
152	#define SVM_EXIT_EXCEPTION_9 0x49
153	#define SVM_EXIT_EXCEPTION_A 0x4A
154	#define SVM_EXIT_EXCEPTION_B 0x4B
155	#define SVM_EXIT_EXCEPTION_C 0x4C
156	#define SVM_EXIT_EXCEPTION_D 0x4D
157	#define SVM_EXIT_EXCEPTION_E 0x4E
158	#define SVM_EXIT_EXCEPTION_F 0x4F
159	#define SVM_EXIT_EXCEPTION_10 0x50
160	#define SVM_EXIT_EXCEPTION_11 0x51
161	#define SVM_EXIT_EXCEPTION_12 0x52
162	#define SVM_EXIT_EXCEPTION_13 0x53
163	#define SVM_EXIT_EXCEPTION_14 0x54
164	#define SVM_EXIT_EXCEPTION_15 0x55
165	#define SVM_EXIT_EXCEPTION_16 0x56
166	#define SVM_EXIT_EXCEPTION_17 0x57
167	#define SVM_EXIT_EXCEPTION_18 0x58
168	#define SVM_EXIT_EXCEPTION_19 0x59
169	#define SVM_EXIT_EXCEPTION_1A 0x5A
170	#define SVM_EXIT_EXCEPTION_1B 0x5B
171	#define SVM_EXIT_EXCEPTION_1C 0x5C
172	#define SVM_EXIT_EXCEPTION_1D 0x5D
173	#define SVM_EXIT_EXCEPTION_1E 0x5E
174	#define SVM_EXIT_EXCEPTION_1F 0x5F
175	/** Physical maskable interrupt. */
176	#define SVM_EXIT_INTR 0x60
177	/** Non-maskable interrupt. */
178	#define SVM_EXIT_NMI 0x61
179	/** System Management interrupt. */
180	#define SVM_EXIT_SMI 0x62
181	/** Physical INIT signal. */
182	#define SVM_EXIT_INIT 0x63
183	/** Virtual interrupt. */
184	#define SVM_EXIT_VINTR 0x64
185	/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
186	#define SVM_EXIT_CR0_SEL_WRITE 0x65
187	/** IDTR read. */
188	#define SVM_EXIT_IDTR_READ 0x66
189	/** GDTR read. */
190	#define SVM_EXIT_GDTR_READ 0x67
191	/** LDTR read. */
192	#define SVM_EXIT_LDTR_READ 0x68
193	/** TR read. */
194	#define SVM_EXIT_TR_READ 0x69
195	/** IDTR write. */
196	#define SVM_EXIT_IDTR_WRITE 0x6A
197	/** GDTR write. */
198	#define SVM_EXIT_GDTR_WRITE 0x6B
199	/** LDTR write. */
200	#define SVM_EXIT_LDTR_WRITE 0x6C
201	/** TR write. */
202	#define SVM_EXIT_TR_WRITE 0x6D
203	/** RDTSC instruction. */
204	#define SVM_EXIT_RDTSC 0x6E
205	/** RDPMC instruction. */
206	#define SVM_EXIT_RDPMC 0x6F
207	/** PUSHF instruction. */
208	#define SVM_EXIT_PUSHF 0x70
209	/** POPF instruction. */
210	#define SVM_EXIT_POPF 0x71
211	/** CPUID instruction. */
212	#define SVM_EXIT_CPUID 0x72
213	/** RSM instruction. */
214	#define SVM_EXIT_RSM 0x73
215	/** IRET instruction. */
216	#define SVM_EXIT_IRET 0x74
217	/** software interrupt (INTn instructions). */
218	#define SVM_EXIT_SWINT 0x75
219	/** INVD instruction. */
220	#define SVM_EXIT_INVD 0x76
221	/** PAUSE instruction. */
222	#define SVM_EXIT_PAUSE 0x77
223	/** HLT instruction. */
224	#define SVM_EXIT_HLT 0x78
225	/** INVLPG instructions. */
226	#define SVM_EXIT_INVLPG 0x79
227	/** INVLPGA instruction. */
228	#define SVM_EXIT_INVLPGA 0x7A
229	/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
230	#define SVM_EXIT_IOIO 0x7B
231	/** RDMSR or WRMSR access to protected MSR. */
232	#define SVM_EXIT_MSR 0x7C
233	/** task switch. */
234	#define SVM_EXIT_TASK_SWITCH 0x7D
235	/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
236	#define SVM_EXIT_FERR_FREEZE 0x7E
237	/** Shutdown. */
238	#define SVM_EXIT_SHUTDOWN 0x7F
239	/** VMRUN instruction. */
240	#define SVM_EXIT_VMRUN 0x80
241	/** VMMCALL instruction. */
242	#define SVM_EXIT_VMMCALL 0x81
243	/** VMLOAD instruction. */
244	#define SVM_EXIT_VMLOAD 0x82
245	/** VMSAVE instruction. */
246	#define SVM_EXIT_VMSAVE 0x83
247	/** STGI instruction. */
248	#define SVM_EXIT_STGI 0x84
249	/** CLGI instruction. */
250	#define SVM_EXIT_CLGI 0x85
251	/** SKINIT instruction. */
252	#define SVM_EXIT_SKINIT 0x86
253	/** RDTSCP instruction. */
254	#define SVM_EXIT_RDTSCP 0x87
255	/** ICEBP instruction. */
256	#define SVM_EXIT_ICEBP 0x88
257	/** WBINVD instruction. */
258	#define SVM_EXIT_WBINVD 0x89
259	/** MONITOR instruction. */
260	#define SVM_EXIT_MONITOR 0x8A
261	/** MWAIT instruction uncond. */
262	#define SVM_EXIT_MWAIT_UNCOND 0x8B
263	/** MWAIT instruction when armed. */
264	#define SVM_EXIT_MWAIT_ARMED 0x8C
265	/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
266	#define SVM_EXIT_NPF 0x400
267
268	/** @} */
269
270
271	/** @name SVMVMCB.u64ExitInfo2
272	* @{
273	*/
274	/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
275	#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
276	/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
277	#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
278	/** Set to 1 if the task switch has an error code; else cleared to 0. */
279	#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
280	/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
281	#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
282	/** @} */
283
284	/** @name SVMVMCB.ctrl.u32InterceptCtrl1
285	* @{
286	*/
287	/** 0 Intercept INTR (physical maskable interrupt). */
288	#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
289	/** 1 Intercept NMI. */
290	#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
291	/** 2 Intercept SMI. */
292	#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
293	/** 3 Intercept INIT. */
294	#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
295	/** 4 Intercept VINTR (virtual maskable interrupt). */
296	#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
297	/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
298	#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
299	/** 6 Intercept reads of IDTR. */
300	#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
301	/** 7 Intercept reads of GDTR. */
302	#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
303	/** 8 Intercept reads of LDTR. */
304	#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
305	/** 9 Intercept reads of TR. */
306	#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
307	/** 10 Intercept writes of IDTR. */
308	#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
309	/** 11 Intercept writes of GDTR. */
310	#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
311	/** 12 Intercept writes of LDTR. */
312	#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
313	/** 13 Intercept writes of TR. */
314	#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
315	/** 14 Intercept RDTSC instruction. */
316	#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
317	/** 15 Intercept RDPMC instruction. */
318	#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
319	/** 16 Intercept PUSHF instruction. */
320	#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
321	/** 17 Intercept POPF instruction. */
322	#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
323	/** 18 Intercept CPUID instruction. */
324	#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
325	/** 19 Intercept RSM instruction. */
326	#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
327	/** 20 Intercept IRET instruction. */
328	#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
329	/** 21 Intercept INTn instruction. */
330	#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
331	/** 22 Intercept INVD instruction. */
332	#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
333	/** 23 Intercept PAUSE instruction. */
334	#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
335	/** 24 Intercept HLT instruction. */
336	#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
337	/** 25 Intercept INVLPG instruction. */
338	#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
339	/** 26 Intercept INVLPGA instruction. */
340	#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
341	/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
342	#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
343	/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
344	#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
345	/** 29 Intercept task switches. */
346	#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
347	/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
348	#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
349	/** 31 Intercept shutdown events. */
350	#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
351	/** @} */
352
353
354	/** @name SVMVMCB.ctrl.u32InterceptCtrl2
355	* @{
356	*/
357	/** 0 Intercept VMRUN instruction. */
358	#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
359	/** 1 Intercept VMMCALL instruction. */
360	#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
361	/** 2 Intercept VMLOAD instruction. */
362	#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
363	/** 3 Intercept VMSAVE instruction. */
364	#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
365	/** 4 Intercept STGI instruction. */
366	#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
367	/** 5 Intercept CLGI instruction. */
368	#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
369	/** 6 Intercept SKINIT instruction. */
370	#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
371	/** 7 Intercept RDTSCP instruction. */
372	#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
373	/** 8 Intercept ICEBP instruction. */
374	#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
375	/** 9 Intercept WBINVD instruction. */
376	#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
377	/** 10 Intercept MONITOR instruction. */
378	#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
379	/** 11 Intercept MWAIT instruction unconditionally. */
380	#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
381	/** 12 Intercept MWAIT instruction when armed. */
382	#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
383	/** 13 Intercept XSETBV instruction. */
384	#define SVM_CTRL2_INTERCEPT_XSETBV RT_BIT(13)
385	/** @} */
386
387	/** @name SVMVMCB.ctrl.u64NestedPaging
388	* @{
389	*/
390	#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
391	/** @} */
392
393	/** @name SVMVMCB.ctrl.u64IntShadow
394	* @{
395	*/
396	#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
397	/** @} */
398
399
400	/** @name SVMINTCTRL.u3Type
401	* @{
402	*/
403	/** External or virtual interrupt. */
404	#define SVM_EVENT_EXTERNAL_IRQ 0
405	/** Non-maskable interrupt. */
406	#define SVM_EVENT_NMI 2
407	/** Exception; fault or trap. */
408	#define SVM_EVENT_EXCEPTION 3
409	/** Software interrupt. */
410	#define SVM_EVENT_SOFTWARE_INT 4
411	/** @} */
412
413
414	/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
415	* @{
416	*/
417	/** Flush nothing. */
418	#define SVM_TLB_FLUSH_NOTHING 0
419	/** Flush entire TLB (host+guest entries) */
420	#define SVM_TLB_FLUSH_ENTIRE 1
421	/** Flush this guest's TLB entries (by ASID) */
422	#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
423	/** Flush this guest's non-global TLB entries (by ASID) */
424	#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
425	/** @} */
426
427
428	/**
429	* SVM Selector type; includes hidden parts.
430	*/
431	#pragma pack(1)
432	typedef struct
433	{
434	uint16_t u16Sel;
435	uint16_t u16Attr;
436	uint32_t u32Limit;
437	uint64_t u64Base; /*< Only lower 32 bits are implemented for CS, DS, ES & SS. /
438	} SVMSEL;
439	#pragma pack()
440
441	/**
442	* SVM GDTR/IDTR type.
443	*/
444	#pragma pack(1)
445	typedef struct
446	{
447	uint16_t u16Reserved1;
448	uint16_t u16Reserved2;
449	uint32_t u32Limit; /*< Only lower 16 bits are implemented. /
450	uint64_t u64Base;
451	} SVMGDTR;
452	#pragma pack()
453
454	typedef SVMGDTR SVMIDTR;
455
456	/**
457	* SVM Event injection structure (EVENTINJ and EXITINTINFO).
458	*/
459	typedef union
460	{
461	struct
462	{
463	uint32_t u8Vector : 8;
464	uint32_t u3Type : 3;
465	uint32_t u1ErrorCodeValid : 1;
466	uint32_t u19Reserved : 19;
467	uint32_t u1Valid : 1;
468	uint32_t u32ErrorCode : 32;
469	} n;
470	uint64_t u;
471	} SVMEVENT;
472
473
474	/**
475	* SVM Interrupt control structure (Virtual Interrupt Control).
476	*/
477	typedef union
478	{
479	struct
480	{
481	uint32_t u8VTPR : 8;
482	uint32_t u1VIrqValid : 1;
483	uint32_t u7Reserved : 7;
484	uint32_t u4VIrqPriority : 4;
485	uint32_t u1IgnoreTPR : 1;
486	uint32_t u3Reserved : 3;
487	uint32_t u1VIrqMasking : 1;
488	uint32_t u6Reserved : 6;
489	uint32_t u1AvicEnable : 1;
490	uint32_t u8VIrqVector : 8;
491	uint32_t u24Reserved : 24;
492	} n;
493	uint64_t u;
494	} SVMINTCTRL;
495
496	/**
497	* SVM TLB control structure.
498	*/
499	typedef union
500	{
501	struct
502	{
503	uint32_t u32ASID : 32;
504	uint32_t u8TLBFlush : 8;
505	uint32_t u24Reserved : 24;
506	} n;
507	uint64_t u;
508	} SVMTLBCTRL;
509
510	/**
511	* SVM IOIO exit structure (EXITINFO1 for IOIO intercepts).
512	*/
513	typedef union
514	{
515	struct
516	{
517	uint32_t u1Type : 1; /*< 0 = out, 1 = in /
518	uint32_t u1Reserved : 1;
519	uint32_t u1STR : 1;
520	uint32_t u1REP : 1;
521	uint32_t u1OP8 : 1;
522	uint32_t u1OP16 : 1;
523	uint32_t u1OP32 : 1;
524	uint32_t u1ADDR16 : 1;
525	uint32_t u1ADDR32 : 1;
526	uint32_t u1ADDR64 : 1;
527	uint32_t u6Reserved : 6;
528	uint32_t u16Port : 16;
529	} n;
530	uint32_t u;
531	} SVMIOIOEXIT;
532
533	/**
534	* SVM nested paging structure.
535	*/
536	typedef union
537	{
538	struct
539	{
540	uint32_t u1NestedPaging : 1; /*< enabled/disabled /
541	} n;
542	uint64_t u;
543	} SVMNPCTRL;
544
545	/**
546	* SVM AVIC.
547	*/
548	typedef union
549	{
550	struct
551	{
552	uint64_t u12Reserved1 : 12;
553	uint64_t u40Addr : 40;
554	uint64_t u12Reserved2 : 12;
555	} n;
556	uint64_t u;
557	} SVMAVIC;
558
559	/**
560	* SVM AVIC PHYSICAL_TABLE pointer.
561	*/
562	typedef union
563	{
564	struct
565	{
566	uint64_t u8LastGuestCoreId : 8;
567	uint64_t u4Reserved : 4;
568	uint64_t u40Addr : 40;
569	uint64_t u12Reserved : 12;
570	} n;
571	uint64_t u;
572	} SVMAVICPHYS;
573
574	/**
575	* SVM VM Control Block. (VMCB)
576	*/
577	#pragma pack(1)
578	typedef struct SVMVMCB
579	{
580	/** Control Area. */
581	struct
582	{
583	/** Offset 0x00 - Intercept reads of CR0-15. */
584	uint16_t u16InterceptRdCRx;
585	/** Offset 0x02 - Intercept writes to CR0-15. */
586	uint16_t u16InterceptWrCRx;
587	/** Offset 0x04 - Intercept reads of DR0-15. */
588	uint16_t u16InterceptRdDRx;
589	/** Offset 0x06 - Intercept writes to DR0-15. */
590	uint16_t u16InterceptWrDRx;
591	/** Offset 0x08 - Intercept exception vectors 0-31. */
592	uint32_t u32InterceptException;
593	/** Offset 0x0C - Intercept control field 1. */
594	uint32_t u32InterceptCtrl1;
595	/** Offset 0x0C - Intercept control field 2. */
596	uint32_t u32InterceptCtrl2;
597	/** Offset 0x14-0x3F - Reserved. */
598	uint8_t u8Reserved[0x3c - 0x14];
599	/** Offset 0x3c - PAUSE filter threshold. */
600	uint16_t u16PauseFilterThreshold;
601	/** Offset 0x3e - PAUSE intercept filter count. */
602	uint16_t u16PauseFilterCount;
603	/** Offset 0x40 - Physical address of IOPM. */
604	uint64_t u64IOPMPhysAddr;
605	/** Offset 0x48 - Physical address of MSRPM. */
606	uint64_t u64MSRPMPhysAddr;
607	/** Offset 0x50 - TSC Offset. */
608	uint64_t u64TSCOffset;
609	/** Offset 0x58 - TLB control field. */
610	SVMTLBCTRL TLBCtrl;
611	/** Offset 0x60 - Interrupt control field. */
612	SVMINTCTRL IntCtrl;
613	/** Offset 0x68 - Interrupt shadow. */
614	uint64_t u64IntShadow;
615	/** Offset 0x70 - Exit code. */
616	uint64_t u64ExitCode;
617	/** Offset 0x78 - Exit info 1. */
618	uint64_t u64ExitInfo1;
619	/** Offset 0x80 - Exit info 2. */
620	uint64_t u64ExitInfo2;
621	/** Offset 0x88 - Exit Interrupt info. */
622	SVMEVENT ExitIntInfo;
623	/** Offset 0x90 - Nested Paging. */
624	SVMNPCTRL NestedPaging;
625	/** Offset 0x98 - AVIC APIC BAR. */
626	SVMAVIC AvicBar;
627	/** Offset 0xA0-0xA7 - Reserved. */
628	uint8_t u8Reserved2[0xA8-0xA0];
629	/** Offset 0xA8 - Event injection. */
630	SVMEVENT EventInject;
631	/** Offset 0xB0 - Host CR3 for nested paging. */
632	uint64_t u64NestedPagingCR3;
633	/** Offset 0xB8 - LBR Virtualization. */
634	uint64_t u64LBRVirt;
635	/** Offset 0xC0 - VMCB Clean Bits. */
636	uint64_t u64VmcbCleanBits;
637	/** Offset 0xC8 - Next sequential instruction pointer. */
638	uint64_t u64NextRIP;
639	/** Offset 0xD0 - Number of bytes fetched. */
640	uint8_t cbInstrFetched;
641	/** Offset 0xD1 - Number of bytes fetched. */
642	uint8_t abInstr[15];
643	/** Offset 0xE0 - AVIC APIC_BACKING_PAGE pointer. */
644	SVMAVIC AvicBackingPagePtr;
645	/** Offset 0xE8-0xEF - Reserved. */
646	uint8_t u8Reserved3[0xF0 - 0xE8];
647	/** Offset 0xF0 - AVIC LOGICAL_TABLE pointer. */
648	SVMAVIC AvicLogicalTablePtr;
649	/** Offset 0xF8 - AVIC PHYSICAL_TABLE pointer. */
650	SVMAVICPHYS AvicPhysicalTablePtr;
651	} ctrl;
652
653	/** Offset 0x100-0x3FF - Reserved. */
654	uint8_t u8Reserved3[0x400-0x100];
655
656	/** State Save Area. Starts at offset 0x400. */
657	struct
658	{
659	/** Offset 0x400 - Guest ES register + hidden parts. */
660	SVMSEL ES;
661	/** Offset 0x410 - Guest CS register + hidden parts. */
662	SVMSEL CS;
663	/** Offset 0x420 - Guest SS register + hidden parts. */
664	SVMSEL SS;
665	/** Offset 0x430 - Guest DS register + hidden parts. */
666	SVMSEL DS;
667	/** Offset 0x440 - Guest FS register + hidden parts. */
668	SVMSEL FS;
669	/** Offset 0x450 - Guest GS register + hidden parts. */
670	SVMSEL GS;
671	/** Offset 0x460 - Guest GDTR register. */
672	SVMGDTR GDTR;
673	/** Offset 0x470 - Guest LDTR register + hidden parts. */
674	SVMSEL LDTR;
675	/** Offset 0x480 - Guest IDTR register. */
676	SVMIDTR IDTR;
677	/** Offset 0x490 - Guest TR register + hidden parts. */
678	SVMSEL TR;
679	/** Offset 0x4A0-0x4CA - Reserved. */
680	uint8_t u8Reserved4[0x4CB-0x4A0];
681	/** Offset 0x4CB - CPL. */
682	uint8_t u8CPL;
683	/** Offset 0x4CC-0x4CF - Reserved. */
684	uint8_t u8Reserved5[0x4D0-0x4CC];
685	/** Offset 0x4D0 - EFER. */
686	uint64_t u64EFER;
687	/** Offset 0x4D8-0x547 - Reserved. */
688	uint8_t u8Reserved6[0x548-0x4D8];
689	/** Offset 0x548 - CR4. */
690	uint64_t u64CR4;
691	/** Offset 0x550 - CR3. */
692	uint64_t u64CR3;
693	/** Offset 0x558 - CR0. */
694	uint64_t u64CR0;
695	/** Offset 0x560 - DR7. */
696	uint64_t u64DR7;
697	/** Offset 0x568 - DR6. */
698	uint64_t u64DR6;
699	/** Offset 0x570 - RFLAGS. */
700	uint64_t u64RFlags;
701	/** Offset 0x578 - RIP. */
702	uint64_t u64RIP;
703	/** Offset 0x580-0x5D7 - Reserved. */
704	uint8_t u8Reserved7[0x5D8-0x580];
705	/** Offset 0x5D8 - RSP. */
706	uint64_t u64RSP;
707	/** Offset 0x5E0-0x5F7 - Reserved. */
708	uint8_t u8Reserved8[0x5F8-0x5E0];
709	/** Offset 0x5F8 - RAX. */
710	uint64_t u64RAX;
711	/** Offset 0x600 - STAR. */
712	uint64_t u64STAR;
713	/** Offset 0x608 - LSTAR. */
714	uint64_t u64LSTAR;
715	/** Offset 0x610 - CSTAR. */
716	uint64_t u64CSTAR;
717	/** Offset 0x618 - SFMASK. */
718	uint64_t u64SFMASK;
719	/** Offset 0x620 - KernelGSBase. */
720	uint64_t u64KernelGSBase;
721	/** Offset 0x628 - SYSENTER_CS. */
722	uint64_t u64SysEnterCS;
723	/** Offset 0x630 - SYSENTER_ESP. */
724	uint64_t u64SysEnterESP;
725	/** Offset 0x638 - SYSENTER_EIP. */
726	uint64_t u64SysEnterEIP;
727	/** Offset 0x640 - CR2. */
728	uint64_t u64CR2;
729	/** Offset 0x648-0x667 - Reserved. */
730	uint8_t u8Reserved9[0x668-0x648];
731	/** Offset 0x668 - G_PAT. */
732	uint64_t u64GPAT;
733	/** Offset 0x670 - DBGCTL. */
734	uint64_t u64DBGCTL;
735	/** Offset 0x678 - BR_FROM. */
736	uint64_t u64BR_FROM;
737	/** Offset 0x680 - BR_TO. */
738	uint64_t u64BR_TO;
739	/** Offset 0x688 - LASTEXCPFROM. */
740	uint64_t u64LASTEXCPFROM;
741	/** Offset 0x690 - LASTEXCPTO. */
742	uint64_t u64LASTEXCPTO;
743	} guest;
744
745	/** Offset 0x698-0xFFF- Reserved. */
746	uint8_t u8Reserved10[0x1000-0x698];
747	} SVMVMCB;
748	#pragma pack()
749	/** Pointer to the SVMVMCB structure. */
750	typedef SVMVMCB *PSVMVMCB;
751	AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdCRx, 0x000);
752	AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterCount, 0x03e);
753	AssertCompileMemberOffset(SVMVMCB, ctrl.TLBCtrl, 0x058);
754	AssertCompileMemberOffset(SVMVMCB, ctrl.ExitIntInfo, 0x088);
755	AssertCompileMemberOffset(SVMVMCB, ctrl.EventInject, 0x0A8);
756	AssertCompileMemberOffset(SVMVMCB, ctrl.abInstr, 0x0D1);
757	AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBackingPagePtr, 0x0E0);
758	AssertCompileMemberOffset(SVMVMCB, ctrl.AvicLogicalTablePtr, 0x0F0);
759	AssertCompileMemberOffset(SVMVMCB, ctrl.AvicPhysicalTablePtr, 0x0F8);
760	AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
761	AssertCompileMemberOffset(SVMVMCB, guest.ES, 0x400);
762	AssertCompileMemberOffset(SVMVMCB, guest.TR, 0x490);
763	AssertCompileMemberOffset(SVMVMCB, guest.u64EFER, 0x4D0);
764	AssertCompileMemberOffset(SVMVMCB, guest.u64CR4, 0x548);
765	AssertCompileMemberOffset(SVMVMCB, guest.u64RIP, 0x578);
766	AssertCompileMemberOffset(SVMVMCB, guest.u64RSP, 0x5D8);
767	AssertCompileMemberOffset(SVMVMCB, guest.u64CR2, 0x640);
768	AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved4, 0x4A0);
769	AssertCompileMemberOffset(SVMVMCB, guest.u8CPL, 0x4CB);
770	AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved6, 0x4D8);
771	AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved7, 0x580);
772	AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved9, 0x648);
773	AssertCompileMemberOffset(SVMVMCB, guest.u64GPAT, 0x668);
774	AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPTO, 0x690);
775	AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
776	AssertCompileSize(SVMAVIC, 0x8);
777	AssertCompileSize(SVMAVICPHYS, 0x8);
778	AssertCompileSize(SVMVMCB, 0x1000);
779
780	#ifdef IN_RING0
781	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
782	#endif /* IN_RING0 */
783
784	/** @} */
785
786	#endif /* ___VBox_vmm_svm_h */
787

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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 46314

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