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source: vbox/trunk/include/VBox/vmm/hm_svm.h@ 46551

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VMM/HMSVMR0: AMD-V bits.
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1/** @file
2 * HM - SVM Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2013 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_svm_h
27#define ___VBox_vmm_svm_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33
34/** @defgroup grp_svm svm Types and Definitions
35 * @ingroup grp_hm
36 * @{
37 */
38
39/** @name SVM features for cpuid 0x8000000a
40 * @{
41 */
42/** Bit 0 - NP - Nested Paging supported. */
43#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
44/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
45#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
46/** Bit 2 - SVML - SVM locking bit supported. */
47#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
48/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
49#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
50/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
51#define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
52/** Bit 5 - VmcbClean - Support VMCB clean bits. */
53#define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
54/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
55 * VMCB.TLB_Control is supported. */
56#define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
57/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
58#define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
59/** Where did we get this from? */
60#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
61/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
62#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
63/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
64 * intercept filter cycle count threshold. */
65#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
66/** @} */
67
68
69/** @name SVM Basic Exit Reasons.
70 * @{
71 */
72/** Invalid guest state in VMCB. */
73#define SVM_EXIT_INVALID (-1)
74/** Read from CR0-CR15. */
75#define SVM_EXIT_READ_CR0 0x0
76#define SVM_EXIT_READ_CR1 0x1
77#define SVM_EXIT_READ_CR2 0x2
78#define SVM_EXIT_READ_CR3 0x3
79#define SVM_EXIT_READ_CR4 0x4
80#define SVM_EXIT_READ_CR5 0x5
81#define SVM_EXIT_READ_CR6 0x6
82#define SVM_EXIT_READ_CR7 0x7
83#define SVM_EXIT_READ_CR8 0x8
84#define SVM_EXIT_READ_CR9 0x9
85#define SVM_EXIT_READ_CR10 0xA
86#define SVM_EXIT_READ_CR11 0xB
87#define SVM_EXIT_READ_CR12 0xC
88#define SVM_EXIT_READ_CR13 0xD
89#define SVM_EXIT_READ_CR14 0xE
90#define SVM_EXIT_READ_CR15 0xF
91/** Writes to CR0-CR15. */
92#define SVM_EXIT_WRITE_CR0 0x10
93#define SVM_EXIT_WRITE_CR1 0x11
94#define SVM_EXIT_WRITE_CR2 0x12
95#define SVM_EXIT_WRITE_CR3 0x13
96#define SVM_EXIT_WRITE_CR4 0x14
97#define SVM_EXIT_WRITE_CR5 0x15
98#define SVM_EXIT_WRITE_CR6 0x16
99#define SVM_EXIT_WRITE_CR7 0x17
100#define SVM_EXIT_WRITE_CR8 0x18
101#define SVM_EXIT_WRITE_CR9 0x19
102#define SVM_EXIT_WRITE_CR10 0x1A
103#define SVM_EXIT_WRITE_CR11 0x1B
104#define SVM_EXIT_WRITE_CR12 0x1C
105#define SVM_EXIT_WRITE_CR13 0x1D
106#define SVM_EXIT_WRITE_CR14 0x1E
107#define SVM_EXIT_WRITE_CR15 0x1F
108/** Read from DR0-DR15. */
109#define SVM_EXIT_READ_DR0 0x20
110#define SVM_EXIT_READ_DR1 0x21
111#define SVM_EXIT_READ_DR2 0x22
112#define SVM_EXIT_READ_DR3 0x23
113#define SVM_EXIT_READ_DR4 0x24
114#define SVM_EXIT_READ_DR5 0x25
115#define SVM_EXIT_READ_DR6 0x26
116#define SVM_EXIT_READ_DR7 0x27
117#define SVM_EXIT_READ_DR8 0x28
118#define SVM_EXIT_READ_DR9 0x29
119#define SVM_EXIT_READ_DR10 0x2A
120#define SVM_EXIT_READ_DR11 0x2B
121#define SVM_EXIT_READ_DR12 0x2C
122#define SVM_EXIT_READ_DR13 0x2D
123#define SVM_EXIT_READ_DR14 0x2E
124#define SVM_EXIT_READ_DR15 0x2F
125/** Writes to DR0-DR15. */
126#define SVM_EXIT_WRITE_DR0 0x30
127#define SVM_EXIT_WRITE_DR1 0x31
128#define SVM_EXIT_WRITE_DR2 0x32
129#define SVM_EXIT_WRITE_DR3 0x33
130#define SVM_EXIT_WRITE_DR4 0x34
131#define SVM_EXIT_WRITE_DR5 0x35
132#define SVM_EXIT_WRITE_DR6 0x36
133#define SVM_EXIT_WRITE_DR7 0x37
134#define SVM_EXIT_WRITE_DR8 0x38
135#define SVM_EXIT_WRITE_DR9 0x39
136#define SVM_EXIT_WRITE_DR10 0x3A
137#define SVM_EXIT_WRITE_DR11 0x3B
138#define SVM_EXIT_WRITE_DR12 0x3C
139#define SVM_EXIT_WRITE_DR13 0x3D
140#define SVM_EXIT_WRITE_DR14 0x3E
141#define SVM_EXIT_WRITE_DR15 0x3F
142/* Exception 0-31. */
143#define SVM_EXIT_EXCEPTION_0 0x40
144#define SVM_EXIT_EXCEPTION_1 0x41
145#define SVM_EXIT_EXCEPTION_2 0x42
146#define SVM_EXIT_EXCEPTION_3 0x43
147#define SVM_EXIT_EXCEPTION_4 0x44
148#define SVM_EXIT_EXCEPTION_5 0x45
149#define SVM_EXIT_EXCEPTION_6 0x46
150#define SVM_EXIT_EXCEPTION_7 0x47
151#define SVM_EXIT_EXCEPTION_8 0x48
152#define SVM_EXIT_EXCEPTION_9 0x49
153#define SVM_EXIT_EXCEPTION_A 0x4A
154#define SVM_EXIT_EXCEPTION_B 0x4B
155#define SVM_EXIT_EXCEPTION_C 0x4C
156#define SVM_EXIT_EXCEPTION_D 0x4D
157#define SVM_EXIT_EXCEPTION_E 0x4E
158#define SVM_EXIT_EXCEPTION_F 0x4F
159#define SVM_EXIT_EXCEPTION_10 0x50
160#define SVM_EXIT_EXCEPTION_11 0x51
161#define SVM_EXIT_EXCEPTION_12 0x52
162#define SVM_EXIT_EXCEPTION_13 0x53
163#define SVM_EXIT_EXCEPTION_14 0x54
164#define SVM_EXIT_EXCEPTION_15 0x55
165#define SVM_EXIT_EXCEPTION_16 0x56
166#define SVM_EXIT_EXCEPTION_17 0x57
167#define SVM_EXIT_EXCEPTION_18 0x58
168#define SVM_EXIT_EXCEPTION_19 0x59
169#define SVM_EXIT_EXCEPTION_1A 0x5A
170#define SVM_EXIT_EXCEPTION_1B 0x5B
171#define SVM_EXIT_EXCEPTION_1C 0x5C
172#define SVM_EXIT_EXCEPTION_1D 0x5D
173#define SVM_EXIT_EXCEPTION_1E 0x5E
174#define SVM_EXIT_EXCEPTION_1F 0x5F
175/** Physical maskable interrupt. */
176#define SVM_EXIT_INTR 0x60
177/** Non-maskable interrupt. */
178#define SVM_EXIT_NMI 0x61
179/** System Management interrupt. */
180#define SVM_EXIT_SMI 0x62
181/** Physical INIT signal. */
182#define SVM_EXIT_INIT 0x63
183/** Virtual interrupt. */
184#define SVM_EXIT_VINTR 0x64
185/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
186#define SVM_EXIT_CR0_SEL_WRITE 0x65
187/** IDTR read. */
188#define SVM_EXIT_IDTR_READ 0x66
189/** GDTR read. */
190#define SVM_EXIT_GDTR_READ 0x67
191/** LDTR read. */
192#define SVM_EXIT_LDTR_READ 0x68
193/** TR read. */
194#define SVM_EXIT_TR_READ 0x69
195/** IDTR write. */
196#define SVM_EXIT_IDTR_WRITE 0x6A
197/** GDTR write. */
198#define SVM_EXIT_GDTR_WRITE 0x6B
199/** LDTR write. */
200#define SVM_EXIT_LDTR_WRITE 0x6C
201/** TR write. */
202#define SVM_EXIT_TR_WRITE 0x6D
203/** RDTSC instruction. */
204#define SVM_EXIT_RDTSC 0x6E
205/** RDPMC instruction. */
206#define SVM_EXIT_RDPMC 0x6F
207/** PUSHF instruction. */
208#define SVM_EXIT_PUSHF 0x70
209/** POPF instruction. */
210#define SVM_EXIT_POPF 0x71
211/** CPUID instruction. */
212#define SVM_EXIT_CPUID 0x72
213/** RSM instruction. */
214#define SVM_EXIT_RSM 0x73
215/** IRET instruction. */
216#define SVM_EXIT_IRET 0x74
217/** software interrupt (INTn instructions). */
218#define SVM_EXIT_SWINT 0x75
219/** INVD instruction. */
220#define SVM_EXIT_INVD 0x76
221/** PAUSE instruction. */
222#define SVM_EXIT_PAUSE 0x77
223/** HLT instruction. */
224#define SVM_EXIT_HLT 0x78
225/** INVLPG instructions. */
226#define SVM_EXIT_INVLPG 0x79
227/** INVLPGA instruction. */
228#define SVM_EXIT_INVLPGA 0x7A
229/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
230#define SVM_EXIT_IOIO 0x7B
231/** RDMSR or WRMSR access to protected MSR. */
232#define SVM_EXIT_MSR 0x7C
233/** task switch. */
234#define SVM_EXIT_TASK_SWITCH 0x7D
235/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
236#define SVM_EXIT_FERR_FREEZE 0x7E
237/** Shutdown. */
238#define SVM_EXIT_SHUTDOWN 0x7F
239/** VMRUN instruction. */
240#define SVM_EXIT_VMRUN 0x80
241/** VMMCALL instruction. */
242#define SVM_EXIT_VMMCALL 0x81
243/** VMLOAD instruction. */
244#define SVM_EXIT_VMLOAD 0x82
245/** VMSAVE instruction. */
246#define SVM_EXIT_VMSAVE 0x83
247/** STGI instruction. */
248#define SVM_EXIT_STGI 0x84
249/** CLGI instruction. */
250#define SVM_EXIT_CLGI 0x85
251/** SKINIT instruction. */
252#define SVM_EXIT_SKINIT 0x86
253/** RDTSCP instruction. */
254#define SVM_EXIT_RDTSCP 0x87
255/** ICEBP instruction. */
256#define SVM_EXIT_ICEBP 0x88
257/** WBINVD instruction. */
258#define SVM_EXIT_WBINVD 0x89
259/** MONITOR instruction. */
260#define SVM_EXIT_MONITOR 0x8A
261/** MWAIT instruction uncond. */
262#define SVM_EXIT_MWAIT_UNCOND 0x8B
263/** MWAIT instruction when armed. */
264#define SVM_EXIT_MWAIT_ARMED 0x8C
265/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
266#define SVM_EXIT_NPF 0x400
267/** AVIC: Virtual IPI delivery not completed. */
268#define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
269/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
270 * hardware. */
271#define SVM_EXIT_AVIC_NOACCEL 0x402
272
273/** The maximum possible exit value. */
274#define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
275/** @} */
276
277
278/** @name SVMVMCB.u64ExitInfo2 for task switches
279 * @{
280 */
281/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
282#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
283/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
284#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
285/** Set to 1 if the task switch has an error code; else cleared to 0. */
286#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
287/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
288#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
289/** @} */
290
291/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
292 * @{
293 */
294/** The access was a read MSR. */
295#define SVM_EXIT1_MSR_READ 0x0
296/** The access was a write MSR. */
297#define SVM_EXIT1_MSR_WRITE 0x1
298/** @} */
299
300/** @name SVMVMCB.ctrl.u32InterceptCtrl1
301 * @{
302 */
303/** 0 Intercept INTR (physical maskable interrupt). */
304#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
305/** 1 Intercept NMI. */
306#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
307/** 2 Intercept SMI. */
308#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
309/** 3 Intercept INIT. */
310#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
311/** 4 Intercept VINTR (virtual maskable interrupt). */
312#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
313/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
314#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
315/** 6 Intercept reads of IDTR. */
316#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
317/** 7 Intercept reads of GDTR. */
318#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
319/** 8 Intercept reads of LDTR. */
320#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
321/** 9 Intercept reads of TR. */
322#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
323/** 10 Intercept writes of IDTR. */
324#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
325/** 11 Intercept writes of GDTR. */
326#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
327/** 12 Intercept writes of LDTR. */
328#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
329/** 13 Intercept writes of TR. */
330#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
331/** 14 Intercept RDTSC instruction. */
332#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
333/** 15 Intercept RDPMC instruction. */
334#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
335/** 16 Intercept PUSHF instruction. */
336#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
337/** 17 Intercept POPF instruction. */
338#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
339/** 18 Intercept CPUID instruction. */
340#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
341/** 19 Intercept RSM instruction. */
342#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
343/** 20 Intercept IRET instruction. */
344#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
345/** 21 Intercept INTn instruction. */
346#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
347/** 22 Intercept INVD instruction. */
348#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
349/** 23 Intercept PAUSE instruction. */
350#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
351/** 24 Intercept HLT instruction. */
352#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
353/** 25 Intercept INVLPG instruction. */
354#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
355/** 26 Intercept INVLPGA instruction. */
356#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
357/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
358#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
359/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
360#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
361/** 29 Intercept task switches. */
362#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
363/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
364#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
365/** 31 Intercept shutdown events. */
366#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
367/** @} */
368
369
370/** @name SVMVMCB.ctrl.u32InterceptCtrl2
371 * @{
372 */
373/** 0 Intercept VMRUN instruction. */
374#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
375/** 1 Intercept VMMCALL instruction. */
376#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
377/** 2 Intercept VMLOAD instruction. */
378#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
379/** 3 Intercept VMSAVE instruction. */
380#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
381/** 4 Intercept STGI instruction. */
382#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
383/** 5 Intercept CLGI instruction. */
384#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
385/** 6 Intercept SKINIT instruction. */
386#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
387/** 7 Intercept RDTSCP instruction. */
388#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
389/** 8 Intercept ICEBP instruction. */
390#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
391/** 9 Intercept WBINVD instruction. */
392#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
393/** 10 Intercept MONITOR instruction. */
394#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
395/** 11 Intercept MWAIT instruction unconditionally. */
396#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
397/** 12 Intercept MWAIT instruction when armed. */
398#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
399/** 13 Intercept XSETBV instruction. */
400#define SVM_CTRL2_INTERCEPT_XSETBV RT_BIT(13)
401/** @} */
402
403/** @name SVMVMCB.ctrl.u64NestedPaging
404 * @{
405 */
406#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
407/** @} */
408
409/** @name SVMVMCB.ctrl.u64IntShadow
410 * @{
411 */
412#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
413/** @} */
414
415
416/** @name SVMINTCTRL.u3Type
417 * @{
418 */
419/** External or virtual interrupt. */
420#define SVM_EVENT_EXTERNAL_IRQ 0
421/** Non-maskable interrupt. */
422#define SVM_EVENT_NMI 2
423/** Exception; fault or trap. */
424#define SVM_EVENT_EXCEPTION 3
425/** Software interrupt. */
426#define SVM_EVENT_SOFTWARE_INT 4
427/** @} */
428
429
430/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
431 * @{
432 */
433/** Flush nothing. */
434#define SVM_TLB_FLUSH_NOTHING 0
435/** Flush entire TLB (host+guest entries) */
436#define SVM_TLB_FLUSH_ENTIRE 1
437/** Flush this guest's TLB entries (by ASID) */
438#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
439/** Flush this guest's non-global TLB entries (by ASID) */
440#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
441/** @} */
442
443
444/**
445 * SVM Selector type; includes hidden parts.
446 */
447#pragma pack(1)
448typedef struct
449{
450 uint16_t u16Sel;
451 uint16_t u16Attr;
452 uint32_t u32Limit;
453 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
454} SVMSEL;
455#pragma pack()
456
457/**
458 * SVM GDTR/IDTR type.
459 */
460#pragma pack(1)
461typedef struct
462{
463 uint16_t u16Reserved1;
464 uint16_t u16Reserved2;
465 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
466 uint64_t u64Base;
467} SVMGDTR;
468#pragma pack()
469typedef SVMGDTR SVMIDTR;
470
471/**
472 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
473 */
474typedef union
475{
476 struct
477 {
478 uint32_t u8Vector : 8;
479 uint32_t u3Type : 3;
480 uint32_t u1ErrorCodeValid : 1;
481 uint32_t u19Reserved : 19;
482 uint32_t u1Valid : 1;
483 uint32_t u32ErrorCode : 32;
484 } n;
485 uint64_t u;
486} SVMEVENT;
487/** Pointer to the SVMEVENT union. */
488typedef SVMEVENT *PSVMEVENT;
489
490/**
491 * SVM Interrupt control structure (Virtual Interrupt Control).
492 */
493typedef union
494{
495 struct
496 {
497 uint32_t u8VTPR : 8;
498 uint32_t u1VIrqValid : 1;
499 uint32_t u7Reserved : 7;
500 uint32_t u4VIrqPriority : 4;
501 uint32_t u1IgnoreTPR : 1;
502 uint32_t u3Reserved : 3;
503 uint32_t u1VIrqMasking : 1;
504 uint32_t u6Reserved : 6;
505 uint32_t u1AvicEnable : 1;
506 uint32_t u8VIrqVector : 8;
507 uint32_t u24Reserved : 24;
508 } n;
509 uint64_t u;
510} SVMINTCTRL;
511
512/**
513 * SVM TLB control structure.
514 */
515typedef union
516{
517 struct
518 {
519 uint32_t u32ASID : 32;
520 uint32_t u8TLBFlush : 8;
521 uint32_t u24Reserved : 24;
522 } n;
523 uint64_t u;
524} SVMTLBCTRL;
525
526/**
527 * SVM IOIO exit structure (EXITINFO1 for IOIO intercepts).
528 */
529typedef union
530{
531 struct
532 {
533 uint32_t u1Type : 1; /**< 0 = out, 1 = in */
534 uint32_t u1Reserved : 1;
535 uint32_t u1STR : 1;
536 uint32_t u1REP : 1;
537 uint32_t u1OP8 : 1;
538 uint32_t u1OP16 : 1;
539 uint32_t u1OP32 : 1;
540 uint32_t u1ADDR16 : 1;
541 uint32_t u1ADDR32 : 1;
542 uint32_t u1ADDR64 : 1;
543 uint32_t u6Reserved : 6;
544 uint32_t u16Port : 16;
545 } n;
546 uint32_t u;
547} SVMIOIOEXIT;
548
549/**
550 * SVM nested paging structure.
551 */
552typedef union
553{
554 struct
555 {
556 uint32_t u1NestedPaging : 1; /**< enabled/disabled */
557 } n;
558 uint64_t u;
559} SVMNPCTRL;
560
561/**
562 * SVM AVIC.
563 */
564typedef union
565{
566 struct
567 {
568 uint64_t u12Reserved1 : 12;
569 uint64_t u40Addr : 40;
570 uint64_t u12Reserved2 : 12;
571 } n;
572 uint64_t u;
573} SVMAVIC;
574AssertCompileSize(SVMAVIC, 8);
575
576/**
577 * SVM AVIC PHYSICAL_TABLE pointer.
578 */
579typedef union
580{
581 struct
582 {
583 uint64_t u8LastGuestCoreId : 8;
584 uint64_t u4Reserved : 4;
585 uint64_t u40Addr : 40;
586 uint64_t u12Reserved : 12;
587 } n;
588 uint64_t u;
589} SVMAVICPHYS;
590AssertCompileSize(SVMAVICPHYS, 8);
591
592/**
593 * SVM VM Control Block. (VMCB)
594 */
595#pragma pack(1)
596typedef struct SVMVMCB
597{
598 /** Control Area. */
599 struct
600 {
601 /** Offset 0x00 - Intercept reads of CR0-15. */
602 uint16_t u16InterceptRdCRx;
603 /** Offset 0x02 - Intercept writes to CR0-15. */
604 uint16_t u16InterceptWrCRx;
605 /** Offset 0x04 - Intercept reads of DR0-15. */
606 uint16_t u16InterceptRdDRx;
607 /** Offset 0x06 - Intercept writes to DR0-15. */
608 uint16_t u16InterceptWrDRx;
609 /** Offset 0x08 - Intercept exception vectors 0-31. */
610 uint32_t u32InterceptException;
611 /** Offset 0x0C - Intercept control field 1. */
612 uint32_t u32InterceptCtrl1;
613 /** Offset 0x0C - Intercept control field 2. */
614 uint32_t u32InterceptCtrl2;
615 /** Offset 0x14-0x3F - Reserved. */
616 uint8_t u8Reserved[0x3c - 0x14];
617 /** Offset 0x3c - PAUSE filter threshold. */
618 uint16_t u16PauseFilterThreshold;
619 /** Offset 0x3e - PAUSE intercept filter count. */
620 uint16_t u16PauseFilterCount;
621 /** Offset 0x40 - Physical address of IOPM. */
622 uint64_t u64IOPMPhysAddr;
623 /** Offset 0x48 - Physical address of MSRPM. */
624 uint64_t u64MSRPMPhysAddr;
625 /** Offset 0x50 - TSC Offset. */
626 uint64_t u64TSCOffset;
627 /** Offset 0x58 - TLB control field. */
628 SVMTLBCTRL TLBCtrl;
629 /** Offset 0x60 - Interrupt control field. */
630 SVMINTCTRL IntCtrl;
631 /** Offset 0x68 - Interrupt shadow. */
632 uint64_t u64IntShadow;
633 /** Offset 0x70 - Exit code. */
634 uint64_t u64ExitCode;
635 /** Offset 0x78 - Exit info 1. */
636 uint64_t u64ExitInfo1;
637 /** Offset 0x80 - Exit info 2. */
638 uint64_t u64ExitInfo2;
639 /** Offset 0x88 - Exit Interrupt info. */
640 SVMEVENT ExitIntInfo;
641 /** Offset 0x90 - Nested Paging. */
642 SVMNPCTRL NestedPaging;
643 /** Offset 0x98 - AVIC APIC BAR. */
644 SVMAVIC AvicBar;
645 /** Offset 0xA0-0xA7 - Reserved. */
646 uint8_t u8Reserved2[0xA8-0xA0];
647 /** Offset 0xA8 - Event injection. */
648 SVMEVENT EventInject;
649 /** Offset 0xB0 - Host CR3 for nested paging. */
650 uint64_t u64NestedPagingCR3;
651 /** Offset 0xB8 - LBR Virtualization. */
652 uint64_t u64LBRVirt;
653 /** Offset 0xC0 - VMCB Clean Bits. */
654 uint64_t u64VmcbCleanBits;
655 /** Offset 0xC8 - Next sequential instruction pointer. */
656 uint64_t u64NextRIP;
657 /** Offset 0xD0 - Number of bytes fetched. */
658 uint8_t cbInstrFetched;
659 /** Offset 0xD1 - Number of bytes fetched. */
660 uint8_t abInstr[15];
661 /** Offset 0xE0 - AVIC APIC_BACKING_PAGE pointer. */
662 SVMAVIC AvicBackingPagePtr;
663 /** Offset 0xE8-0xEF - Reserved. */
664 uint8_t u8Reserved3[0xF0 - 0xE8];
665 /** Offset 0xF0 - AVIC LOGICAL_TABLE pointer. */
666 SVMAVIC AvicLogicalTablePtr;
667 /** Offset 0xF8 - AVIC PHYSICAL_TABLE pointer. */
668 SVMAVICPHYS AvicPhysicalTablePtr;
669 } ctrl;
670
671 /** Offset 0x100-0x3FF - Reserved. */
672 uint8_t u8Reserved3[0x400-0x100];
673
674 /** State Save Area. Starts at offset 0x400. */
675 struct
676 {
677 /** Offset 0x400 - Guest ES register + hidden parts. */
678 SVMSEL ES;
679 /** Offset 0x410 - Guest CS register + hidden parts. */
680 SVMSEL CS;
681 /** Offset 0x420 - Guest SS register + hidden parts. */
682 SVMSEL SS;
683 /** Offset 0x430 - Guest DS register + hidden parts. */
684 SVMSEL DS;
685 /** Offset 0x440 - Guest FS register + hidden parts. */
686 SVMSEL FS;
687 /** Offset 0x450 - Guest GS register + hidden parts. */
688 SVMSEL GS;
689 /** Offset 0x460 - Guest GDTR register. */
690 SVMGDTR GDTR;
691 /** Offset 0x470 - Guest LDTR register + hidden parts. */
692 SVMSEL LDTR;
693 /** Offset 0x480 - Guest IDTR register. */
694 SVMIDTR IDTR;
695 /** Offset 0x490 - Guest TR register + hidden parts. */
696 SVMSEL TR;
697 /** Offset 0x4A0-0x4CA - Reserved. */
698 uint8_t u8Reserved4[0x4CB-0x4A0];
699 /** Offset 0x4CB - CPL. */
700 uint8_t u8CPL;
701 /** Offset 0x4CC-0x4CF - Reserved. */
702 uint8_t u8Reserved5[0x4D0-0x4CC];
703 /** Offset 0x4D0 - EFER. */
704 uint64_t u64EFER;
705 /** Offset 0x4D8-0x547 - Reserved. */
706 uint8_t u8Reserved6[0x548-0x4D8];
707 /** Offset 0x548 - CR4. */
708 uint64_t u64CR4;
709 /** Offset 0x550 - CR3. */
710 uint64_t u64CR3;
711 /** Offset 0x558 - CR0. */
712 uint64_t u64CR0;
713 /** Offset 0x560 - DR7. */
714 uint64_t u64DR7;
715 /** Offset 0x568 - DR6. */
716 uint64_t u64DR6;
717 /** Offset 0x570 - RFLAGS. */
718 uint64_t u64RFlags;
719 /** Offset 0x578 - RIP. */
720 uint64_t u64RIP;
721 /** Offset 0x580-0x5D7 - Reserved. */
722 uint8_t u8Reserved7[0x5D8-0x580];
723 /** Offset 0x5D8 - RSP. */
724 uint64_t u64RSP;
725 /** Offset 0x5E0-0x5F7 - Reserved. */
726 uint8_t u8Reserved8[0x5F8-0x5E0];
727 /** Offset 0x5F8 - RAX. */
728 uint64_t u64RAX;
729 /** Offset 0x600 - STAR. */
730 uint64_t u64STAR;
731 /** Offset 0x608 - LSTAR. */
732 uint64_t u64LSTAR;
733 /** Offset 0x610 - CSTAR. */
734 uint64_t u64CSTAR;
735 /** Offset 0x618 - SFMASK. */
736 uint64_t u64SFMASK;
737 /** Offset 0x620 - KernelGSBase. */
738 uint64_t u64KernelGSBase;
739 /** Offset 0x628 - SYSENTER_CS. */
740 uint64_t u64SysEnterCS;
741 /** Offset 0x630 - SYSENTER_ESP. */
742 uint64_t u64SysEnterESP;
743 /** Offset 0x638 - SYSENTER_EIP. */
744 uint64_t u64SysEnterEIP;
745 /** Offset 0x640 - CR2. */
746 uint64_t u64CR2;
747 /** Offset 0x648-0x667 - Reserved. */
748 uint8_t u8Reserved9[0x668-0x648];
749 /** Offset 0x668 - G_PAT. */
750 uint64_t u64GPAT;
751 /** Offset 0x670 - DBGCTL. */
752 uint64_t u64DBGCTL;
753 /** Offset 0x678 - BR_FROM. */
754 uint64_t u64BR_FROM;
755 /** Offset 0x680 - BR_TO. */
756 uint64_t u64BR_TO;
757 /** Offset 0x688 - LASTEXCPFROM. */
758 uint64_t u64LASTEXCPFROM;
759 /** Offset 0x690 - LASTEXCPTO. */
760 uint64_t u64LASTEXCPTO;
761 } guest;
762
763 /** Offset 0x698-0xFFF- Reserved. */
764 uint8_t u8Reserved10[0x1000-0x698];
765} SVMVMCB;
766#pragma pack()
767/** Pointer to the SVMVMCB structure. */
768typedef SVMVMCB *PSVMVMCB;
769AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdCRx, 0x000);
770AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterCount, 0x03e);
771AssertCompileMemberOffset(SVMVMCB, ctrl.TLBCtrl, 0x058);
772AssertCompileMemberOffset(SVMVMCB, ctrl.ExitIntInfo, 0x088);
773AssertCompileMemberOffset(SVMVMCB, ctrl.EventInject, 0x0A8);
774AssertCompileMemberOffset(SVMVMCB, ctrl.abInstr, 0x0D1);
775AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBackingPagePtr, 0x0E0);
776AssertCompileMemberOffset(SVMVMCB, ctrl.AvicLogicalTablePtr, 0x0F0);
777AssertCompileMemberOffset(SVMVMCB, ctrl.AvicPhysicalTablePtr, 0x0F8);
778AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
779AssertCompileMemberOffset(SVMVMCB, guest.ES, 0x400);
780AssertCompileMemberOffset(SVMVMCB, guest.TR, 0x490);
781AssertCompileMemberOffset(SVMVMCB, guest.u64EFER, 0x4D0);
782AssertCompileMemberOffset(SVMVMCB, guest.u64CR4, 0x548);
783AssertCompileMemberOffset(SVMVMCB, guest.u64RIP, 0x578);
784AssertCompileMemberOffset(SVMVMCB, guest.u64RSP, 0x5D8);
785AssertCompileMemberOffset(SVMVMCB, guest.u64CR2, 0x640);
786AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved4, 0x4A0);
787AssertCompileMemberOffset(SVMVMCB, guest.u8CPL, 0x4CB);
788AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved6, 0x4D8);
789AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved7, 0x580);
790AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved9, 0x648);
791AssertCompileMemberOffset(SVMVMCB, guest.u64GPAT, 0x668);
792AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPTO, 0x690);
793AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
794AssertCompileSize(SVMVMCB, 0x1000);
795
796#ifdef IN_RING0
797VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
798#endif /* IN_RING0 */
799
800/** @} */
801
802#endif
803
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