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1/** @file
2 * HM - SVM (AMD-V) Structures and Definitions. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2015 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_svm_h
27#define ___VBox_vmm_svm_h
28
29#include <VBox/types.h>
30#include <VBox/err.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33
34
35/** @defgroup grp_svm SVM (AMD-V) Types and Definitions
36 * @ingroup grp_hm
37 * @{
38 */
39
40/** @name SVM features for cpuid 0x8000000a
41 * @{
42 */
43/** Bit 0 - NP - Nested Paging supported. */
44#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
45/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
46#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
47/** Bit 2 - SVML - SVM locking bit supported. */
48#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
49/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
50#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
51/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
52#define AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
53/** Bit 5 - VmcbClean - Support VMCB clean bits. */
54#define AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
55/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
56 * VMCB.TLB_Control is supported. */
57#define AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
58/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
59#define AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
60/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
61#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
62/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
63 * intercept filter cycle count threshold. */
64#define AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
65/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
66#define AMD_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
67/** @} */
68
69
70/** @name SVM Basic Exit Reasons.
71 * @{
72 */
73/** Invalid guest state in VMCB. */
74#define SVM_EXIT_INVALID (-1)
75/** Read from CR0-CR15. */
76#define SVM_EXIT_READ_CR0 0x0
77#define SVM_EXIT_READ_CR1 0x1
78#define SVM_EXIT_READ_CR2 0x2
79#define SVM_EXIT_READ_CR3 0x3
80#define SVM_EXIT_READ_CR4 0x4
81#define SVM_EXIT_READ_CR5 0x5
82#define SVM_EXIT_READ_CR6 0x6
83#define SVM_EXIT_READ_CR7 0x7
84#define SVM_EXIT_READ_CR8 0x8
85#define SVM_EXIT_READ_CR9 0x9
86#define SVM_EXIT_READ_CR10 0xA
87#define SVM_EXIT_READ_CR11 0xB
88#define SVM_EXIT_READ_CR12 0xC
89#define SVM_EXIT_READ_CR13 0xD
90#define SVM_EXIT_READ_CR14 0xE
91#define SVM_EXIT_READ_CR15 0xF
92/** Writes to CR0-CR15. */
93#define SVM_EXIT_WRITE_CR0 0x10
94#define SVM_EXIT_WRITE_CR1 0x11
95#define SVM_EXIT_WRITE_CR2 0x12
96#define SVM_EXIT_WRITE_CR3 0x13
97#define SVM_EXIT_WRITE_CR4 0x14
98#define SVM_EXIT_WRITE_CR5 0x15
99#define SVM_EXIT_WRITE_CR6 0x16
100#define SVM_EXIT_WRITE_CR7 0x17
101#define SVM_EXIT_WRITE_CR8 0x18
102#define SVM_EXIT_WRITE_CR9 0x19
103#define SVM_EXIT_WRITE_CR10 0x1A
104#define SVM_EXIT_WRITE_CR11 0x1B
105#define SVM_EXIT_WRITE_CR12 0x1C
106#define SVM_EXIT_WRITE_CR13 0x1D
107#define SVM_EXIT_WRITE_CR14 0x1E
108#define SVM_EXIT_WRITE_CR15 0x1F
109/** Read from DR0-DR15. */
110#define SVM_EXIT_READ_DR0 0x20
111#define SVM_EXIT_READ_DR1 0x21
112#define SVM_EXIT_READ_DR2 0x22
113#define SVM_EXIT_READ_DR3 0x23
114#define SVM_EXIT_READ_DR4 0x24
115#define SVM_EXIT_READ_DR5 0x25
116#define SVM_EXIT_READ_DR6 0x26
117#define SVM_EXIT_READ_DR7 0x27
118#define SVM_EXIT_READ_DR8 0x28
119#define SVM_EXIT_READ_DR9 0x29
120#define SVM_EXIT_READ_DR10 0x2A
121#define SVM_EXIT_READ_DR11 0x2B
122#define SVM_EXIT_READ_DR12 0x2C
123#define SVM_EXIT_READ_DR13 0x2D
124#define SVM_EXIT_READ_DR14 0x2E
125#define SVM_EXIT_READ_DR15 0x2F
126/** Writes to DR0-DR15. */
127#define SVM_EXIT_WRITE_DR0 0x30
128#define SVM_EXIT_WRITE_DR1 0x31
129#define SVM_EXIT_WRITE_DR2 0x32
130#define SVM_EXIT_WRITE_DR3 0x33
131#define SVM_EXIT_WRITE_DR4 0x34
132#define SVM_EXIT_WRITE_DR5 0x35
133#define SVM_EXIT_WRITE_DR6 0x36
134#define SVM_EXIT_WRITE_DR7 0x37
135#define SVM_EXIT_WRITE_DR8 0x38
136#define SVM_EXIT_WRITE_DR9 0x39
137#define SVM_EXIT_WRITE_DR10 0x3A
138#define SVM_EXIT_WRITE_DR11 0x3B
139#define SVM_EXIT_WRITE_DR12 0x3C
140#define SVM_EXIT_WRITE_DR13 0x3D
141#define SVM_EXIT_WRITE_DR14 0x3E
142#define SVM_EXIT_WRITE_DR15 0x3F
143/* Exception 0-31. */
144#define SVM_EXIT_EXCEPTION_0 0x40
145#define SVM_EXIT_EXCEPTION_1 0x41
146#define SVM_EXIT_EXCEPTION_2 0x42
147#define SVM_EXIT_EXCEPTION_3 0x43
148#define SVM_EXIT_EXCEPTION_4 0x44
149#define SVM_EXIT_EXCEPTION_5 0x45
150#define SVM_EXIT_EXCEPTION_6 0x46
151#define SVM_EXIT_EXCEPTION_7 0x47
152#define SVM_EXIT_EXCEPTION_8 0x48
153#define SVM_EXIT_EXCEPTION_9 0x49
154#define SVM_EXIT_EXCEPTION_A 0x4A
155#define SVM_EXIT_EXCEPTION_B 0x4B
156#define SVM_EXIT_EXCEPTION_C 0x4C
157#define SVM_EXIT_EXCEPTION_D 0x4D
158#define SVM_EXIT_EXCEPTION_E 0x4E
159#define SVM_EXIT_EXCEPTION_F 0x4F
160#define SVM_EXIT_EXCEPTION_10 0x50
161#define SVM_EXIT_EXCEPTION_11 0x51
162#define SVM_EXIT_EXCEPTION_12 0x52
163#define SVM_EXIT_EXCEPTION_13 0x53
164#define SVM_EXIT_EXCEPTION_14 0x54
165#define SVM_EXIT_EXCEPTION_15 0x55
166#define SVM_EXIT_EXCEPTION_16 0x56
167#define SVM_EXIT_EXCEPTION_17 0x57
168#define SVM_EXIT_EXCEPTION_18 0x58
169#define SVM_EXIT_EXCEPTION_19 0x59
170#define SVM_EXIT_EXCEPTION_1A 0x5A
171#define SVM_EXIT_EXCEPTION_1B 0x5B
172#define SVM_EXIT_EXCEPTION_1C 0x5C
173#define SVM_EXIT_EXCEPTION_1D 0x5D
174#define SVM_EXIT_EXCEPTION_1E 0x5E
175#define SVM_EXIT_EXCEPTION_1F 0x5F
176/** Physical maskable interrupt. */
177#define SVM_EXIT_INTR 0x60
178/** Non-maskable interrupt. */
179#define SVM_EXIT_NMI 0x61
180/** System Management interrupt. */
181#define SVM_EXIT_SMI 0x62
182/** Physical INIT signal. */
183#define SVM_EXIT_INIT 0x63
184/** Virtual interrupt. */
185#define SVM_EXIT_VINTR 0x64
186/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
187#define SVM_EXIT_CR0_SEL_WRITE 0x65
188/** IDTR read. */
189#define SVM_EXIT_IDTR_READ 0x66
190/** GDTR read. */
191#define SVM_EXIT_GDTR_READ 0x67
192/** LDTR read. */
193#define SVM_EXIT_LDTR_READ 0x68
194/** TR read. */
195#define SVM_EXIT_TR_READ 0x69
196/** IDTR write. */
197#define SVM_EXIT_IDTR_WRITE 0x6A
198/** GDTR write. */
199#define SVM_EXIT_GDTR_WRITE 0x6B
200/** LDTR write. */
201#define SVM_EXIT_LDTR_WRITE 0x6C
202/** TR write. */
203#define SVM_EXIT_TR_WRITE 0x6D
204/** RDTSC instruction. */
205#define SVM_EXIT_RDTSC 0x6E
206/** RDPMC instruction. */
207#define SVM_EXIT_RDPMC 0x6F
208/** PUSHF instruction. */
209#define SVM_EXIT_PUSHF 0x70
210/** POPF instruction. */
211#define SVM_EXIT_POPF 0x71
212/** CPUID instruction. */
213#define SVM_EXIT_CPUID 0x72
214/** RSM instruction. */
215#define SVM_EXIT_RSM 0x73
216/** IRET instruction. */
217#define SVM_EXIT_IRET 0x74
218/** software interrupt (INTn instructions). */
219#define SVM_EXIT_SWINT 0x75
220/** INVD instruction. */
221#define SVM_EXIT_INVD 0x76
222/** PAUSE instruction. */
223#define SVM_EXIT_PAUSE 0x77
224/** HLT instruction. */
225#define SVM_EXIT_HLT 0x78
226/** INVLPG instructions. */
227#define SVM_EXIT_INVLPG 0x79
228/** INVLPGA instruction. */
229#define SVM_EXIT_INVLPGA 0x7A
230/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
231#define SVM_EXIT_IOIO 0x7B
232/** RDMSR or WRMSR access to protected MSR. */
233#define SVM_EXIT_MSR 0x7C
234/** task switch. */
235#define SVM_EXIT_TASK_SWITCH 0x7D
236/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
237#define SVM_EXIT_FERR_FREEZE 0x7E
238/** Shutdown. */
239#define SVM_EXIT_SHUTDOWN 0x7F
240/** VMRUN instruction. */
241#define SVM_EXIT_VMRUN 0x80
242/** VMMCALL instruction. */
243#define SVM_EXIT_VMMCALL 0x81
244/** VMLOAD instruction. */
245#define SVM_EXIT_VMLOAD 0x82
246/** VMSAVE instruction. */
247#define SVM_EXIT_VMSAVE 0x83
248/** STGI instruction. */
249#define SVM_EXIT_STGI 0x84
250/** CLGI instruction. */
251#define SVM_EXIT_CLGI 0x85
252/** SKINIT instruction. */
253#define SVM_EXIT_SKINIT 0x86
254/** RDTSCP instruction. */
255#define SVM_EXIT_RDTSCP 0x87
256/** ICEBP instruction. */
257#define SVM_EXIT_ICEBP 0x88
258/** WBINVD instruction. */
259#define SVM_EXIT_WBINVD 0x89
260/** MONITOR instruction. */
261#define SVM_EXIT_MONITOR 0x8A
262/** MWAIT instruction. */
263#define SVM_EXIT_MWAIT 0x8B
264/** MWAIT instruction, when armed. */
265#define SVM_EXIT_MWAIT_ARMED 0x8C
266/** XSETBV instruction. */
267#define SVM_EXIT_XSETBV 0x8D
268/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
269#define SVM_EXIT_NPF 0x400
270/** AVIC: Virtual IPI delivery not completed. */
271#define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401
272/** AVIC: Attempted access by guest to a vAPIC register not handled by AVIC
273 * hardware. */
274#define SVM_EXIT_AVIC_NOACCEL 0x402
275
276/** The maximum possible exit value. */
277#define SVM_EXIT_MAX (SVM_EXIT_AVIC_NOACCEL)
278/** @} */
279
280
281/** @name SVMVMCB.u64ExitInfo2 for task switches
282 * @{
283 */
284/** Set to 1 if the task switch was caused by an IRET; else cleared to 0. */
285#define SVM_EXIT2_TASK_SWITCH_IRET RT_BIT_64(36)
286/** Set to 1 if the task switch was caused by a far jump; else cleared to 0. */
287#define SVM_EXIT2_TASK_SWITCH_JMP RT_BIT_64(38)
288/** Set to 1 if the task switch has an error code; else cleared to 0. */
289#define SVM_EXIT2_TASK_SWITCH_HAS_ERROR_CODE RT_BIT_64(44)
290/** The value of EFLAGS.RF that would be saved in the outgoing TSS if the task switch were not intercepted. */
291#define SVM_EXIT2_TASK_SWITCH_EFLAGS_RF RT_BIT_64(48)
292/** @} */
293
294/** @name SVMVMCB.u64ExitInfo1 for MSR accesses
295 * @{
296 */
297/** The access was a read MSR. */
298#define SVM_EXIT1_MSR_READ 0x0
299/** The access was a write MSR. */
300#define SVM_EXIT1_MSR_WRITE 0x1
301/** @} */
302
303/** @name SVMVMCB.ctrl.u32InterceptCtrl1
304 * @{
305 */
306/** 0 Intercept INTR (physical maskable interrupt). */
307#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
308/** 1 Intercept NMI. */
309#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
310/** 2 Intercept SMI. */
311#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
312/** 3 Intercept INIT. */
313#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
314/** 4 Intercept VINTR (virtual maskable interrupt). */
315#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
316/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
317#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
318/** 6 Intercept reads of IDTR. */
319#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
320/** 7 Intercept reads of GDTR. */
321#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
322/** 8 Intercept reads of LDTR. */
323#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
324/** 9 Intercept reads of TR. */
325#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
326/** 10 Intercept writes of IDTR. */
327#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
328/** 11 Intercept writes of GDTR. */
329#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
330/** 12 Intercept writes of LDTR. */
331#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
332/** 13 Intercept writes of TR. */
333#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
334/** 14 Intercept RDTSC instruction. */
335#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
336/** 15 Intercept RDPMC instruction. */
337#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
338/** 16 Intercept PUSHF instruction. */
339#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
340/** 17 Intercept POPF instruction. */
341#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
342/** 18 Intercept CPUID instruction. */
343#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
344/** 19 Intercept RSM instruction. */
345#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
346/** 20 Intercept IRET instruction. */
347#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
348/** 21 Intercept INTn instruction. */
349#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
350/** 22 Intercept INVD instruction. */
351#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
352/** 23 Intercept PAUSE instruction. */
353#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
354/** 24 Intercept HLT instruction. */
355#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
356/** 25 Intercept INVLPG instruction. */
357#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
358/** 26 Intercept INVLPGA instruction. */
359#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
360/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
361#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
362/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
363#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
364/** 29 Intercept task switches. */
365#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
366/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
367#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
368/** 31 Intercept shutdown events. */
369#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
370/** @} */
371
372
373/** @name SVMVMCB.ctrl.u32InterceptCtrl2
374 * @{
375 */
376/** 0 Intercept VMRUN instruction. */
377#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
378/** 1 Intercept VMMCALL instruction. */
379#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
380/** 2 Intercept VMLOAD instruction. */
381#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
382/** 3 Intercept VMSAVE instruction. */
383#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
384/** 4 Intercept STGI instruction. */
385#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
386/** 5 Intercept CLGI instruction. */
387#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
388/** 6 Intercept SKINIT instruction. */
389#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
390/** 7 Intercept RDTSCP instruction. */
391#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
392/** 8 Intercept ICEBP instruction. */
393#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
394/** 9 Intercept WBINVD instruction. */
395#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
396/** 10 Intercept MONITOR instruction. */
397#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
398/** 11 Intercept MWAIT instruction unconditionally. */
399#define SVM_CTRL2_INTERCEPT_MWAIT RT_BIT(11)
400/** 12 Intercept MWAIT instruction when armed. */
401#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
402/** 13 Intercept XSETBV instruction. */
403#define SVM_CTRL2_INTERCEPT_XSETBV RT_BIT(13)
404/** @} */
405
406/** @name SVMVMCB.ctrl.u64NestedPaging
407 * @{
408 */
409#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
410/** @} */
411
412/** @name SVMVMCB.ctrl.u64IntShadow
413 * @{
414 */
415#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
416/** @} */
417
418
419/** @name SVMINTCTRL.u3Type
420 * @{
421 */
422/** External or virtual interrupt. */
423#define SVM_EVENT_EXTERNAL_IRQ 0
424/** Non-maskable interrupt. */
425#define SVM_EVENT_NMI 2
426/** Exception; fault or trap. */
427#define SVM_EVENT_EXCEPTION 3
428/** Software interrupt. */
429#define SVM_EVENT_SOFTWARE_INT 4
430/** @} */
431
432
433/** @name SVMVMCB.ctrl.TLBCtrl.n.u8TLBFlush
434 * @{
435 */
436/** Flush nothing. */
437#define SVM_TLB_FLUSH_NOTHING 0
438/** Flush entire TLB (host+guest entries) */
439#define SVM_TLB_FLUSH_ENTIRE 1
440/** Flush this guest's TLB entries (by ASID) */
441#define SVM_TLB_FLUSH_SINGLE_CONTEXT 3
442/** Flush this guest's non-global TLB entries (by ASID) */
443#define SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS 7
444/** @} */
445
446
447/**
448 * SVM Selector type; includes hidden parts.
449 */
450typedef struct
451{
452 uint16_t u16Sel;
453 uint16_t u16Attr;
454 uint32_t u32Limit;
455 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
456} SVMSEL;
457AssertCompileSize(SVMSEL, 16);
458
459/**
460 * SVM GDTR/IDTR type.
461 */
462typedef struct
463{
464 uint16_t u16Reserved1;
465 uint16_t u16Reserved2;
466 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
467 uint64_t u64Base;
468} SVMGDTR;
469AssertCompileSize(SVMGDTR, 16);
470typedef SVMGDTR SVMIDTR;
471
472/**
473 * SVM Event injection structure (EVENTINJ and EXITINTINFO).
474 */
475typedef union
476{
477 struct
478 {
479 uint32_t u8Vector : 8;
480 uint32_t u3Type : 3;
481 uint32_t u1ErrorCodeValid : 1;
482 uint32_t u19Reserved : 19;
483 uint32_t u1Valid : 1;
484 uint32_t u32ErrorCode : 32;
485 } n;
486 uint64_t u;
487} SVMEVENT;
488/** Pointer to the SVMEVENT union. */
489typedef SVMEVENT *PSVMEVENT;
490
491/**
492 * SVM Interrupt control structure (Virtual Interrupt Control).
493 */
494typedef union
495{
496 struct
497 {
498 uint32_t u8VTPR : 8; /* V_TPR */
499 uint32_t u1VIrqValid : 1; /* V_IRQ */
500 uint32_t u7Reserved : 7;
501 uint32_t u4VIrqPriority : 4; /* V_INTR_PRIO */
502 uint32_t u1IgnoreTPR : 1; /* V_IGN_TPR */
503 uint32_t u3Reserved : 3;
504 uint32_t u1VIrqMasking : 1; /* V_INTR_MASKING */
505 uint32_t u6Reserved : 6;
506 uint32_t u1AvicEnable : 1;
507 uint32_t u8VIrqVector : 8; /* V_INTR_VECTOR */
508 uint32_t u24Reserved : 24;
509 } n;
510 uint64_t u;
511} SVMINTCTRL;
512
513/**
514 * SVM TLB control structure.
515 */
516typedef union
517{
518 struct
519 {
520 uint32_t u32ASID : 32;
521 uint32_t u8TLBFlush : 8;
522 uint32_t u24Reserved : 24;
523 } n;
524 uint64_t u;
525} SVMTLBCTRL;
526
527/**
528 * SVM IOIO exit structure (EXITINFO1 for IOIO intercepts).
529 */
530typedef union
531{
532 struct
533 {
534 uint32_t u1Type : 1; /**< 0 = out, 1 = in */
535 uint32_t u1Reserved : 1;
536 uint32_t u1STR : 1;
537 uint32_t u1REP : 1;
538 uint32_t u1OP8 : 1;
539 uint32_t u1OP16 : 1;
540 uint32_t u1OP32 : 1;
541 uint32_t u1ADDR16 : 1;
542 uint32_t u1ADDR32 : 1;
543 uint32_t u1ADDR64 : 1;
544 uint32_t u6Reserved : 6;
545 uint32_t u16Port : 16;
546 } n;
547 uint32_t u;
548} SVMIOIOEXIT;
549
550/** @name SVMIOIOEXIT.u1Type
551 * @{ */
552/** IO write. */
553#define SVM_IOIO_WRITE 0
554/** IO read. */
555#define SVM_IOIO_READ 1
556/** @}*/
557
558/**
559 * SVM nested paging structure.
560 */
561typedef union
562{
563 struct
564 {
565 uint32_t u1NestedPaging : 1; /**< enabled/disabled */
566 } n;
567 uint64_t u;
568} SVMNPCTRL;
569
570/**
571 * SVM AVIC.
572 */
573typedef union
574{
575 struct
576 {
577 uint64_t u12Reserved1 : 12;
578 uint64_t u40Addr : 40;
579 uint64_t u12Reserved2 : 12;
580 } n;
581 uint64_t u;
582} SVMAVIC;
583AssertCompileSize(SVMAVIC, 8);
584
585/**
586 * SVM AVIC PHYSICAL_TABLE pointer.
587 */
588typedef union
589{
590 struct
591 {
592 uint64_t u8LastGuestCoreId : 8;
593 uint64_t u4Reserved : 4;
594 uint64_t u40Addr : 40;
595 uint64_t u12Reserved : 12;
596 } n;
597 uint64_t u;
598} SVMAVICPHYS;
599AssertCompileSize(SVMAVICPHYS, 8);
600
601/**
602 * SVM VM Control Block. (VMCB)
603 */
604typedef struct SVMVMCB
605{
606 /** Control Area. */
607 struct
608 {
609 /** Offset 0x00 - Intercept reads of CR0-15. */
610 uint16_t u16InterceptRdCRx;
611 /** Offset 0x02 - Intercept writes to CR0-15. */
612 uint16_t u16InterceptWrCRx;
613 /** Offset 0x04 - Intercept reads of DR0-15. */
614 uint16_t u16InterceptRdDRx;
615 /** Offset 0x06 - Intercept writes to DR0-15. */
616 uint16_t u16InterceptWrDRx;
617 /** Offset 0x08 - Intercept exception vectors 0-31. */
618 uint32_t u32InterceptException;
619 /** Offset 0x0C - Intercept control field 1. */
620 uint32_t u32InterceptCtrl1;
621 /** Offset 0x10 - Intercept control field 2. */
622 uint32_t u32InterceptCtrl2;
623 /** Offset 0x14-0x3F - Reserved. */
624 uint8_t u8Reserved[0x3c - 0x14];
625 /** Offset 0x3c - PAUSE filter threshold. */
626 uint16_t u16PauseFilterThreshold;
627 /** Offset 0x3e - PAUSE intercept filter count. */
628 uint16_t u16PauseFilterCount;
629 /** Offset 0x40 - Physical address of IOPM. */
630 uint64_t u64IOPMPhysAddr;
631 /** Offset 0x48 - Physical address of MSRPM. */
632 uint64_t u64MSRPMPhysAddr;
633 /** Offset 0x50 - TSC Offset. */
634 uint64_t u64TSCOffset;
635 /** Offset 0x58 - TLB control field. */
636 SVMTLBCTRL TLBCtrl;
637 /** Offset 0x60 - Interrupt control field. */
638 SVMINTCTRL IntCtrl;
639 /** Offset 0x68 - Interrupt shadow. */
640 uint64_t u64IntShadow;
641 /** Offset 0x70 - Exit code. */
642 uint64_t u64ExitCode;
643 /** Offset 0x78 - Exit info 1. */
644 uint64_t u64ExitInfo1;
645 /** Offset 0x80 - Exit info 2. */
646 uint64_t u64ExitInfo2;
647 /** Offset 0x88 - Exit Interrupt info. */
648 SVMEVENT ExitIntInfo;
649 /** Offset 0x90 - Nested Paging. */
650 SVMNPCTRL NestedPaging;
651 /** Offset 0x98 - AVIC APIC BAR. */
652 SVMAVIC AvicBar;
653 /** Offset 0xA0-0xA7 - Reserved. */
654 uint8_t u8Reserved2[0xA8-0xA0];
655 /** Offset 0xA8 - Event injection. */
656 SVMEVENT EventInject;
657 /** Offset 0xB0 - Host CR3 for nested paging. */
658 uint64_t u64NestedPagingCR3;
659 /** Offset 0xB8 - LBR Virtualization. */
660 uint64_t u64LBRVirt;
661 /** Offset 0xC0 - VMCB Clean Bits. */
662 uint64_t u64VmcbCleanBits;
663 /** Offset 0xC8 - Next sequential instruction pointer. */
664 uint64_t u64NextRIP;
665 /** Offset 0xD0 - Number of bytes fetched. */
666 uint8_t cbInstrFetched;
667 /** Offset 0xD1 - Fetched bytes. */
668 uint8_t abInstr[15];
669 /** Offset 0xE0 - AVIC APIC_BACKING_PAGE pointer. */
670 SVMAVIC AvicBackingPagePtr;
671 /** Offset 0xE8-0xEF - Reserved. */
672 uint8_t u8Reserved3[0xF0 - 0xE8];
673 /** Offset 0xF0 - AVIC LOGICAL_TABLE pointer. */
674 SVMAVIC AvicLogicalTablePtr;
675 /** Offset 0xF8 - AVIC PHYSICAL_TABLE pointer. */
676 SVMAVICPHYS AvicPhysicalTablePtr;
677 } ctrl;
678
679 /** Offset 0x100-0x3FF - Reserved. */
680 uint8_t u8Reserved3[0x400-0x100];
681
682 /** State Save Area. Starts at offset 0x400. */
683 struct
684 {
685 /** Offset 0x400 - Guest ES register + hidden parts. */
686 SVMSEL ES;
687 /** Offset 0x410 - Guest CS register + hidden parts. */
688 SVMSEL CS;
689 /** Offset 0x420 - Guest SS register + hidden parts. */
690 SVMSEL SS;
691 /** Offset 0x430 - Guest DS register + hidden parts. */
692 SVMSEL DS;
693 /** Offset 0x440 - Guest FS register + hidden parts. */
694 SVMSEL FS;
695 /** Offset 0x450 - Guest GS register + hidden parts. */
696 SVMSEL GS;
697 /** Offset 0x460 - Guest GDTR register. */
698 SVMGDTR GDTR;
699 /** Offset 0x470 - Guest LDTR register + hidden parts. */
700 SVMSEL LDTR;
701 /** Offset 0x480 - Guest IDTR register. */
702 SVMIDTR IDTR;
703 /** Offset 0x490 - Guest TR register + hidden parts. */
704 SVMSEL TR;
705 /** Offset 0x4A0-0x4CA - Reserved. */
706 uint8_t u8Reserved4[0x4CB-0x4A0];
707 /** Offset 0x4CB - CPL. */
708 uint8_t u8CPL;
709 /** Offset 0x4CC-0x4CF - Reserved. */
710 uint8_t u8Reserved5[0x4D0-0x4CC];
711 /** Offset 0x4D0 - EFER. */
712 uint64_t u64EFER;
713 /** Offset 0x4D8-0x547 - Reserved. */
714 uint8_t u8Reserved6[0x548-0x4D8];
715 /** Offset 0x548 - CR4. */
716 uint64_t u64CR4;
717 /** Offset 0x550 - CR3. */
718 uint64_t u64CR3;
719 /** Offset 0x558 - CR0. */
720 uint64_t u64CR0;
721 /** Offset 0x560 - DR7. */
722 uint64_t u64DR7;
723 /** Offset 0x568 - DR6. */
724 uint64_t u64DR6;
725 /** Offset 0x570 - RFLAGS. */
726 uint64_t u64RFlags;
727 /** Offset 0x578 - RIP. */
728 uint64_t u64RIP;
729 /** Offset 0x580-0x5D7 - Reserved. */
730 uint8_t u8Reserved7[0x5D8-0x580];
731 /** Offset 0x5D8 - RSP. */
732 uint64_t u64RSP;
733 /** Offset 0x5E0-0x5F7 - Reserved. */
734 uint8_t u8Reserved8[0x5F8-0x5E0];
735 /** Offset 0x5F8 - RAX. */
736 uint64_t u64RAX;
737 /** Offset 0x600 - STAR. */
738 uint64_t u64STAR;
739 /** Offset 0x608 - LSTAR. */
740 uint64_t u64LSTAR;
741 /** Offset 0x610 - CSTAR. */
742 uint64_t u64CSTAR;
743 /** Offset 0x618 - SFMASK. */
744 uint64_t u64SFMASK;
745 /** Offset 0x620 - KernelGSBase. */
746 uint64_t u64KernelGSBase;
747 /** Offset 0x628 - SYSENTER_CS. */
748 uint64_t u64SysEnterCS;
749 /** Offset 0x630 - SYSENTER_ESP. */
750 uint64_t u64SysEnterESP;
751 /** Offset 0x638 - SYSENTER_EIP. */
752 uint64_t u64SysEnterEIP;
753 /** Offset 0x640 - CR2. */
754 uint64_t u64CR2;
755 /** Offset 0x648-0x667 - Reserved. */
756 uint8_t u8Reserved9[0x668-0x648];
757 /** Offset 0x668 - G_PAT. */
758 uint64_t u64GPAT;
759 /** Offset 0x670 - DBGCTL. */
760 uint64_t u64DBGCTL;
761 /** Offset 0x678 - BR_FROM. */
762 uint64_t u64BR_FROM;
763 /** Offset 0x680 - BR_TO. */
764 uint64_t u64BR_TO;
765 /** Offset 0x688 - LASTEXCPFROM. */
766 uint64_t u64LASTEXCPFROM;
767 /** Offset 0x690 - LASTEXCPTO. */
768 uint64_t u64LASTEXCPTO;
769 } guest;
770
771 /** Offset 0x698-0xFFF- Reserved. */
772 uint8_t u8Reserved10[0x1000-0x698];
773} SVMVMCB;
774/** Pointer to the SVMVMCB structure. */
775typedef SVMVMCB *PSVMVMCB;
776AssertCompileMemberOffset(SVMVMCB, ctrl, 0x00);
777AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdCRx, 0x00);
778AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptWrCRx, 0x02);
779AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptRdDRx, 0x04);
780AssertCompileMemberOffset(SVMVMCB, ctrl.u16InterceptWrDRx, 0x06);
781AssertCompileMemberOffset(SVMVMCB, ctrl.u32InterceptException, 0x08);
782AssertCompileMemberOffset(SVMVMCB, ctrl.u32InterceptCtrl1, 0x0C);
783AssertCompileMemberOffset(SVMVMCB, ctrl.u32InterceptCtrl2, 0x10);
784AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved, 0x14);
785AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterThreshold, 0x3c);
786AssertCompileMemberOffset(SVMVMCB, ctrl.u16PauseFilterCount, 0x3e);
787AssertCompileMemberOffset(SVMVMCB, ctrl.u64IOPMPhysAddr, 0x40);
788AssertCompileMemberOffset(SVMVMCB, ctrl.u64MSRPMPhysAddr, 0x48);
789AssertCompileMemberOffset(SVMVMCB, ctrl.u64TSCOffset, 0x50);
790AssertCompileMemberOffset(SVMVMCB, ctrl.TLBCtrl, 0x58);
791AssertCompileMemberOffset(SVMVMCB, ctrl.IntCtrl, 0x60);
792AssertCompileMemberOffset(SVMVMCB, ctrl.u64IntShadow, 0x68);
793AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitCode, 0x70);
794AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitInfo1, 0x78);
795AssertCompileMemberOffset(SVMVMCB, ctrl.u64ExitInfo2, 0x80);
796AssertCompileMemberOffset(SVMVMCB, ctrl.ExitIntInfo, 0x88);
797AssertCompileMemberOffset(SVMVMCB, ctrl.NestedPaging, 0x90);
798AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBar, 0x98);
799AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved2, 0xA0);
800AssertCompileMemberOffset(SVMVMCB, ctrl.EventInject, 0xA8);
801AssertCompileMemberOffset(SVMVMCB, ctrl.u64NestedPagingCR3, 0xB0);
802AssertCompileMemberOffset(SVMVMCB, ctrl.u64LBRVirt, 0xB8);
803AssertCompileMemberOffset(SVMVMCB, ctrl.u64VmcbCleanBits, 0xC0);
804AssertCompileMemberOffset(SVMVMCB, ctrl.u64NextRIP, 0xC8);
805AssertCompileMemberOffset(SVMVMCB, ctrl.cbInstrFetched, 0xD0);
806AssertCompileMemberOffset(SVMVMCB, ctrl.abInstr, 0xD1);
807AssertCompileMemberOffset(SVMVMCB, ctrl.AvicBackingPagePtr, 0xE0);
808AssertCompileMemberOffset(SVMVMCB, ctrl.u8Reserved3, 0xE8);
809AssertCompileMemberOffset(SVMVMCB, ctrl.AvicLogicalTablePtr, 0xF0);
810AssertCompileMemberOffset(SVMVMCB, ctrl.AvicPhysicalTablePtr, 0xF8);
811AssertCompileMemberOffset(SVMVMCB, u8Reserved3, 0x100);
812AssertCompileMemberOffset(SVMVMCB, guest, 0x400);
813AssertCompileMemberOffset(SVMVMCB, guest.ES, 0x400);
814AssertCompileMemberOffset(SVMVMCB, guest.CS, 0x410);
815AssertCompileMemberOffset(SVMVMCB, guest.SS, 0x420);
816AssertCompileMemberOffset(SVMVMCB, guest.DS, 0x430);
817AssertCompileMemberOffset(SVMVMCB, guest.FS, 0x440);
818AssertCompileMemberOffset(SVMVMCB, guest.GS, 0x450);
819AssertCompileMemberOffset(SVMVMCB, guest.GDTR, 0x460);
820AssertCompileMemberOffset(SVMVMCB, guest.LDTR, 0x470);
821AssertCompileMemberOffset(SVMVMCB, guest.IDTR, 0x480);
822AssertCompileMemberOffset(SVMVMCB, guest.TR, 0x490);
823AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved4, 0x4A0);
824AssertCompileMemberOffset(SVMVMCB, guest.u8CPL, 0x4CB);
825AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved5, 0x4CC);
826AssertCompileMemberOffset(SVMVMCB, guest.u64EFER, 0x4D0);
827AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved6, 0x4D8);
828AssertCompileMemberOffset(SVMVMCB, guest.u64CR4, 0x548);
829AssertCompileMemberOffset(SVMVMCB, guest.u64CR3, 0x550);
830AssertCompileMemberOffset(SVMVMCB, guest.u64CR0, 0x558);
831AssertCompileMemberOffset(SVMVMCB, guest.u64DR7, 0x560);
832AssertCompileMemberOffset(SVMVMCB, guest.u64DR6, 0x568);
833AssertCompileMemberOffset(SVMVMCB, guest.u64RFlags, 0x570);
834AssertCompileMemberOffset(SVMVMCB, guest.u64RIP, 0x578);
835AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved7, 0x580);
836AssertCompileMemberOffset(SVMVMCB, guest.u64RSP, 0x5D8);
837AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved8, 0x5E0);
838AssertCompileMemberOffset(SVMVMCB, guest.u64RAX, 0x5F8);
839AssertCompileMemberOffset(SVMVMCB, guest.u64STAR, 0x600);
840AssertCompileMemberOffset(SVMVMCB, guest.u64LSTAR, 0x608);
841AssertCompileMemberOffset(SVMVMCB, guest.u64CSTAR, 0x610);
842AssertCompileMemberOffset(SVMVMCB, guest.u64SFMASK, 0x618);
843AssertCompileMemberOffset(SVMVMCB, guest.u64KernelGSBase, 0x620);
844AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterCS, 0x628);
845AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterESP, 0x630);
846AssertCompileMemberOffset(SVMVMCB, guest.u64SysEnterEIP, 0x638);
847AssertCompileMemberOffset(SVMVMCB, guest.u64CR2, 0x640);
848AssertCompileMemberOffset(SVMVMCB, guest.u8Reserved9, 0x648);
849AssertCompileMemberOffset(SVMVMCB, guest.u64GPAT, 0x668);
850AssertCompileMemberOffset(SVMVMCB, guest.u64DBGCTL, 0x670);
851AssertCompileMemberOffset(SVMVMCB, guest.u64BR_FROM, 0x678);
852AssertCompileMemberOffset(SVMVMCB, guest.u64BR_TO, 0x680);
853AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPFROM, 0x688);
854AssertCompileMemberOffset(SVMVMCB, guest.u64LASTEXCPTO, 0x690);
855AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
856AssertCompileSize(SVMVMCB, 0x1000);
857
858#ifdef IN_RING0
859VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
860#endif /* IN_RING0 */
861
862/** @} */
863
864#endif
865
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